Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T46,T47
1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T46,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T46,T47

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T46,T47
1	0	Covered	T31,T38,T41
1	1	Covered	T31,T46,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T46,T47
0	1	Covered	T31,T46,T47
1	0	Covered	T31,T38,T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T49,T130
0	1	Covered	T41,T49,T130
1	0	Covered	T31,T255

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T41,T49
1	-	Covered	T41,T49,T130

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T46,T47
0	1	Covered	T31,T46,T47
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T46,T47
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T31,T46,T47
IdleSt	0	-	-	-	-	-	-	Covered	T31,T46,T47
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T93,T233,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T46,T47
DetectSt	-	-	-	-	1	-	-	Covered	T31,T46,T47
DetectSt	-	-	-	-	0	1	-	Covered	T31,T41,T49
DetectSt	-	-	-	-	0	0	-	Covered	T31,T46,T47
StableSt	-	-	-	-	-	-	1	Covered	T31,T41,T49
StableSt	-	-	-	-	-	-	0	Covered	T41,T49,T130
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	2841	0	0
CntIncr_A	7120944	101622	0	0
CntNoWrap_A	7120944	6419005	0	0
DetectStDropOut_A	7120944	419	0	0
DetectedOut_A	7120944	69458	0	0
DetectedPulseOut_A	7120944	724	0	0
DisabledIdleSt_A	7120944	5953390	0	0
DisabledNoDetection_A	7120944	5955764	0	0
EnterDebounceSt_A	7120944	1439	0	0
EnterDetectSt_A	7120944	1403	0	0
EnterStableSt_A	7120944	724	0	0
PulseIsPulse_A	7120944	724	0	0
StayInStableSt	7120944	68643	0	0
gen_high_event_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	611	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	2841	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	44	0	0
T38	0	50	0	0
T41	0	52	0	0
T46	4767	28	0	0
T47	0	40	0	0
T49	0	30	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T93	0	12	0	0
T103	0	14	0	0
T104	0	22	0	0
T130	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	101622	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	1228	0	0
T38	0	1489	0	0
T41	0	1872	0	0
T46	4767	598	0	0
T47	0	881	0	0
T49	0	885	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T93	0	360	0	0
T103	0	417	0	0
T104	0	622	0	0
T130	0	774	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6419005	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8352	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	419	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	2	0	0
T38	0	9	0	0
T46	4767	14	0	0
T47	0	20	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T82	0	25	0	0
T103	0	7	0	0
T104	0	11	0	0
T105	0	9	0	0
T106	0	19	0	0
T184	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	69458	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	5	0	0
T41	0	1965	0	0
T46	4767	0	0	0
T49	0	1073	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T83	0	1577	0	0
T130	0	385	0	0
T229	0	390	0	0
T236	0	628	0	0
T237	0	155	0	0
T238	0	622	0	0
T250	0	144	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	724	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	5	0	0
T41	0	26	0	0
T46	4767	0	0	0
T49	0	15	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T83	0	9	0	0
T130	0	9	0	0
T229	0	11	0	0
T236	0	7	0	0
T237	0	6	0	0
T238	0	6	0	0
T250	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5953390	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	5444	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5955764	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	5445	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1439	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	22	0	0
T38	0	25	0	0
T41	0	26	0	0
T46	4767	14	0	0
T47	0	20	0	0
T49	0	15	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T93	0	12	0	0
T103	0	7	0	0
T104	0	11	0	0
T130	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1403	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	22	0	0
T38	0	25	0	0
T41	0	26	0	0
T46	4767	14	0	0
T47	0	20	0	0
T49	0	15	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T82	0	28	0	0
T103	0	7	0	0
T104	0	11	0	0
T130	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	724	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	5	0	0
T41	0	26	0	0
T46	4767	0	0	0
T49	0	15	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T83	0	9	0	0
T130	0	9	0	0
T229	0	11	0	0
T236	0	7	0	0
T237	0	6	0	0
T238	0	6	0	0
T250	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	724	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	5	0	0
T41	0	26	0	0
T46	4767	0	0	0
T49	0	15	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T83	0	9	0	0
T130	0	9	0	0
T229	0	11	0	0
T236	0	7	0	0
T237	0	6	0	0
T238	0	6	0	0
T250	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	68643	0	0
T37	1149	0	0	0
T41	26032	1935	0	0
T49	10795	1057	0	0
T83	0	1567	0	0
T98	3569	0	0	0
T130	0	376	0	0
T135	446	0	0	0
T173	406	0	0	0
T174	577	0	0	0
T175	524	0	0	0
T229	0	379	0	0
T236	0	620	0	0
T237	0	148	0	0
T238	0	616	0	0
T250	0	141	0	0
T256	0	1048	0	0
T257	3758	0	0	0
T258	402	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	611	0	0
T37	1149	0	0	0
T41	26032	22	0	0
T49	10795	14	0	0
T83	0	8	0	0
T98	3569	0	0	0
T130	0	9	0	0
T135	446	0	0	0
T173	406	0	0	0
T174	577	0	0	0
T175	524	0	0	0
T229	0	11	0	0
T236	0	6	0	0
T237	0	5	0	0
T238	0	6	0	0
T250	0	3	0	0
T256	0	6	0	0
T257	3758	0	0	0
T258	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T16,T46
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T16,T46
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T16,T18,T95

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T16,T18,T95

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T16,T18,T95

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T16,T18
1	0	Covered	T31,T15,T16
1	1	Covered	T16,T18,T95

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T95
0	1	Covered	T18,T136,T240
1	0	Covered	T76,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T95,T39
0	1	Covered	T16,T95,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T95,T39
1	-	Covered	T16,T95,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T95
0	1	Covered	T16,T18,T95
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T95
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T95
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T95
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T42,T259
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T95
DetectSt	-	-	-	-	1	-	-	Covered	T18,T136,T240
DetectSt	-	-	-	-	0	1	-	Covered	T16,T95,T39
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T95
StableSt	-	-	-	-	-	-	1	Covered	T16,T95,T39
StableSt	-	-	-	-	-	-	0	Covered	T16,T95,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	953	0	0
CntIncr_A	7120944	56444	0	0
CntNoWrap_A	7120944	6420893	0	0
DetectStDropOut_A	7120944	93	0	0
DetectedOut_A	7120944	14481	0	0
DetectedPulseOut_A	7120944	350	0	0
DisabledIdleSt_A	7120944	6011537	0	0
DisabledNoDetection_A	7120944	6013383	0	0
EnterDebounceSt_A	7120944	506	0	0
EnterDetectSt_A	7120944	448	0	0
EnterStableSt_A	7120944	350	0	0
PulseIsPulse_A	7120944	350	0	0
StayInStableSt	7120944	14111	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	329	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	953	0	0
T16	14020	8	0	0
T17	601	0	0	0
T18	30837	25	0	0
T39	0	22	0	0
T40	0	6	0	0
T41	0	8	0	0
T42	0	9	0	0
T46	4767	0	0	0
T49	0	4	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	4	0	0
T102	526	0	0	0
T125	0	4	0	0
T136	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	56444	0	0
T16	14020	412	0	0
T17	601	0	0	0
T18	30837	1678	0	0
T39	0	1276	0	0
T40	0	324	0	0
T41	0	180	0	0
T42	0	711	0	0
T46	4767	0	0	0
T49	0	124	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	304	0	0
T102	526	0	0	0
T125	0	494	0	0
T136	0	371	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6420893	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	93	0	0
T18	30837	11	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T43	106976	0	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T136	0	1	0	0
T163	0	4	0	0
T208	0	3	0	0
T240	0	6	0	0
T253	0	2	0	0
T260	0	3	0	0
T261	0	12	0	0
T262	0	6	0	0
T263	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	14481	0	0
T16	14020	68	0	0
T17	601	0	0	0
T39	0	139	0	0
T40	0	279	0	0
T41	0	301	0	0
T42	0	80	0	0
T46	4767	0	0	0
T49	0	318	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T74	0	72	0	0
T95	14733	192	0	0
T102	526	0	0	0
T125	0	39	0	0
T154	0	184	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	350	0	0
T16	14020	4	0	0
T17	601	0	0	0
T39	0	11	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	4	0	0
T46	4767	0	0	0
T49	0	2	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T74	0	7	0	0
T95	14733	2	0	0
T102	526	0	0	0
T125	0	2	0	0
T154	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6011537	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8391	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6013383	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8393	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	506	0	0
T16	14020	4	0	0
T17	601	0	0	0
T18	30837	14	0	0
T39	0	11	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	5	0	0
T46	4767	0	0	0
T49	0	2	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	2	0	0
T102	526	0	0	0
T125	0	2	0	0
T136	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	448	0	0
T16	14020	4	0	0
T17	601	0	0	0
T18	30837	11	0	0
T39	0	11	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	4	0	0
T46	4767	0	0	0
T49	0	2	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	2	0	0
T102	526	0	0	0
T125	0	2	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	350	0	0
T16	14020	4	0	0
T17	601	0	0	0
T39	0	11	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	4	0	0
T46	4767	0	0	0
T49	0	2	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T74	0	7	0	0
T95	14733	2	0	0
T102	526	0	0	0
T125	0	2	0	0
T154	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	350	0	0
T16	14020	4	0	0
T17	601	0	0	0
T39	0	11	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	4	0	0
T46	4767	0	0	0
T49	0	2	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T74	0	7	0	0
T95	14733	2	0	0
T102	526	0	0	0
T125	0	2	0	0
T154	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	14111	0	0
T16	14020	64	0	0
T17	601	0	0	0
T39	0	128	0	0
T40	0	276	0	0
T41	0	297	0	0
T42	0	76	0	0
T46	4767	0	0	0
T49	0	316	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T74	0	65	0	0
T95	14733	190	0	0
T102	526	0	0	0
T125	0	37	0	0
T154	0	182	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	329	0	0
T16	14020	4	0	0
T17	601	0	0	0
T39	0	11	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	4	0	0
T46	4767	0	0	0
T49	0	2	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T74	0	7	0	0
T95	14733	2	0	0
T102	526	0	0	0
T125	0	2	0	0
T154	0	2	0	0