Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1222013153	11375	0	0
auto_block_debounce_ctl_rd_A	1222013153	2310	0	0
auto_block_out_ctl_rd_A	1222013153	3029	0	0
com_det_ctl_0_rd_A	1222013153	4341	0	0
com_det_ctl_1_rd_A	1222013153	4731	0	0
com_det_ctl_2_rd_A	1222013153	4509	0	0
com_det_ctl_3_rd_A	1222013153	4397	0	0
com_out_ctl_0_rd_A	1222013153	5204	0	0
com_out_ctl_1_rd_A	1222013153	5009	0	0
com_out_ctl_2_rd_A	1222013153	5121	0	0
com_out_ctl_3_rd_A	1222013153	5307	0	0
com_pre_det_ctl_0_rd_A	1222013153	1542	0	0
com_pre_det_ctl_1_rd_A	1222013153	1666	0	0
com_pre_det_ctl_2_rd_A	1222013153	1559	0	0
com_pre_det_ctl_3_rd_A	1222013153	1637	0	0
com_pre_sel_ctl_0_rd_A	1222013153	5581	0	0
com_pre_sel_ctl_1_rd_A	1222013153	5502	0	0
com_pre_sel_ctl_2_rd_A	1222013153	5545	0	0
com_pre_sel_ctl_3_rd_A	1222013153	5663	0	0
com_sel_ctl_0_rd_A	1222013153	5578	0	0
com_sel_ctl_1_rd_A	1222013153	5621	0	0
com_sel_ctl_2_rd_A	1222013153	5546	0	0
com_sel_ctl_3_rd_A	1222013153	5283	0	0
ec_rst_ctl_rd_A	1222013153	2825	0	0
intr_enable_rd_A	1222013153	2584	0	0
key_intr_ctl_rd_A	1222013153	4285	0	0
key_intr_debounce_ctl_rd_A	1222013153	1654	0	0
key_invert_ctl_rd_A	1222013153	6612	0	0
pin_allowed_ctl_rd_A	1222013153	7818	0	0
pin_out_ctl_rd_A	1222013153	6189	0	0
pin_out_value_rd_A	1222013153	6010	0	0
regwen_rd_A	1222013153	2046	0	0
ulp_ac_debounce_ctl_rd_A	1222013153	1688	0	0
ulp_ctl_rd_A	1222013153	1763	0	0
ulp_lid_debounce_ctl_rd_A	1222013153	1859	0	0
ulp_pwrb_debounce_ctl_rd_A	1222013153	1620	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	11375	0	0
T2	292897	4	0	0
T3	425915	6	0	0
T4	749622	0	0	0
T21	200944	0	0	0
T22	202946	2	0	0
T23	48610	0	0	0
T24	52815	355	0	0
T25	50379	524	0	0
T26	89209	0	0	0
T35	50828	0	0	0
T264	0	678	0	0
T266	0	474	0	0
T267	0	776	0	0
T268	0	379	0	0
T269	0	290	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	2310	0	0
T3	425915	53	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	119	0	0
T35	50828	0	0	0
T36	0	7	0	0
T268	0	9	0	0
T280	0	15	0	0
T281	0	54	0	0
T282	0	129	0	0
T283	0	24	0	0
T284	0	1	0	0
T285	0	7	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	3029	0	0
T3	425915	78	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	274	0	0
T35	50828	0	0	0
T36	0	14	0	0
T268	0	10	0	0
T280	0	64	0	0
T281	0	172	0	0
T282	0	228	0	0
T283	0	7	0	0
T284	0	10	0	0
T285	0	4	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	4341	0	0
T3	425915	43	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	65	0	0
T35	50828	0	0	0
T36	0	4	0	0
T268	0	3	0	0
T280	0	9	0	0
T281	0	32	0	0
T282	0	67	0	0
T283	0	3	0	0
T284	0	4	0	0
T285	0	8	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	4731	0	0
T3	425915	31	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	80	0	0
T35	50828	0	0	0
T36	0	5	0	0
T280	0	10	0	0
T281	0	27	0	0
T282	0	83	0	0
T283	0	11	0	0
T285	0	2	0	0
T286	0	36	0	0
T287	0	14	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	4509	0	0
T3	425915	52	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	64	0	0
T35	50828	0	0	0
T36	0	15	0	0
T280	0	8	0	0
T281	0	41	0	0
T282	0	54	0	0
T283	0	2	0	0
T285	0	2	0	0
T286	0	45	0	0
T287	0	5	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	4397	0	0
T3	425915	33	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	94	0	0
T35	50828	0	0	0
T36	0	17	0	0
T268	0	8	0	0
T280	0	7	0	0
T281	0	18	0	0
T282	0	73	0	0
T284	0	7	0	0
T286	0	26	0	0
T287	0	25	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5204	0	0
T3	425915	94	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	138	0	0
T35	50828	0	0	0
T36	0	16	0	0
T280	0	8	0	0
T281	0	72	0	0
T282	0	184	0	0
T283	0	42	0	0
T284	0	6	0	0
T285	0	1	0	0
T286	0	27	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5009	0	0
T3	425915	101	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	159	0	0
T35	50828	0	0	0
T36	0	7	0	0
T268	0	9	0	0
T280	0	14	0	0
T281	0	71	0	0
T282	0	170	0	0
T283	0	8	0	0
T284	0	10	0	0
T285	0	5	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5121	0	0
T3	425915	68	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	200	0	0
T35	50828	0	0	0
T36	0	35	0	0
T280	0	16	0	0
T281	0	96	0	0
T282	0	182	0	0
T283	0	10	0	0
T284	0	6	0	0
T285	0	6	0	0
T286	0	8	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5307	0	0
T3	425915	71	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	202	0	0
T35	50828	0	0	0
T36	0	14	0	0
T268	0	1	0	0
T280	0	31	0	0
T281	0	99	0	0
T282	0	226	0	0
T283	0	35	0	0
T284	0	15	0	0
T285	0	5	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	1542	0	0
T3	425915	25	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	72	0	0
T35	50828	0	0	0
T36	0	7	0	0
T268	0	9	0	0
T280	0	2	0	0
T281	0	30	0	0
T282	0	88	0	0
T283	0	44	0	0
T285	0	2	0	0
T286	0	39	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	1666	0	0
T3	425915	28	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	93	0	0
T35	50828	0	0	0
T36	0	8	0	0
T280	0	3	0	0
T281	0	28	0	0
T282	0	78	0	0
T283	0	12	0	0
T284	0	9	0	0
T285	0	6	0	0
T286	0	42	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	1559	0	0
T3	425915	30	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	75	0	0
T35	50828	0	0	0
T36	0	8	0	0
T268	0	16	0	0
T280	0	5	0	0
T281	0	43	0	0
T282	0	44	0	0
T283	0	22	0	0
T284	0	7	0	0
T285	0	9	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	1637	0	0
T3	425915	25	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	75	0	0
T35	50828	0	0	0
T36	0	7	0	0
T268	0	5	0	0
T280	0	9	0	0
T281	0	41	0	0
T282	0	93	0	0
T283	0	13	0	0
T285	0	5	0	0
T286	0	24	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5581	0	0
T3	425915	85	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	220	0	0
T35	50828	0	0	0
T36	0	22	0	0
T268	0	1	0	0
T280	0	4	0	0
T281	0	159	0	0
T282	0	271	0	0
T285	0	6	0	0
T286	0	38	0	0
T287	0	4	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5502	0	0
T3	425915	116	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	205	0	0
T35	50828	0	0	0
T36	0	26	0	0
T280	0	20	0	0
T281	0	202	0	0
T282	0	158	0	0
T283	0	22	0	0
T284	0	17	0	0
T286	0	18	0	0
T287	0	24	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5545	0	0
T3	425915	131	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	285	0	0
T35	50828	0	0	0
T36	0	38	0	0
T268	0	3	0	0
T280	0	22	0	0
T281	0	86	0	0
T282	0	324	0	0
T283	0	14	0	0
T284	0	3	0	0
T286	0	8	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5663	0	0
T3	425915	152	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	261	0	0
T35	50828	0	0	0
T36	0	41	0	0
T280	0	27	0	0
T281	0	102	0	0
T282	0	275	0	0
T283	0	19	0	0
T285	0	8	0	0
T286	0	52	0	0
T287	0	7	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5578	0	0
T3	425915	114	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	265	0	0
T35	50828	0	0	0
T36	0	25	0	0
T280	0	13	0	0
T281	0	83	0	0
T282	0	235	0	0
T283	0	40	0	0
T284	0	12	0	0
T286	0	46	0	0
T287	0	29	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5621	0	0
T3	425915	117	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	293	0	0
T35	50828	0	0	0
T36	0	39	0	0
T268	0	7	0	0
T280	0	16	0	0
T281	0	127	0	0
T282	0	307	0	0
T283	0	35	0	0
T284	0	7	0	0
T285	0	6	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5546	0	0
T3	425915	89	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	286	0	0
T35	50828	0	0	0
T36	0	24	0	0
T268	0	6	0	0
T280	0	29	0	0
T281	0	107	0	0
T282	0	227	0	0
T283	0	39	0	0
T284	0	9	0	0
T285	0	3	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	5283	0	0
T3	425915	81	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	211	0	0
T35	50828	0	0	0
T36	0	1	0	0
T280	0	24	0	0
T281	0	103	0	0
T282	0	243	0	0
T283	0	27	0	0
T284	0	1	0	0
T286	0	47	0	0
T288	0	22	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	2825	0	0
T3	425915	30	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	63	0	0
T35	50828	0	0	0
T36	0	7	0	0
T280	0	10	0	0
T281	0	33	0	0
T282	0	102	0	0
T283	0	17	0	0
T284	0	2	0	0
T286	0	54	0	0
T288	0	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	2584	0	0
T3	425915	20	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	63	0	0
T35	50828	0	0	0
T36	0	5	0	0
T280	0	15	0	0
T289	0	9	0	0
T290	0	19	0	0
T291	0	11	0	0
T292	0	20	0	0
T293	0	20	0	0
T294	0	12	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	4285	0	0
T3	425915	204	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	443	0	0
T35	50828	0	0	0
T36	0	72	0	0
T268	0	14	0	0
T280	0	57	0	0
T281	0	275	0	0
T282	0	552	0	0
T283	0	11	0	0
T284	0	23	0	0
T285	0	6	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	1654	0	0
T3	425915	49	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	74	0	0
T35	50828	0	0	0
T36	0	14	0	0
T268	0	9	0	0
T280	0	2	0	0
T281	0	34	0	0
T282	0	74	0	0
T283	0	9	0	0
T284	0	9	0	0
T286	0	25	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	6612	0	0
T3	425915	308	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	586	0	0
T35	50828	0	0	0
T36	0	76	0	0
T280	0	39	0	0
T281	0	275	0	0
T282	0	435	0	0
T283	0	18	0	0
T284	0	37	0	0
T286	0	60	0	0
T287	0	14	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	7818	0	0
T3	425915	331	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	561	0	0
T35	50828	0	0	0
T36	0	141	0	0
T268	0	7	0	0
T280	0	65	0	0
T281	0	292	0	0
T282	0	644	0	0
T283	0	19	0	0
T284	0	41	0	0
T285	0	7	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	6189	0	0
T3	425915	194	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	375	0	0
T35	50828	0	0	0
T36	0	54	0	0
T268	0	5	0	0
T280	0	8	0	0
T281	0	188	0	0
T282	0	308	0	0
T283	0	31	0	0
T284	0	1	0	0
T286	0	26	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	6010	0	0
T3	425915	169	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	345	0	0
T35	50828	0	0	0
T36	0	14	0	0
T268	0	2	0	0
T280	0	3	0	0
T281	0	199	0	0
T282	0	332	0	0
T283	0	1	0	0
T284	0	5	0	0
T285	0	5	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	2046	0	0
T3	425915	44	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	102	0	0
T35	50828	0	0	0
T36	0	8	0	0
T280	0	13	0	0
T281	0	71	0	0
T282	0	86	0	0
T283	0	51	0	0
T285	0	5	0	0
T286	0	71	0	0
T287	0	3	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	1688	0	0
T3	425915	21	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	87	0	0
T35	50828	0	0	0
T36	0	8	0	0
T268	0	19	0	0
T280	0	17	0	0
T281	0	56	0	0
T282	0	46	0	0
T283	0	4	0	0
T284	0	2	0	0
T286	0	45	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	1763	0	0
T3	425915	37	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	80	0	0
T35	50828	0	0	0
T36	0	9	0	0
T280	0	7	0	0
T281	0	56	0	0
T282	0	68	0	0
T283	0	27	0	0
T285	0	6	0	0
T286	0	17	0	0
T287	0	6	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	1859	0	0
T3	425915	37	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	80	0	0
T35	50828	0	0	0
T36	0	14	0	0
T268	0	14	0	0
T280	0	6	0	0
T281	0	41	0	0
T282	0	54	0	0
T283	0	30	0	0
T284	0	8	0	0
T285	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222013153	1620	0	0
T3	425915	34	0	0
T4	749622	0	0	0
T5	101311	0	0	0
T21	200944	0	0	0
T22	202946	0	0	0
T23	48610	0	0	0
T24	52815	0	0	0
T25	50379	0	0	0
T26	89209	0	0	0
T33	0	73	0	0
T35	50828	0	0	0
T36	0	7	0	0
T280	0	13	0	0
T281	0	29	0	0
T282	0	41	0	0
T283	0	19	0	0
T285	0	5	0	0
T286	0	20	0	0
T287	0	25	0	0