Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2101

1

T18

15

T19

16

T21

15

auto[1]

537

1

T16

13

T18

9

T19

12

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2006

1

T16

10

T18

21

T19

19

auto[1]

632

1

T16

3

T18

3

T19

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1923

1

T16

12

T18

12

T19

21

auto[1]

715

1

T16

1

T18

12

T19

7

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1835

1

T16

3

T18

12

T19

22

auto[1]

803

1

T16

10

T18

12

T19

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2329

1

T16

13

T18

24

T19

21

auto[1]

309

1

T19

7

T23

14

T77

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2448

1

T16

13

T18

24

T19

25

auto[1]

190

1

T19

3

T21

1

T23

8

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2424

1

T16

13

T18

24

T19

16

auto[1]

214

1

T19

12

T21

1

T23

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2427

1

T16

13

T18

24

T19

22

auto[1]

211

1

T19

6

T21

4

T44

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2422

1

T16

13

T18

24

T19

28

auto[1]

216

1

T21

4

T23

8

T44

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1929

1

T16

7

T18

18

T19

15

auto[1]

709

1

T16

6

T18

6

T19

13

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	974	1			T16	13		T18	24		T45	14
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	100	1			T19	7		T77	1		T214	24
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	53	1			T21	4		T44	4		T119	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	18	1			T254	2		T72	3		T103	9
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	59	1			T21	4		T44	5		T77	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	41	1			T78	4		T340	8		T341	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T342	3		T343	2		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	54	1			T19	6		T21	1		T119	8
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	40	1			T23	6		T119	5		T76	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	24	1			T210	4		T103	6		T344	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	17	1			T210	8		T142	1		T345	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	18	1			T19	3		T97	2		T344	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	6	1			T119	3		T98	3		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T346	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	39	1			T21	1		T210	4		T78	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	16	1			T242	1		T347	4		T342	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	18	1			T348	5		T349	4		T350	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	18	1			T23	8		T103	3		T351	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	18	1			T332	2		T352	3		T353	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	5	1			T72	5		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T354	5		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	12	1			T355	2		T255	1		T356	6
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	6	1			T244	6		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T96	1		T79	2		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	10	1			T19	3		T323	5		T350	2
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T357	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

94

1

T46

1

T120

6

T102

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

80

1

T233

7

T242

5

T120

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T19

3

T254

1

T280

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

120

1

T23

4

T254

2

T102

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

63

1

T16

6

T18

6

T121

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

127

1

T23

3

T119

5

T242

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

51

1

T16

3

T18

3

T56

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

129

1

T18

12

T23

4

T56

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

49

1

T56

2

T354

5

T198

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

72

1

T19

7

T51

2

T319

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T16

1

T332

2

T353

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

75

1

T45

4

T57

6

T121

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

33

1

T21

1

T57

3

T231

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

56

1

T45

2

T320

8

T172

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T120

2

T197

5

T265

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

114

1

T21

4

T121

10

T119

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T94

5

T97

2

T198

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T44

5

T68

2

T358

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T16

2

T19

3

T68

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T56

7

T210

8

T280

9

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T16

1

T19

6

T44

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T18

3

T21

1

T23

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T231

2

T320

1

T110

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

58

1

T56

3

T102

1

T319

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T94

2

T100

4

T320

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

31

1

T77

3

T120

2

T141

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T51

2

T272

2

T262

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T121

3

T233

1

T120

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T21

4

T359

2

T263

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

29

1

T120

2

T102

3

T118

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T45

1

T56

1

T155

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded