Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T43

12

T31

12

T90

10

auto[1]

1145

1

T43

8

T31

8

T90

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

544

1

T43

5

T31

5

T90

4

from_0to1

535

1

T43

5

T31

6

T90

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T43

11

T31

13

T90

9

auto[1]

1128

1

T43

9

T31

7

T90

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T43

8

T31

7

T90

9

auto[1]

1138

1

T43

12

T31

13

T90

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T43

1

T90

1

T367

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T31

2

T368

1

T369

1

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T43

2

T367

1

T368

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T43

1

T31

1

T367

2

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T368

2

T369

1

T132

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T43

1

T31

3

T90

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T43

1

T367

1

T369

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T43

1

T90

1

T369

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T43

1

T250

1

T370

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T90

1

T367

1

T368

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T369

1

T370

2

T164

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T31

2

T90

2

T368

2

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T31

1

T90

1

T368

1

auto[1]

from_0to1

auto[0]

auto[1]

81

1

T43

1

T31

1

T367

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T367

3

T267

1

T49

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T43

1

T31

1

T90

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T43

6

T31

9

T90

13

auto[1]

1116

1

T43

14

T31

11

T90

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T43

4

T31

5

T90

6

from_0to1

541

1

T43

4

T31

5

T90

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T43

11

T31

7

T90

7

auto[1]

1160

1

T43

9

T31

13

T90

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T43

12

T31

14

T90

10

auto[1]

1177

1

T43

8

T31

6

T90

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T31

1

T368

1

T56

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T43

1

T369

1

T370

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T31

2

T90

1

T370

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T90

2

T367

1

T369

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T43

1

T90

2

T367

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T90

1

T368

1

T369

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T31

1

T367

1

T368

1

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T367

2

T369

1

T370

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T43

1

T90

1

T367

2

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T90

1

T367

2

T368

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T43

1

T367

1

T369

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T43

1

T31

2

T90

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T43

1

T90

1

T368

2

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T31

1

T249

1

T250

1

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T43

1

T31

2

T90

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T43

1

T31

1

T367

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1178

1

T43

9

T31

14

T90

12

auto[1]

1091

1

T43

11

T31

6

T90

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

537

1

T43

4

T31

6

T90

5

from_0to1

533

1

T43

4

T31

6

T90

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T43

10

T31

10

T90

9

auto[1]

1122

1

T43

10

T31

10

T90

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T43

13

T31

12

T90

9

auto[1]

1116

1

T43

7

T31

8

T90

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T31

1

T90

1

T369

2

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T43

1

T31

4

T90

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T43

1

T31

1

T369

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T368

2

T249

1

T56

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T43

1

T31

1

T367

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T31

1

T90

1

T249

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T31

2

T90

1

T369

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T90

1

T368

1

T250

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T250

1

T370

1

T56

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T43

1

T367

1

T369

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T90

1

T367

3

T368

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T43

1

T90

1

T249

2

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T90

1

T367

1

T249

2

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T43

1

T367

1

T368

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T43

2

T31

1

T368

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T31

1

T90

1

T367

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1137

1

T43

12

T31

10

T90

12

auto[1]

1132

1

T43

8

T31

10

T90

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

557

1

T43

6

T31

6

T90

4

from_0to1

562

1

T43

6

T31

6

T90

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T43

6

T31

11

T90

12

auto[1]

1142

1

T43

14

T31

9

T90

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1178

1

T43

11

T31

8

T90

11

auto[1]

1091

1

T43

9

T31

12

T90

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T31

1

T90

1

T368

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T31

1

T90

1

T367

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T43

1

T90

2

T249

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T43

1

T31

1

T249

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T43

1

T31

1

T90

3

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T43

1

T368

2

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T43

2

T90

1

T367

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T31

1

T367

1

T368

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T31

1

T367

1

T368

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T43

1

T31

1

T367

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T43

1

T368

1

T369

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T43

2

T31

1

T367

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T31

1

T90

1

T250

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T31

1

T368

1

T369

1

auto[1]

from_0to1

auto[1]

auto[0]

84

1

T43

2

T367

1

T249

3

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T31

2

T367

1

T369

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1183

1

T43

8

T31

11

T90

9

auto[1]

1086

1

T43

12

T31

9

T90

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T43

5

T31

6

T90

5

from_0to1

559

1

T43

5

T31

6

T90

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T43

10

T31

6

T90

12

auto[1]

1163

1

T43

10

T31

14

T90

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T43

9

T31

12

T90

8

auto[1]

1138

1

T43

11

T31

8

T90

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T31

1

T367

2

T368

2

auto[0]

from_1to0

auto[0]

auto[1]

81

1

T43

1

T90

1

T369

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T368

1

T369

1

T249

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T43

1

T31

1

T90

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T90

2

T369

1

T250

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T43

1

T367

1

T368

1

auto[0]

from_0to1

auto[1]

auto[0]

88

1

T31

3

T367

1

T368

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T31

1

T90

1

T368

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T31

1

T250

1

T370

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T43

1

T31

2

T90

2

auto[1]

from_1to0

auto[1]

auto[0]

88

1

T43

2

T368

1

T249

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T31

1

T369

2

T249

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T43

1

T31

1

T367

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T90

1

T368

1

T369

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T43

2

T31

1

T90

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T43

1

T90

1

T367

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T43

12

T31

9

T90

11

auto[1]

1108

1

T43

8

T31

11

T90

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

562

1

T43

6

T31

3

T90

6

from_0to1

556

1

T43

6

T31

4

T90

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T43

8

T31

8

T90

11

auto[1]

1182

1

T43

12

T31

12

T90

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T43

9

T31

14

T90

10

auto[1]

1118

1

T43

11

T31

6

T90

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

83

1

T368

2

T370

1

T46

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T43

1

T31

1

T90

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T43

1

T90

1

T367

3

auto[0]

from_1to0

auto[1]

auto[1]

81

1

T43

1

T90

2

T367

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T90

2

T367

2

T369

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T43

2

T367

2

T368

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T43

1

T31

1

T367

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T43

1

T31

1

T367

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T31

1

T90

1

T46

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T367

2

T368

1

T369

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T43

2

T31

1

T368

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T43

1

T368

2

T249

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T43

1

T46

1

T64

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T90

2

T368

2

T370

2

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T31

2

T90

1

T368

1

auto[1]

from_0to1

auto[1]

auto[1]

85

1

T43

1

T90

1

T368

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T43

11

T31

9

T90

7

auto[1]

1133

1

T43

9

T31

11

T90

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T43

4

T31

4

T90

5

from_0to1

531

1

T43

5

T31

4

T90

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T43

9

T31

10

T90

5

auto[1]

1126

1

T43

11

T31

10

T90

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T43

9

T31

14

T90

14

auto[1]

1114

1

T43

11

T31

6

T90

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T43

1

T31

3

T250

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T367

1

T368

1

T46

2

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T43

2

T367

2

T369

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T31

1

T90

1

T367

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T31

1

T90

1

T367

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T367

2

T368

1

T369

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T90

1

T367

1

T368

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T43

3

T250

1

T370

2

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T43

1

T367

1

T368

2

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T90

1

T369

2

T249

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T90

3

T368

1

T249

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T249

1

T56

2

T132

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T90

2

T367

1

T368

2

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T43

2

T249

2

T250

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T368

1

T56

1

T46

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T31

3

T90

1

T367

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T43

12

T31

10

T90

11

auto[1]

1179

1

T43

8

T31

10

T90

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T43

6

T31

4

T90

4

from_0to1

536

1

T43

6

T31

3

T90

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T43

10

T31

9

T90

10

auto[1]

1123

1

T43

10

T31

11

T90

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T43

7

T31

10

T90

15

auto[1]

1131

1

T43

13

T31

10

T90

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

82

1

T43

2

T90

2

T367

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T43

2

T367

1

T368

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T90

1

T367

1

T132

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T367

2

T370

3

T46

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T31

1

T90

1

T367

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T43

2

T31

1

T367

2

auto[0]

from_0to1

auto[1]

auto[0]

40

1

T43

1

T90

2

T250

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T90

1

T367

1

T368

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T368

1

T46

1

T132

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T43

1

T368

1

T369

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T31

1

T90

1

T367

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T43

1

T31

3

T368

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T367

1

T368

1

T369

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T43

1

T31

1

T249

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T43

1

T369

1

T250

1

auto[1]

from_0to1

auto[1]

auto[1]

81

1

T43

1

T369

1

T370

1