Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	159123	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124531

1

T7

41

T1

31

T8

2420

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	147431	1			T7	43		T1	89		T8	2534
values[0x0]	67828	1			T7	27		T1	19		T8	1298
values[0x1]	68395	1			T7	14		T1	19		T8	1296

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	129138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

154516

1

T7

52

T1

50

T8

2899

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1641	1			T8	19		T2	2		T10	13
valid_sources[0x01]	1319	1			T8	30		T372	1		T5	2
valid_sources[0x02]	1053	1			T7	3		T8	20		T2	1
valid_sources[0x03]	1870	1			T8	22		T372	1		T5	1
valid_sources[0x04]	840	1			T8	16		T26	1		T3	1
valid_sources[0x05]	884	1			T8	19		T5	1		T10	9
valid_sources[0x06]	1314	1			T8	15		T2	1		T3	1
valid_sources[0x07]	1105	1			T8	19		T5	1		T10	11
valid_sources[0x08]	955	1			T8	19		T372	1		T5	1
valid_sources[0x09]	1199	1			T8	24		T2	2		T373	2
valid_sources[0x0a]	1769	1			T8	21		T3	3		T288	1
valid_sources[0x0b]	875	1			T8	25		T24	2		T288	3
valid_sources[0x0c]	1139	1			T8	18		T2	1		T5	1
valid_sources[0x0d]	1051	1			T8	16		T3	1		T5	1
valid_sources[0x0e]	842	1			T8	22		T5	6		T288	1
valid_sources[0x0f]	783	1			T8	18		T288	1		T10	9
valid_sources[0x10]	1173	1			T7	3		T8	14		T27	121
valid_sources[0x11]	942	1			T1	7		T8	17		T3	4
valid_sources[0x12]	836	1			T7	1		T8	20		T3	2
valid_sources[0x13]	1149	1			T8	19		T3	1		T372	1
valid_sources[0x14]	1101	1			T8	18		T3	2		T288	2
valid_sources[0x15]	889	1			T8	18		T24	1		T30	1
valid_sources[0x16]	885	1			T7	1		T8	20		T42	1
valid_sources[0x17]	813	1			T8	15		T26	1		T5	1
valid_sources[0x18]	912	1			T8	24		T24	13		T3	1
valid_sources[0x19]	799	1			T7	1		T8	18		T2	4
valid_sources[0x1a]	915	1			T8	23		T24	1		T2	1
valid_sources[0x1b]	836	1			T7	1		T8	25		T24	2
valid_sources[0x1c]	992	1			T1	14		T8	22		T3	4
valid_sources[0x1d]	1367	1			T8	22		T10	11		T11	10
valid_sources[0x1e]	1025	1			T8	28		T3	2		T29	2
valid_sources[0x1f]	887	1			T8	18		T2	2		T5	1
valid_sources[0x20]	1034	1			T8	20		T29	3		T30	1
valid_sources[0x21]	933	1			T7	1		T8	14		T372	1
valid_sources[0x22]	1379	1			T8	26		T288	1		T10	9
valid_sources[0x23]	815	1			T8	22		T5	1		T288	1
valid_sources[0x24]	926	1			T7	2		T8	26		T29	1
valid_sources[0x25]	1021	1			T7	2		T1	3		T8	20
valid_sources[0x26]	939	1			T8	25		T29	1		T5	4
valid_sources[0x27]	2060	1			T8	20		T5	3		T288	4
valid_sources[0x28]	1066	1			T8	16		T3	1		T5	1
valid_sources[0x29]	812	1			T8	17		T10	10		T11	7
valid_sources[0x2a]	874	1			T8	20		T3	2		T29	1
valid_sources[0x2b]	2362	1			T8	24		T2	6		T27	113
valid_sources[0x2c]	870	1			T8	25		T26	4		T3	1
valid_sources[0x2d]	925	1			T8	18		T27	118		T372	1
valid_sources[0x2e]	1062	1			T8	15		T2	5		T288	2
valid_sources[0x2f]	1071	1			T8	19		T5	1		T288	3
valid_sources[0x30]	776	1			T8	25		T26	3		T3	2
valid_sources[0x31]	1127	1			T7	2		T8	11		T2	2
valid_sources[0x32]	1039	1			T8	19		T5	2		T288	1
valid_sources[0x33]	975	1			T1	5		T8	18		T29	1
valid_sources[0x34]	1847	1			T7	1		T8	22		T27	233
valid_sources[0x35]	2026	1			T7	1		T8	11		T24	3
valid_sources[0x36]	843	1			T8	19		T2	2		T288	2
valid_sources[0x37]	1000	1			T8	30		T5	1		T288	1
valid_sources[0x38]	881	1			T8	15		T5	1		T288	4
valid_sources[0x39]	1080	1			T1	3		T8	21		T2	1
valid_sources[0x3a]	942	1			T8	18		T3	1		T30	1
valid_sources[0x3b]	966	1			T8	18		T29	1		T5	2
valid_sources[0x3c]	1019	1			T8	25		T2	1		T5	1
valid_sources[0x3d]	854	1			T8	26		T2	3		T5	1
valid_sources[0x3e]	946	1			T8	15		T2	1		T3	2
valid_sources[0x3f]	1432	1			T8	14		T2	1		T42	1
valid_sources[0x40]	1040	1			T8	19		T26	2		T42	6
valid_sources[0x41]	804	1			T8	12		T3	1		T288	2
valid_sources[0x42]	928	1			T8	21		T3	2		T372	1
valid_sources[0x43]	1132	1			T7	1		T1	25		T8	22
valid_sources[0x44]	1192	1			T8	30		T2	1		T27	115
valid_sources[0x45]	896	1			T8	22		T2	1		T3	1
valid_sources[0x46]	1285	1			T8	20		T27	120		T30	2
valid_sources[0x47]	1113	1			T8	26		T10	6		T11	15
valid_sources[0x48]	1475	1			T8	17		T2	3		T42	3
valid_sources[0x49]	903	1			T7	1		T1	18		T8	17
valid_sources[0x4a]	999	1			T8	21		T2	1		T42	3
valid_sources[0x4b]	939	1			T8	24		T42	2		T288	2
valid_sources[0x4c]	1489	1			T8	21		T3	2		T10	11
valid_sources[0x4d]	872	1			T8	17		T25	5		T2	2
valid_sources[0x4e]	1305	1			T1	4		T8	30		T288	3
valid_sources[0x4f]	821	1			T8	23		T3	1		T5	1
valid_sources[0x50]	1033	1			T7	1		T8	19		T2	2
valid_sources[0x51]	1226	1			T7	1		T8	21		T24	9
valid_sources[0x52]	1462	1			T8	24		T3	1		T29	1
valid_sources[0x53]	1562	1			T8	15		T5	1		T373	1
valid_sources[0x54]	1100	1			T7	1		T8	12		T27	128
valid_sources[0x55]	1362	1			T8	12		T42	1		T288	2
valid_sources[0x56]	950	1			T7	4		T8	20		T288	2
valid_sources[0x57]	1083	1			T8	19		T24	6		T27	116
valid_sources[0x58]	1128	1			T8	15		T27	122		T3	1
valid_sources[0x59]	1232	1			T7	1		T8	20		T10	9
valid_sources[0x5a]	992	1			T7	3		T8	10		T288	3
valid_sources[0x5b]	969	1			T8	24		T28	21		T30	1
valid_sources[0x5c]	888	1			T8	18		T372	1		T5	1
valid_sources[0x5d]	812	1			T8	22		T5	1		T10	7
valid_sources[0x5e]	765	1			T8	27		T29	3		T42	1
valid_sources[0x5f]	875	1			T8	17		T24	2		T2	2
valid_sources[0x60]	907	1			T8	18		T29	2		T288	2
valid_sources[0x61]	796	1			T8	22		T373	1		T288	1
valid_sources[0x62]	903	1			T7	2		T8	28		T3	2
valid_sources[0x63]	972	1			T8	22		T5	3		T10	10
valid_sources[0x64]	896	1			T7	1		T8	29		T4	86
valid_sources[0x65]	2328	1			T8	16		T3	1		T5	3
valid_sources[0x66]	808	1			T8	20		T10	5		T11	9
valid_sources[0x67]	893	1			T8	24		T5	1		T288	1
valid_sources[0x68]	955	1			T8	19		T288	3		T10	6
valid_sources[0x69]	773	1			T8	11		T2	5		T3	1
valid_sources[0x6a]	972	1			T8	19		T27	128		T3	2
valid_sources[0x6b]	993	1			T7	1		T8	23		T4	17
valid_sources[0x6c]	856	1			T8	15		T3	3		T372	1
valid_sources[0x6d]	1131	1			T8	22		T5	3		T288	1
valid_sources[0x6e]	938	1			T1	11		T8	23		T27	116
valid_sources[0x6f]	870	1			T8	22		T2	1		T3	1
valid_sources[0x70]	828	1			T7	1		T8	18		T3	1
valid_sources[0x71]	911	1			T7	1		T8	24		T26	4
valid_sources[0x72]	2067	1			T7	1		T8	21		T3	1
valid_sources[0x73]	785	1			T8	18		T3	1		T5	1
valid_sources[0x74]	983	1			T7	1		T8	18		T2	8
valid_sources[0x75]	2029	1			T7	2		T8	27		T27	236
valid_sources[0x76]	1001	1			T8	23		T3	2		T288	1
valid_sources[0x77]	1435	1			T8	17		T30	1		T42	1
valid_sources[0x78]	872	1			T8	21		T373	1		T288	1
valid_sources[0x79]	921	1			T8	24		T3	1		T29	1
valid_sources[0x7a]	1135	1			T8	17		T27	121		T3	1
valid_sources[0x7b]	1629	1			T7	2		T8	17		T5	1
valid_sources[0x7c]	2216	1			T8	17		T288	1		T10	4
valid_sources[0x7d]	842	1			T8	13		T2	6		T26	4
valid_sources[0x7e]	1017	1			T8	26		T3	1		T30	1
valid_sources[0x7f]	1814	1			T8	25		T27	128		T288	1
valid_sources[0x80]	1286	1			T8	23		T2	1		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67766

1

T7

20

T1

13

T8

1259

values[0x0]

all_enables

biggest_size

33252

1

T7

13

T1

6

T8

672

values[0x1]

all_enables

biggest_size

23513

1

T7

8

T1

12

T8

489