Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
92 |
92 |
100.00 |
Total Bits 0->1 |
46 |
46 |
100.00 |
Total Bits 1->0 |
46 |
46 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
92 |
92 |
100.00 |
Port Bits 0->1 |
46 |
46 |
100.00 |
Port Bits 1->0 |
46 |
46 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T43,T14,T31 |
Yes |
T43,T14,T31 |
INPUT |
rst_ni |
Yes |
Yes |
T16,T17,T18 |
Yes |
T43,T14,T31 |
INPUT |
oh_i[15:0] |
Yes |
Yes |
*T14,*T15,*T16 |
Yes |
T14,T15,T16 |
INPUT |
oh_i[16] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[42:17] |
Yes |
Yes |
T17,T20,T54 |
Yes |
T17,T20,T54 |
INPUT |
addr_i[5:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T43,T14,T31 |
Yes |
T43,T14,T31 |
INPUT |
err_o |
Yes |
Yes |
T247,T269,T289 |
Yes |
T247,T269,T289 |
OUTPUT |
*Tests covering at least one bit in the range