Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T16,T17,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T16,T17,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T16,T17,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T35
1	0	Covered	T43,T14,T31
1	1	Covered	T16,T17,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T54
0	1	Covered	T73,T106,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T54
0	1	Covered	T16,T17,T54
1	0	Covered	T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T17,T54
1	-	Covered	T16,T17,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T35
0	1	Covered	T16,T17,T35
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T54
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T35
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T17,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T35,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T35
DetectSt	-	-	-	-	1	-	-	Covered	T73,T106,T107
DetectSt	-	-	-	-	0	1	-	Covered	T16,T17,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T17,T54
StableSt	-	-	-	-	-	-	0	Covered	T16,T17,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	288	0	0
CntIncr_A	8322531	156902	0	0
CntNoWrap_A	8322531	7634220	0	0
DetectStDropOut_A	8322531	5	0	0
DetectedOut_A	8322531	846	0	0
DetectedPulseOut_A	8322531	127	0	0
DisabledIdleSt_A	8322531	7470899	0	0
DisabledNoDetection_A	8322531	7473330	0	0
EnterDebounceSt_A	8322531	165	0	0
EnterDetectSt_A	8322531	132	0	0
EnterStableSt_A	8322531	127	0	0
PulseIsPulse_A	8322531	127	0	0
StayInStableSt	8322531	719	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8322531	7179	0	0
gen_low_level_sva.LowLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	126	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	288	0	0
T16	26856	7	0	0
T17	14784	8	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	2	0	0
T36	427	0	0	0
T46	0	6	0	0
T54	0	4	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	3	0	0
T86	0	1	0	0
T87	0	3	0	0
T88	0	2	0	0
T89	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	156902	0	0
T16	26856	268	0	0
T17	14784	262	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	74	0	0
T36	427	0	0	0
T46	0	113	0	0
T54	0	92	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	93	0	0
T86	0	93	0	0
T87	0	52	0	0
T88	0	23	0	0
T89	0	264	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634220	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19149	0	0
T17	14784	5254	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	198	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	5	0	0
T73	2609	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	18581	0	0	0
T111	422	0	0	0
T112	936	0	0	0
T113	410	0	0	0
T114	635	0	0	0
T115	667	0	0	0
T116	620	0	0	0
T117	526	0	0	0
T118	32373	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	846	0	0
T16	26856	27	0	0
T17	14784	41	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	20	0	0
T49	0	20	0	0
T54	0	8	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	7	0	0
T87	0	11	0	0
T88	0	10	0	0
T89	0	10	0	0
T120	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	127	0	0
T16	26856	3	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	3	0	0
T49	0	3	0	0
T54	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T120	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7470899	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	18728	0	0
T17	14784	4780	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	65	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7473330	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	18757	0	0
T17	14784	4805	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	66	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	165	0	0
T16	26856	4	0	0
T17	14784	5	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	2	0	0
T36	427	0	0	0
T46	0	3	0	0
T54	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	132	0	0
T16	26856	3	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	3	0	0
T49	0	3	0	0
T54	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T120	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	127	0	0
T16	26856	3	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	3	0	0
T49	0	3	0	0
T54	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T120	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	127	0	0
T16	26856	3	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	3	0	0
T49	0	3	0	0
T54	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T120	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	719	0	0
T16	26856	24	0	0
T17	14784	37	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	17	0	0
T49	0	17	0	0
T54	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	6	0	0
T87	0	10	0	0
T88	0	9	0	0
T89	0	8	0	0
T120	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7179	0	0
T14	848	3	0	0
T15	939	7	0	0
T16	26856	60	0	0
T17	14784	33	0	0
T31	504	5	0	0
T32	414	1	0	0
T33	525	5	0	0
T34	493	8	0	0
T35	601	3	0	0
T43	504	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	126	0	0
T16	26856	3	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	3	0	0
T49	0	3	0	0
T54	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T120	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T14,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T14,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T43,T31,T32
1	1	Covered	T14,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T62,T83,T64
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T14,T15,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T83,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T62,T83,T64
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T15,T16
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	170	0	0
CntIncr_A	8322531	77102	0	0
CntNoWrap_A	8322531	7634338	0	0
DetectStDropOut_A	8322531	15	0	0
DetectedOut_A	8322531	6423	0	0
DetectedPulseOut_A	8322531	44	0	0
DisabledIdleSt_A	8322531	6087161	0	0
DisabledNoDetection_A	8322531	6089646	0	0
EnterDebounceSt_A	8322531	113	0	0
EnterDetectSt_A	8322531	59	0	0
EnterStableSt_A	8322531	44	0	0
PulseIsPulse_A	8322531	44	0	0
StayInStableSt	8322531	6379	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8322531	7179	0	0
gen_low_level_sva.LowLevelEvent_A	8322531	7636997	0	0
gen_sticky_sva.StableStDropOut_A	8322531	1288365	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	170	0	0
T14	848	2	0	0
T15	939	2	0	0
T16	26856	2	0	0
T17	14784	3	0	0
T22	0	2	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	4	0	0
T63	0	2	0	0
T64	0	5	0	0
T83	0	4	0	0
T124	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	77102	0	0
T14	848	92	0	0
T15	939	25	0	0
T16	26856	10	0	0
T17	14784	78	0	0
T22	0	73	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	130	0	0
T63	0	41	0	0
T64	0	141	0	0
T83	0	36	0	0
T124	0	132	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634338	0	0
T14	848	445	0	0
T15	939	536	0	0
T16	26856	19154	0	0
T17	14784	5259	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	15	0	0
T57	18948	0	0	0
T62	1040	1	0	0
T64	0	2	0	0
T77	14756	0	0	0
T81	0	2	0	0
T83	1102	1	0	0
T85	671	0	0	0
T86	751	0	0	0
T122	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	496	0	0	0
T131	749	0	0	0
T132	502	0	0	0
T133	437	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6423	0	0
T14	848	225	0	0
T15	939	120	0	0
T16	26856	69	0	0
T17	14784	0	0	0
T22	0	150	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	132	0	0
T63	0	10	0	0
T65	0	15	0	0
T66	0	3	0	0
T80	0	455	0	0
T123	0	130	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	44	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	1	0	0
T17	14784	0	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T80	0	2	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6087161	0	0
T14	848	30	0	0
T15	939	316	0	0
T16	26856	18680	0	0
T17	14784	4889	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6089646	0	0
T14	848	31	0	0
T15	939	317	0	0
T16	26856	18710	0	0
T17	14784	4917	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	113	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	1	0	0
T17	14784	3	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	3	0	0
T83	0	3	0	0
T124	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	59	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	1	0	0
T17	14784	0	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T83	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	44	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	1	0	0
T17	14784	0	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T80	0	2	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	44	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	1	0	0
T17	14784	0	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T80	0	2	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6379	0	0
T14	848	224	0	0
T15	939	119	0	0
T16	26856	68	0	0
T17	14784	0	0	0
T22	0	149	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	131	0	0
T63	0	9	0	0
T65	0	14	0	0
T66	0	2	0	0
T80	0	453	0	0
T123	0	129	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7179	0	0
T14	848	3	0	0
T15	939	7	0	0
T16	26856	60	0	0
T17	14784	33	0	0
T31	504	5	0	0
T32	414	1	0	0
T33	525	5	0	0
T34	493	8	0	0
T35	601	3	0	0
T43	504	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1288365	0	0
T14	848	74	0	0
T15	939	68	0	0
T16	26856	380	0	0
T17	14784	0	0	0
T22	0	343898	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	210	0	0
T63	0	71	0	0
T65	0	68	0	0
T66	0	175	0	0
T80	0	279	0	0
T123	0	70	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T14,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T14,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T43,T31,T32
1	1	Covered	T14,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T17
0	1	Covered	T81,T80,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T17
0	1	Unreachable
1	0	Covered	T14,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T17
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T83,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T81,T80,T82
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	172	0	0
CntIncr_A	8322531	418206	0	0
CntNoWrap_A	8322531	7634336	0	0
DetectStDropOut_A	8322531	16	0	0
DetectedOut_A	8322531	1045789	0	0
DetectedPulseOut_A	8322531	46	0	0
DisabledIdleSt_A	8322531	6087161	0	0
DisabledNoDetection_A	8322531	6089646	0	0
EnterDebounceSt_A	8322531	112	0	0
EnterDetectSt_A	8322531	62	0	0
EnterStableSt_A	8322531	46	0	0
PulseIsPulse_A	8322531	46	0	0
StayInStableSt	8322531	1045743	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_sticky_sva.StableStDropOut_A	8322531	78879	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	172	0	0
T14	848	2	0	0
T15	939	2	0	0
T16	26856	4	0	0
T17	14784	2	0	0
T22	0	2	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	4	0	0
T63	0	2	0	0
T64	0	3	0	0
T83	0	3	0	0
T124	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	418206	0	0
T14	848	69	0	0
T15	939	48	0	0
T16	26856	96	0	0
T17	14784	47	0	0
T22	0	61192	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	62	0	0
T63	0	80	0	0
T64	0	2070	0	0
T83	0	138	0	0
T124	0	300	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634336	0	0
T14	848	445	0	0
T15	939	536	0	0
T16	26856	19152	0	0
T17	14784	5260	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	16	0	0
T80	0	2	0	0
T81	4299	1	0	0
T82	0	1	0	0
T103	26238	0	0	0
T109	0	1	0	0
T127	0	3	0	0
T134	0	1	0	0
T135	0	3	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	630	0	0	0
T140	503	0	0	0
T141	5568	0	0	0
T142	7396	0	0	0
T143	18127	0	0	0
T144	802	0	0	0
T145	404	0	0	0
T146	688	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1045789	0	0
T14	848	156	0	0
T15	939	99	0	0
T16	26856	0	0	0
T17	14784	110	0	0
T22	0	282857	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	106	0	0
T63	0	26	0	0
T65	0	15	0	0
T66	0	57	0	0
T80	0	310	0	0
T122	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	46	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	0	0	0
T17	14784	1	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T80	0	2	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6087161	0	0
T14	848	30	0	0
T15	939	316	0	0
T16	26856	18680	0	0
T17	14784	4889	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6089646	0	0
T14	848	31	0	0
T15	939	317	0	0
T16	26856	18710	0	0
T17	14784	4917	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	112	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	4	0	0
T17	14784	1	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	3	0	0
T83	0	3	0	0
T124	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	62	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	0	0	0
T17	14784	1	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T81	0	1	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	46	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	0	0	0
T17	14784	1	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T80	0	2	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	46	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	0	0	0
T17	14784	1	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T80	0	2	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1045743	0	0
T14	848	155	0	0
T15	939	98	0	0
T16	26856	0	0	0
T17	14784	109	0	0
T22	0	282856	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	104	0	0
T63	0	25	0	0
T65	0	14	0	0
T66	0	56	0	0
T80	0	308	0	0
T122	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	78879	0	0
T14	848	170	0	0
T15	939	63	0	0
T16	26856	0	0	0
T17	14784	193	0	0
T22	0	69	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	387	0	0
T63	0	26	0	0
T65	0	59	0	0
T66	0	43	0	0
T80	0	499	0	0
T122	0	309	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T14,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T14,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T43,T31,T32
1	1	Covered	T14,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T17
0	1	Covered	T16,T17,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T17
0	1	Unreachable
1	0	Covered	T14,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T83,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T16,T17,T80
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	186	0	0
CntIncr_A	8322531	6184	0	0
CntNoWrap_A	8322531	7634322	0	0
DetectStDropOut_A	8322531	21	0	0
DetectedOut_A	8322531	6389	0	0
DetectedPulseOut_A	8322531	50	0	0
DisabledIdleSt_A	8322531	6087161	0	0
DisabledNoDetection_A	8322531	6089646	0	0
EnterDebounceSt_A	8322531	117	0	0
EnterDetectSt_A	8322531	71	0	0
EnterStableSt_A	8322531	50	0	0
PulseIsPulse_A	8322531	50	0	0
StayInStableSt	8322531	6339	0	0
gen_high_event_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_sticky_sva.StableStDropOut_A	8322531	1418321	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	186	0	0
T14	848	2	0	0
T15	939	2	0	0
T16	26856	6	0	0
T17	14784	6	0	0
T22	0	2	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	4	0	0
T63	0	2	0	0
T64	0	2	0	0
T83	0	3	0	0
T124	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6184	0	0
T14	848	54	0	0
T15	939	40	0	0
T16	26856	376	0	0
T17	14784	291	0	0
T22	0	72	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	170	0	0
T63	0	55	0	0
T64	0	84	0	0
T83	0	231	0	0
T124	0	150	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634322	0	0
T14	848	445	0	0
T15	939	536	0	0
T16	26856	19150	0	0
T17	14784	5256	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	21	0	0
T16	26856	2	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T80	0	2	0	0
T128	0	3	0	0
T135	0	6	0	0
T136	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6389	0	0
T14	848	227	0	0
T15	939	105	0	0
T16	26856	0	0	0
T17	14784	1	0	0
T22	0	347	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	330	0	0
T63	0	35	0	0
T64	0	335	0	0
T80	0	404	0	0
T81	0	165	0	0
T122	0	137	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	50	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	0	0	0
T17	14784	1	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6087161	0	0
T14	848	30	0	0
T15	939	316	0	0
T16	26856	18680	0	0
T17	14784	4889	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6089646	0	0
T14	848	31	0	0
T15	939	317	0	0
T16	26856	18710	0	0
T17	14784	4917	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	117	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	4	0	0
T17	14784	3	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T83	0	3	0	0
T124	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	71	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	2	0	0
T17	14784	3	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T81	0	1	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	50	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	0	0	0
T17	14784	1	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	50	0	0
T14	848	1	0	0
T15	939	1	0	0
T16	26856	0	0	0
T17	14784	1	0	0
T22	0	1	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6339	0	0
T14	848	226	0	0
T15	939	104	0	0
T16	26856	0	0	0
T17	14784	0	0	0
T22	0	346	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	328	0	0
T63	0	34	0	0
T64	0	334	0	0
T80	0	402	0	0
T81	0	164	0	0
T122	0	136	0	0
T151	0	27	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1418321	0	0
T14	848	129	0	0
T15	939	70	0	0
T16	26856	0	0	0
T17	14784	40	0	0
T22	0	343702	0	0
T31	504	0	0	0
T32	414	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T62	0	64	0	0
T63	0	44	0	0
T64	0	1736	0	0
T80	0	335	0	0
T81	0	32	0	0
T122	0	200	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T49,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T17,T49,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T49,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T54,T49
1	0	Covered	T43,T14,T31
1	1	Covered	T17,T49,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T49,T51
0	1	Covered	T17,T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T49,T51
0	1	Covered	T17,T51,T81
1	0	Covered	T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T49,T51
1	-	Covered	T17,T51,T81

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T49,T51
0	1	Covered	T17,T49,T51
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T49,T51
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T49,T51
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T49,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T153
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T49,T51
DetectSt	-	-	-	-	1	-	-	Covered	T17,T152
DetectSt	-	-	-	-	0	1	-	Covered	T17,T49,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T51,T81
StableSt	-	-	-	-	-	-	0	Covered	T17,T49,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	83	0	0
CntIncr_A	8322531	2180	0	0
CntNoWrap_A	8322531	7634425	0	0
DetectStDropOut_A	8322531	2	0	0
DetectedOut_A	8322531	2535	0	0
DetectedPulseOut_A	8322531	39	0	0
DisabledIdleSt_A	8322531	7579683	0	0
DisabledNoDetection_A	8322531	7582119	0	0
EnterDebounceSt_A	8322531	42	0	0
EnterDetectSt_A	8322531	41	0	0
EnterStableSt_A	8322531	39	0	0
PulseIsPulse_A	8322531	39	0	0
StayInStableSt	8322531	2474	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	83	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	2	0	0
T51	0	4	0	0
T52	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	2	0	0
T81	0	4	0	0
T144	0	4	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2180	0	0
T17	14784	66	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	50	0	0
T51	0	38	0	0
T52	0	74	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	41	0	0
T81	0	175	0	0
T144	0	82	0	0
T154	0	41	0	0
T155	0	14	0	0
T156	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634425	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5258	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T152	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2535	0	0
T17	14784	76	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	42	0	0
T51	0	64	0	0
T52	0	364	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	84	0	0
T144	0	70	0	0
T154	0	45	0	0
T155	0	40	0	0
T156	0	27	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	39	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T144	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7579683	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	4599	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7582119	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	4624	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	42	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T144	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	41	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T144	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	39	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T144	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	39	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T144	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2474	0	0
T17	14784	75	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	40	0	0
T51	0	61	0	0
T52	0	362	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	81	0	0
T123	0	43	0	0
T144	0	68	0	0
T154	0	43	0	0
T155	0	38	0	0
T156	0	26	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	15	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T51	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	1	0	0
T123	0	1	0	0
T144	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T53,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T17,T53,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T53,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T53,T46
1	0	Covered	T43,T31,T32
1	1	Covered	T17,T53,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T53,T47
0	1	Covered	T51,T161
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T53,T47
0	1	Covered	T17,T53,T48
1	0	Covered	T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T53,T47
1	-	Covered	T17,T53,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T53,T47
0	1	Covered	T17,T53,T47
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T53,T47
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T53,T47
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T53,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T123,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T53,T47
DetectSt	-	-	-	-	1	-	-	Covered	T51,T161
DetectSt	-	-	-	-	0	1	-	Covered	T17,T53,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T53,T48
StableSt	-	-	-	-	-	-	0	Covered	T17,T53,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	126	0	0
CntIncr_A	8322531	20151	0	0
CntNoWrap_A	8322531	7634382	0	0
DetectStDropOut_A	8322531	2	0	0
DetectedOut_A	8322531	6211	0	0
DetectedPulseOut_A	8322531	57	0	0
DisabledIdleSt_A	8322531	7419778	0	0
DisabledNoDetection_A	8322531	7422205	0	0
EnterDebounceSt_A	8322531	68	0	0
EnterDetectSt_A	8322531	59	0	0
EnterStableSt_A	8322531	57	0	0
PulseIsPulse_A	8322531	57	0	0
StayInStableSt	8322531	6131	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8322531	2581	0	0
gen_low_level_sva.LowLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	126	0	0
T17	14784	12	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	4	0	0
T51	0	9	0	0
T53	0	4	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	2	0	0
T81	0	2	0	0
T154	0	2	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	20151	0	0
T17	14784	140	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	41	0	0
T48	0	61	0	0
T49	0	133	0	0
T51	0	80	0	0
T53	0	134	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	41	0	0
T81	0	79	0	0
T154	0	41	0	0
T163	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634382	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5250	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2	0	0
T51	34232	1	0	0
T96	8228	0	0	0
T161	0	1	0	0
T163	793	0	0	0
T164	11914	0	0	0
T165	1018	0	0	0
T166	2025	0	0	0
T167	507	0	0	0
T168	423	0	0	0
T169	678	0	0	0
T170	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6211	0	0
T17	14784	192	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	39	0	0
T48	0	419	0	0
T49	0	315	0	0
T51	0	122	0	0
T53	0	228	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	2	0	0
T81	0	422	0	0
T154	0	124	0	0
T163	0	17	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	57	0	0
T17	14784	6	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	3	0	0
T53	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7419778	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	4306	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7422205	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	4330	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	68	0	0
T17	14784	6	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	5	0	0
T53	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	59	0	0
T17	14784	6	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	4	0	0
T53	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	57	0	0
T17	14784	6	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	3	0	0
T53	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	57	0	0
T17	14784	6	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	3	0	0
T53	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6131	0	0
T17	14784	183	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	37	0	0
T48	0	418	0	0
T49	0	311	0	0
T51	0	118	0	0
T53	0	225	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	421	0	0
T154	0	123	0	0
T163	0	16	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2581	0	0
T14	848	0	0	0
T15	939	0	0	0
T16	26856	21	0	0
T17	14784	27	0	0
T31	504	4	0	0
T32	414	2	0	0
T33	525	7	0	0
T34	493	6	0	0
T35	601	0	0	0
T36	0	2	0	0
T43	504	6	0	0
T59	0	6	0	0
T60	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	32	0	0
T17	14784	3	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T163	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0