Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T53,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T17,T53,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T53,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T54,T53
1	0	Covered	T43,T14,T31
1	1	Covered	T17,T53,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T53,T48
0	1	Covered	T52
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T53,T48
0	1	Covered	T17,T48,T81
1	0	Covered	T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T53,T48
1	-	Covered	T17,T48,T81

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T53,T48
0	1	Covered	T17,T53,T48
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T53,T48
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T53,T48
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T53,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T159
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T53,T48
DetectSt	-	-	-	-	1	-	-	Covered	T52
DetectSt	-	-	-	-	0	1	-	Covered	T17,T53,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T48,T81
StableSt	-	-	-	-	-	-	0	Covered	T17,T53,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	77	0	0
CntIncr_A	8322531	2075	0	0
CntNoWrap_A	8322531	7634431	0	0
DetectStDropOut_A	8322531	1	0	0
DetectedOut_A	8322531	3419	0	0
DetectedPulseOut_A	8322531	37	0	0
DisabledIdleSt_A	8322531	7292162	0	0
DisabledNoDetection_A	8322531	7294597	0	0
EnterDebounceSt_A	8322531	39	0	0
EnterDetectSt_A	8322531	38	0	0
EnterStableSt_A	8322531	37	0	0
PulseIsPulse_A	8322531	37	0	0
StayInStableSt	8322531	3363	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	77	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	2	0	0
T81	0	4	0	0
T144	0	4	0	0
T169	0	2	0	0
T173	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2075	0	0
T17	14784	25	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	61	0	0
T49	0	50	0	0
T52	0	74	0	0
T53	0	67	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	41	0	0
T81	0	158	0	0
T144	0	82	0	0
T169	0	92	0	0
T173	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634431	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5260	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1	0	0
T50	760	0	0	0
T52	987	1	0	0
T66	660	0	0	0
T99	5671	0	0	0
T174	502	0	0	0
T175	867	0	0	0
T176	522	0	0	0
T177	645	0	0	0
T178	665	0	0	0
T179	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	3419	0	0
T17	14784	41	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	326	0	0
T49	0	41	0	0
T53	0	330	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	191	0	0
T123	0	170	0	0
T144	0	169	0	0
T169	0	45	0	0
T173	0	228	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	37	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T123	0	1	0	0
T144	0	2	0	0
T169	0	1	0	0
T173	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7292162	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	4869	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7294597	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	4895	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	39	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T144	0	2	0	0
T169	0	1	0	0
T173	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	38	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T144	0	2	0	0
T169	0	1	0	0
T173	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	37	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T123	0	1	0	0
T144	0	2	0	0
T169	0	1	0	0
T173	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	37	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T123	0	1	0	0
T144	0	2	0	0
T169	0	1	0	0
T173	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	3363	0	0
T17	14784	40	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	325	0	0
T49	0	39	0	0
T53	0	328	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	188	0	0
T123	0	168	0	0
T144	0	166	0	0
T162	0	37	0	0
T169	0	43	0	0
T173	0	225	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	16	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T48	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	1	0	0
T144	0	1	0	0
T153	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T53,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T17,T53,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T53,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T20,T53
1	0	Covered	T43,T31,T32
1	1	Covered	T17,T53,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T53,T46
0	1	Covered	T182,T183
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T53,T47
0	1	Covered	T17,T53,T46
1	0	Covered	T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T53,T47
1	-	Covered	T17,T53,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T53,T46
0	1	Covered	T17,T53,T46
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T53,T46
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T53,T46
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T53,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T51,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T53,T46
DetectSt	-	-	-	-	1	-	-	Covered	T182,T183
DetectSt	-	-	-	-	0	1	-	Covered	T17,T53,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T53,T46
StableSt	-	-	-	-	-	-	0	Covered	T17,T53,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	140	0	0
CntIncr_A	8322531	82725	0	0
CntNoWrap_A	8322531	7634368	0	0
DetectStDropOut_A	8322531	2	0	0
DetectedOut_A	8322531	118984	0	0
DetectedPulseOut_A	8322531	65	0	0
DisabledIdleSt_A	8322531	7204075	0	0
DisabledNoDetection_A	8322531	7206506	0	0
EnterDebounceSt_A	8322531	74	0	0
EnterDetectSt_A	8322531	67	0	0
EnterStableSt_A	8322531	65	0	0
PulseIsPulse_A	8322531	65	0	0
StayInStableSt	8322531	118886	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8322531	3068	0	0
gen_low_level_sva.LowLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	140	0	0
T17	14784	9	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	0	4	0	0
T50	0	4	0	0
T51	0	5	0	0
T52	0	4	0	0
T53	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	4	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	82725	0	0
T17	14784	116	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	95	0	0
T47	0	41	0	0
T49	0	145	0	0
T50	0	62	0	0
T51	0	40	0	0
T52	0	148	0	0
T53	0	67	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	82	0	0
T163	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634368	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5253	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2	0	0
T182	645	1	0	0
T183	0	1	0	0
T184	502	0	0	0
T185	2619	0	0	0
T186	426	0	0	0
T187	507	0	0	0
T188	738	0	0	0
T189	427	0	0	0
T190	494	0	0	0
T191	632	0	0	0
T192	742	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	118984	0	0
T17	14784	299	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T47	0	40	0	0
T49	0	87	0	0
T50	0	212	0	0
T51	0	153	0	0
T52	0	332	0	0
T53	0	44	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	55	0	0
T163	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	65	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	2	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7204075	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	4604	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7206506	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	4629	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	74	0	0
T17	14784	5	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	2	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	67	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	2	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	65	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	2	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	65	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	2	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	118886	0	0
T17	14784	293	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	38	0	0
T49	0	85	0	0
T50	0	209	0	0
T51	0	150	0	0
T52	0	329	0	0
T53	0	43	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T154	0	52	0	0
T163	0	57	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	3068	0	0
T14	848	0	0	0
T15	939	0	0	0
T16	26856	26	0	0
T17	14784	31	0	0
T31	504	6	0	0
T32	414	1	0	0
T33	525	5	0	0
T34	493	4	0	0
T35	601	0	0	0
T36	0	2	0	0
T43	504	6	0	0
T59	0	7	0	0
T60	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	30	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	1	0	0
T156	0	1	0	0
T173	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T53,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T17,T53,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T53,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T53,T46
1	0	Covered	T43,T14,T31
1	1	Covered	T17,T53,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T53,T46
0	1	Covered	T17,T157
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T53,T46
0	1	Covered	T17,T154,T81
1	0	Covered	T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T53,T46
1	-	Covered	T17,T154,T81

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T53,T46
0	1	Covered	T17,T53,T46
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T53,T46
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T53,T46
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T53,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T123,T193,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T53,T46
DetectSt	-	-	-	-	1	-	-	Covered	T17,T69,T157
DetectSt	-	-	-	-	0	1	-	Covered	T17,T53,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T154,T81
StableSt	-	-	-	-	-	-	0	Covered	T17,T53,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	114	0	0
CntIncr_A	8322531	136807	0	0
CntNoWrap_A	8322531	7634394	0	0
DetectStDropOut_A	8322531	3	0	0
DetectedOut_A	8322531	110075	0	0
DetectedPulseOut_A	8322531	50	0	0
DisabledIdleSt_A	8322531	7156259	0	0
DisabledNoDetection_A	8322531	7158697	0	0
EnterDebounceSt_A	8322531	60	0	0
EnterDetectSt_A	8322531	54	0	0
EnterStableSt_A	8322531	50	0	0
PulseIsPulse_A	8322531	50	0	0
StayInStableSt	8322531	109999	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	114	0	0
T17	14784	10	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	2	0	0
T50	0	2	0	0
T53	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	2	0	0
T81	0	4	0	0
T143	0	2	0	0
T154	0	4	0	0
T169	0	2	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	136807	0	0
T17	14784	164	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	95	0	0
T50	0	31	0	0
T53	0	67	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	41	0	0
T81	0	192	0	0
T143	0	15	0	0
T154	0	82	0	0
T169	0	92	0	0
T194	0	77	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634394	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5252	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	3	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T157	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	110075	0	0
T17	14784	265	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	138	0	0
T50	0	88	0	0
T53	0	442	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	252	0	0
T143	0	69	0	0
T154	0	136	0	0
T169	0	177	0	0
T172	0	198	0	0
T194	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	50	0	0
T17	14784	3	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	2	0	0
T143	0	1	0	0
T154	0	2	0	0
T169	0	1	0	0
T172	0	3	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7156259	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	4501	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7158697	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	4526	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	60	0	0
T17	14784	5	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T143	0	1	0	0
T154	0	2	0	0
T169	0	1	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	54	0	0
T17	14784	5	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	2	0	0
T143	0	1	0	0
T154	0	2	0	0
T169	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	50	0	0
T17	14784	3	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	2	0	0
T143	0	1	0	0
T154	0	2	0	0
T169	0	1	0	0
T172	0	3	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	50	0	0
T17	14784	3	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	2	0	0
T143	0	1	0	0
T154	0	2	0	0
T169	0	1	0	0
T172	0	3	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	109999	0	0
T17	14784	261	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	136	0	0
T50	0	86	0	0
T53	0	440	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T81	0	249	0	0
T143	0	67	0	0
T154	0	133	0	0
T169	0	175	0	0
T172	0	194	0	0
T194	0	10	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	23	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T80	0	2	0	0
T81	0	1	0	0
T123	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T172	0	2	0	0
T173	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T49,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T17,T49,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T49,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T54,T47
1	0	Covered	T43,T14,T31
1	1	Covered	T17,T49,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T49,T51
0	1	Not Covered
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T49,T51
0	1	Covered	T17,T49,T51
1	0	Covered	T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T49,T51
1	-	Covered	T17,T49,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T49,T51
0	1	Covered	T17,T49,T51
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T49,T51
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T49,T51
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T49,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T172,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T49,T51
DetectSt	-	-	-	-	1	-	-	Covered	T69
DetectSt	-	-	-	-	0	1	-	Covered	T17,T49,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T49,T51
StableSt	-	-	-	-	-	-	0	Covered	T17,T49,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	86	0	0
CntIncr_A	8322531	10939	0	0
CntNoWrap_A	8322531	7634422	0	0
DetectStDropOut_A	8322531	0	0	0
DetectedOut_A	8322531	3020	0	0
DetectedPulseOut_A	8322531	40	0	0
DisabledIdleSt_A	8322531	7579737	0	0
DisabledNoDetection_A	8322531	7582178	0	0
EnterDebounceSt_A	8322531	45	0	0
EnterDetectSt_A	8322531	41	0	0
EnterStableSt_A	8322531	40	0	0
PulseIsPulse_A	8322531	40	0	0
StayInStableSt	8322531	2955	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8322531	6778	0	0
gen_low_level_sva.LowLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	86	0	0
T17	14784	8	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	6	0	0
T51	0	4	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	2	0	0
T144	0	2	0	0
T154	0	2	0	0
T156	0	2	0	0
T163	0	1	0	0
T172	0	3	0	0
T173	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	10939	0	0
T17	14784	143	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	228	0	0
T51	0	29	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	41	0	0
T144	0	41	0	0
T154	0	41	0	0
T156	0	32	0	0
T163	0	88	0	0
T172	0	138	0	0
T173	0	141	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634422	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5254	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	3020	0	0
T17	14784	142	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	124	0	0
T51	0	88	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T144	0	198	0	0
T154	0	42	0	0
T156	0	175	0	0
T172	0	1	0	0
T173	0	232	0	0
T182	0	97	0	0
T197	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	40	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	3	0	0
T51	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T144	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T172	0	1	0	0
T173	0	2	0	0
T182	0	1	0	0
T197	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7579737	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	4494	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7582178	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	4519	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	45	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	3	0	0
T51	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T144	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T163	0	1	0	0
T172	0	2	0	0
T173	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	41	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	3	0	0
T51	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T144	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T172	0	1	0	0
T173	0	2	0	0
T197	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	40	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	3	0	0
T51	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T144	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T172	0	1	0	0
T173	0	2	0	0
T182	0	1	0	0
T197	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	40	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	3	0	0
T51	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T144	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T172	0	1	0	0
T173	0	2	0	0
T182	0	1	0	0
T197	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2955	0	0
T17	14784	136	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	119	0	0
T51	0	85	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T144	0	196	0	0
T154	0	41	0	0
T156	0	173	0	0
T158	0	39	0	0
T173	0	229	0	0
T182	0	95	0	0
T197	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6778	0	0
T14	848	3	0	0
T15	939	7	0	0
T16	26856	47	0	0
T17	14784	36	0	0
T31	504	6	0	0
T32	414	2	0	0
T33	525	3	0	0
T34	493	5	0	0
T35	601	0	0	0
T36	0	3	0	0
T43	504	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	14	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T154	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T43,T31,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T14,T31
1	0	Covered	T43,T31,T32
1	1	Covered	T43,T31,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T20,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T17,T20,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T20,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T20,T54
1	0	Covered	T43,T31,T32
1	1	Covered	T17,T20,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T54
0	1	Covered	T20,T159,T202
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T54
0	1	Covered	T17,T20,T49
1	0	Covered	T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T20,T54
1	-	Covered	T17,T20,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T20,T54
0	1	Covered	T17,T20,T54
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T20,T54
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T20,T54
IdleSt	0	-	-	-	-	-	-	Covered	T43,T31,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T20,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T199,T203,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T20,T54
DetectSt	-	-	-	-	1	-	-	Covered	T20,T159,T202
DetectSt	-	-	-	-	0	1	-	Covered	T17,T20,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T20,T49
StableSt	-	-	-	-	-	-	0	Covered	T17,T20,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	158	0	0
CntIncr_A	8322531	197587	0	0
CntNoWrap_A	8322531	7634350	0	0
DetectStDropOut_A	8322531	3	0	0
DetectedOut_A	8322531	88897	0	0
DetectedPulseOut_A	8322531	74	0	0
DisabledIdleSt_A	8322531	7158137	0	0
DisabledNoDetection_A	8322531	7160559	0	0
EnterDebounceSt_A	8322531	81	0	0
EnterDetectSt_A	8322531	77	0	0
EnterStableSt_A	8322531	74	0	0
PulseIsPulse_A	8322531	74	0	0
StayInStableSt	8322531	88793	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	158	0	0
T17	14784	4	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	4	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	2	0	0
T49	0	6	0	0
T51	0	8	0	0
T54	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	2	0	0
T81	0	2	0	0
T163	0	2	0	0
T194	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	197587	0	0
T17	14784	92	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	39074	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	41	0	0
T49	0	142	0	0
T51	0	60	0	0
T54	0	25	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	41	0	0
T81	0	96	0	0
T163	0	88	0	0
T194	0	154	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634350	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5258	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	3	0	0
T20	87664	1	0	0
T91	411	0	0	0
T92	525	0	0	0
T129	143571	0	0	0
T148	714	0	0	0
T159	3639	1	0	0
T193	531	0	0	0
T202	0	1	0	0
T205	407	0	0	0
T206	411	0	0	0
T207	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	88897	0	0
T17	14784	79	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	9020	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	40	0	0
T49	0	156	0	0
T51	0	159	0	0
T54	0	62	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	2	0	0
T81	0	287	0	0
T163	0	42	0	0
T194	0	169	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	74	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	4	0	0
T54	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T163	0	1	0	0
T194	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7158137	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	4799	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7160559	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	4825	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	81	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	2	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	4	0	0
T54	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T163	0	1	0	0
T194	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	77	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	2	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	4	0	0
T54	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T163	0	1	0	0
T194	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	74	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	4	0	0
T54	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T163	0	1	0	0
T194	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	74	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	4	0	0
T54	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T163	0	1	0	0
T194	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	88793	0	0
T17	14784	76	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	9019	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T47	0	38	0	0
T49	0	153	0	0
T51	0	153	0	0
T54	0	60	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T81	0	285	0	0
T163	0	41	0	0
T194	0	166	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	42	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T20	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	3	0	0
T51	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T80	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T163	0	1	0	0
T173	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T31,T32
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T31,T32
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T49,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T17,T49,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T17,T49,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T54,T47
1	0	Covered	T43,T31,T32
1	1	Covered	T17,T49,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T51,T52
0	1	Covered	T17,T208
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T51,T52
0	1	Covered	T49,T51,T52
1	0	Covered	T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T51,T52
1	-	Covered	T49,T51,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T49,T51
0	1	Covered	T17,T49,T51
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T49,T51
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T49,T51
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T49,T51
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T49,T51
DetectSt	-	-	-	-	1	-	-	Covered	T17,T208
DetectSt	-	-	-	-	0	1	-	Covered	T49,T51,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T49,T51,T52
StableSt	-	-	-	-	-	-	0	Covered	T49,T51,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	78	0	0
CntIncr_A	8322531	55103	0	0
CntNoWrap_A	8322531	7634430	0	0
DetectStDropOut_A	8322531	2	0	0
DetectedOut_A	8322531	10768	0	0
DetectedPulseOut_A	8322531	37	0	0
DisabledIdleSt_A	8322531	7417498	0	0
DisabledNoDetection_A	8322531	7419934	0	0
EnterDebounceSt_A	8322531	39	0	0
EnterDetectSt_A	8322531	39	0	0
EnterStableSt_A	8322531	37	0	0
PulseIsPulse_A	8322531	37	0	0
StayInStableSt	8322531	10713	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8322531	6321	0	0
gen_low_level_sva.LowLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	78	0	0
T17	14784	2	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	4	0	0
T52	0	2	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T172	0	2	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	55103	0	0
T17	14784	46	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	145	0	0
T50	0	31	0	0
T51	0	31	0	0
T52	0	74	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	41	0	0
T143	0	15	0	0
T144	0	41	0	0
T172	0	69	0	0
T194	0	77	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7634430	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5260	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T208	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	10768	0	0
T49	32310	182	0	0
T50	0	45	0	0
T51	34232	110	0	0
T52	0	118	0	0
T58	561	0	0	0
T69	0	2	0	0
T78	35238	0	0	0
T143	0	125	0	0
T144	0	110	0	0
T156	0	101	0	0
T172	0	45	0	0
T194	0	54	0	0
T209	571	0	0	0
T210	13866	0	0	0
T211	4344	0	0	0
T212	491	0	0	0
T213	407	0	0	0
T214	20230	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	37	0	0
T49	32310	2	0	0
T50	0	1	0	0
T51	34232	2	0	0
T52	0	1	0	0
T58	561	0	0	0
T69	0	1	0	0
T78	35238	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T156	0	1	0	0
T172	0	1	0	0
T194	0	1	0	0
T209	571	0	0	0
T210	13866	0	0	0
T211	4344	0	0	0
T212	491	0	0	0
T213	407	0	0	0
T214	20230	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7417498	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	4992	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7419934	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5019	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	39	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T172	0	1	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	39	0	0
T17	14784	1	0	0
T18	35857	0	0	0
T19	17432	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T69	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T172	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	37	0	0
T49	32310	2	0	0
T50	0	1	0	0
T51	34232	2	0	0
T52	0	1	0	0
T58	561	0	0	0
T69	0	1	0	0
T78	35238	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T156	0	1	0	0
T172	0	1	0	0
T194	0	1	0	0
T209	571	0	0	0
T210	13866	0	0	0
T211	4344	0	0	0
T212	491	0	0	0
T213	407	0	0	0
T214	20230	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	37	0	0
T49	32310	2	0	0
T50	0	1	0	0
T51	34232	2	0	0
T52	0	1	0	0
T58	561	0	0	0
T69	0	1	0	0
T78	35238	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T156	0	1	0	0
T172	0	1	0	0
T194	0	1	0	0
T209	571	0	0	0
T210	13866	0	0	0
T211	4344	0	0	0
T212	491	0	0	0
T213	407	0	0	0
T214	20230	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	10713	0	0
T49	32310	179	0	0
T50	0	43	0	0
T51	34232	107	0	0
T52	0	117	0	0
T58	561	0	0	0
T69	0	1	0	0
T78	35238	0	0	0
T143	0	123	0	0
T144	0	109	0	0
T156	0	99	0	0
T172	0	43	0	0
T194	0	53	0	0
T209	571	0	0	0
T210	13866	0	0	0
T211	4344	0	0	0
T212	491	0	0	0
T213	407	0	0	0
T214	20230	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	6321	0	0
T14	848	0	0	0
T15	939	0	0	0
T16	26856	36	0	0
T17	14784	31	0	0
T18	0	10	0	0
T31	504	3	0	0
T32	414	2	0	0
T33	525	5	0	0
T34	493	6	0	0
T35	601	0	0	0
T36	0	2	0	0
T43	504	5	0	0
T59	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	17	0	0
T49	32310	1	0	0
T51	34232	1	0	0
T52	0	1	0	0
T58	561	0	0	0
T78	35238	0	0	0
T123	0	1	0	0
T144	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T182	0	1	0	0
T194	0	1	0	0
T200	0	1	0	0
T209	571	0	0	0
T210	13866	0	0	0
T211	4344	0	0	0
T212	491	0	0	0
T213	407	0	0	0
T214	20230	0	0	0