Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T21,T23
1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T23
1	0	Covered	T19,T21,T23
1	1	Covered	T19,T21,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T23
0	1	Covered	T74,T96,T97
1	0	Covered	T44,T74,T242

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T23
0	1	Covered	T19,T21,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T23
1	-	Covered	T19,T21,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T23
0	1	Covered	T19,T21,T23
0	0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T23
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T23
IdleSt	0	-	-	-	-	-	-	Covered	T19,T21,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T21,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T75,T69
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T23
DetectSt	-	-	-	-	1	-	-	Covered	T44,T74,T242
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T23
DetectSt	-	-	-	-	0	0	-	Covered	T19,T21,T23
StableSt	-	-	-	-	-	-	1	Covered	T19,T21,T23
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	2932	0	0
CntIncr_A	8322531	108876	0	0
CntNoWrap_A	8322531	7631576	0	0
DetectStDropOut_A	8322531	344	0	0
DetectedOut_A	8322531	81114	0	0
DetectedPulseOut_A	8322531	882	0	0
DisabledIdleSt_A	8322531	7151264	0	0
DisabledNoDetection_A	8322531	7153547	0	0
EnterDebounceSt_A	8322531	1486	0	0
EnterDetectSt_A	8322531	1447	0	0
EnterStableSt_A	8322531	882	0	0
PulseIsPulse_A	8322531	882	0	0
StayInStableSt	8322531	80121	0	0
gen_high_event_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	770	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2932	0	0
T19	17432	10	0	0
T20	87664	0	0	0
T21	16135	54	0	0
T22	918069	0	0	0
T23	14118	16	0	0
T44	0	2	0	0
T54	2881	0	0	0
T74	0	24	0	0
T75	0	10	0	0
T76	0	36	0	0
T77	0	34	0	0
T84	0	2	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	108876	0	0
T19	17432	230	0	0
T20	87664	0	0	0
T21	16135	2025	0	0
T22	918069	0	0	0
T23	14118	640	0	0
T44	0	81	0	0
T54	2881	0	0	0
T74	0	1550	0	0
T75	0	2702	0	0
T76	0	1062	0	0
T77	0	527	0	0
T84	0	80	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	2225	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7631576	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	344	0	0
T69	0	1	0	0
T74	10703	5	0	0
T96	8228	9	0	0
T97	0	11	0	0
T98	0	5	0	0
T99	0	14	0	0
T103	0	7	0	0
T243	0	9	0	0
T244	0	8	0	0
T245	0	14	0	0
T246	999	0	0	0
T247	8444	0	0	0
T248	408	0	0	0
T249	538	0	0	0
T250	512	0	0	0
T251	432	0	0	0
T252	505	0	0	0
T253	871	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	81114	0	0
T19	17432	387	0	0
T20	87664	0	0	0
T21	16135	1836	0	0
T22	918069	0	0	0
T23	14118	1827	0	0
T54	2881	0	0	0
T75	0	95	0	0
T76	0	1782	0	0
T77	0	697	0	0
T78	0	4050	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	2026	0	0
T210	0	626	0	0
T254	0	2965	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	882	0	0
T19	17432	5	0	0
T20	87664	0	0	0
T21	16135	27	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T54	2881	0	0	0
T75	0	1	0	0
T76	0	18	0	0
T77	0	17	0	0
T78	0	16	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	25	0	0
T210	0	11	0	0
T254	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7151264	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7153547	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1486	0	0
T19	17432	5	0	0
T20	87664	0	0	0
T21	16135	27	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T44	0	1	0	0
T54	2881	0	0	0
T74	0	12	0	0
T75	0	9	0	0
T76	0	18	0	0
T77	0	17	0	0
T84	0	2	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1447	0	0
T19	17432	5	0	0
T20	87664	0	0	0
T21	16135	27	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T44	0	1	0	0
T54	2881	0	0	0
T74	0	12	0	0
T75	0	1	0	0
T76	0	18	0	0
T77	0	17	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	25	0	0
T254	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	882	0	0
T19	17432	5	0	0
T20	87664	0	0	0
T21	16135	27	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T54	2881	0	0	0
T75	0	1	0	0
T76	0	18	0	0
T77	0	17	0	0
T78	0	16	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	25	0	0
T210	0	11	0	0
T254	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	882	0	0
T19	17432	5	0	0
T20	87664	0	0	0
T21	16135	27	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T54	2881	0	0	0
T75	0	1	0	0
T76	0	18	0	0
T77	0	17	0	0
T78	0	16	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	25	0	0
T210	0	11	0	0
T254	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	80121	0	0
T19	17432	381	0	0
T20	87664	0	0	0
T21	16135	1808	0	0
T22	918069	0	0	0
T23	14118	1818	0	0
T54	2881	0	0	0
T75	0	94	0	0
T76	0	1760	0	0
T77	0	679	0	0
T78	0	4030	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	1994	0	0
T210	0	614	0	0
T254	0	2936	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	770	0	0
T19	17432	4	0	0
T20	87664	0	0	0
T21	16135	26	0	0
T22	918069	0	0	0
T23	14118	7	0	0
T54	2881	0	0	0
T75	0	1	0	0
T76	0	14	0	0
T77	0	16	0	0
T78	0	12	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	18	0	0
T210	0	10	0	0
T254	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T16,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T16,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T16,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T56,T46
1	0	Covered	T69,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
1	0	Covered	T69,T255

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T19
1	-	Covered	T16,T18,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T18
0	1	Covered	T16,T17,T18
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T19
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T18
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T23,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T18
DetectSt	-	-	-	-	1	-	-	Covered	T16,T56,T46
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T19
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T19
StableSt	-	-	-	-	-	-	1	Covered	T16,T18,T19
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	1001	0	0
CntIncr_A	8322531	52967	0	0
CntNoWrap_A	8322531	7633507	0	0
DetectStDropOut_A	8322531	86	0	0
DetectedOut_A	8322531	16131	0	0
DetectedPulseOut_A	8322531	369	0	0
DisabledIdleSt_A	8322531	7206856	0	0
DisabledNoDetection_A	8322531	7208564	0	0
EnterDebounceSt_A	8322531	543	0	0
EnterDetectSt_A	8322531	460	0	0
EnterStableSt_A	8322531	369	0	0
PulseIsPulse_A	8322531	369	0	0
StayInStableSt	8322531	15717	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1001	0	0
T16	26856	12	0	0
T17	14784	1	0	0
T18	35857	6	0	0
T19	0	2	0	0
T21	0	2	0	0
T23	0	4	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	9	0	0
T46	0	5	0	0
T56	0	32	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	52967	0	0
T16	26856	389	0	0
T17	14784	20	0	0
T18	35857	528	0	0
T19	0	53	0	0
T21	0	83	0	0
T23	0	135	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	571	0	0
T46	0	104	0	0
T56	0	1907	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7633507	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19144	0	0
T17	14784	5261	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	86	0	0
T16	26856	5	0	0
T17	14784	0	0	0
T18	35857	0	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T46	0	1	0	0
T56	0	7	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	2	0	0
T95	0	5	0	0
T100	0	2	0	0
T101	0	7	0	0
T102	0	9	0	0
T104	0	10	0	0
T105	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	16131	0	0
T16	26856	47	0	0
T17	14784	0	0	0
T18	35857	40	0	0
T19	0	94	0	0
T21	0	56	0	0
T23	0	83	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	314	0	0
T46	0	3	0	0
T56	0	597	0	0
T57	0	87	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	369	0	0
T16	26856	1	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	4	0	0
T46	0	1	0	0
T56	0	8	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7206856	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	15480	0	0
T17	14784	5221	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7208564	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	15504	0	0
T17	14784	5247	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	543	0	0
T16	26856	6	0	0
T17	14784	1	0	0
T18	35857	3	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	3	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	5	0	0
T46	0	3	0	0
T56	0	17	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	460	0	0
T16	26856	6	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	4	0	0
T46	0	2	0	0
T56	0	15	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	369	0	0
T16	26856	1	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	4	0	0
T46	0	1	0	0
T56	0	8	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	369	0	0
T16	26856	1	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	4	0	0
T46	0	1	0	0
T56	0	8	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	15717	0	0
T16	26856	46	0	0
T17	14784	0	0	0
T18	35857	37	0	0
T19	0	93	0	0
T21	0	55	0	0
T23	0	82	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	310	0	0
T46	0	2	0	0
T56	0	589	0	0
T57	0	81	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	46	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	320	0	0
T16	26856	1	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	4	0	0
T46	0	1	0	0
T56	0	8	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T121	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T21,T23
1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T23
1	0	Covered	T19,T21,T23
1	1	Covered	T19,T21,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T23
0	1	Covered	T76,T97,T71
1	0	Covered	T76,T97,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T23
0	1	Covered	T19,T21,T23
1	0	Covered	T78,T69,T256

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T23
1	-	Covered	T19,T21,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T23
0	1	Covered	T19,T21,T23
0	0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T23
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T23
IdleSt	0	-	-	-	-	-	-	Covered	T19,T21,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T21,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T75,T69
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T23
DetectSt	-	-	-	-	1	-	-	Covered	T76,T97,T71
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T23
DetectSt	-	-	-	-	0	0	-	Covered	T19,T21,T23
StableSt	-	-	-	-	-	-	1	Covered	T19,T21,T23
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	2817	0	0
CntIncr_A	8322531	101878	0	0
CntNoWrap_A	8322531	7631691	0	0
DetectStDropOut_A	8322531	354	0	0
DetectedOut_A	8322531	67592	0	0
DetectedPulseOut_A	8322531	821	0	0
DisabledIdleSt_A	8322531	7162734	0	0
DisabledNoDetection_A	8322531	7165009	0	0
EnterDebounceSt_A	8322531	1445	0	0
EnterDetectSt_A	8322531	1374	0	0
EnterStableSt_A	8322531	821	0	0
PulseIsPulse_A	8322531	821	0	0
StayInStableSt	8322531	66652	0	0
gen_high_event_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	664	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	2817	0	0
T19	17432	18	0	0
T20	87664	0	0	0
T21	16135	62	0	0
T22	918069	0	0	0
T23	14118	10	0	0
T44	0	52	0	0
T54	2881	0	0	0
T74	0	10	0	0
T75	0	11	0	0
T76	0	10	0	0
T77	0	20	0	0
T84	0	21	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	101878	0	0
T19	17432	603	0	0
T20	87664	0	0	0
T21	16135	1705	0	0
T22	918069	0	0	0
T23	14118	430	0	0
T44	0	1170	0	0
T54	2881	0	0	0
T74	0	325	0	0
T75	0	3256	0	0
T76	0	304	0	0
T77	0	480	0	0
T84	0	840	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	553	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7631691	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	354	0	0
T65	2604	0	0	0
T69	0	1	0	0
T71	22577	17	0	0
T72	0	6	0	0
T76	15496	1	0	0
T88	664	0	0	0
T97	6104	17	0	0
T98	12450	0	0	0
T99	0	31	0	0
T142	0	7	0	0
T243	0	20	0	0
T244	0	5	0	0
T245	0	23	0	0
T257	496	0	0	0
T258	404	0	0	0
T259	592	0	0	0
T260	594	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	67592	0	0
T19	17432	386	0	0
T20	87664	0	0	0
T21	16135	3311	0	0
T22	918069	0	0	0
T23	14118	448	0	0
T44	0	2334	0	0
T54	2881	0	0	0
T74	0	331	0	0
T77	0	260	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	551	0	0
T210	0	571	0	0
T242	0	412	0	0
T254	0	463	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	821	0	0
T19	17432	9	0	0
T20	87664	0	0	0
T21	16135	31	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T44	0	26	0	0
T54	2881	0	0	0
T74	0	5	0	0
T77	0	10	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	7	0	0
T210	0	11	0	0
T242	0	14	0	0
T254	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7162734	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7165009	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1445	0	0
T19	17432	9	0	0
T20	87664	0	0	0
T21	16135	31	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T44	0	26	0	0
T54	2881	0	0	0
T74	0	5	0	0
T75	0	11	0	0
T76	0	5	0	0
T77	0	10	0	0
T84	0	21	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1374	0	0
T19	17432	9	0	0
T20	87664	0	0	0
T21	16135	31	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T44	0	26	0	0
T54	2881	0	0	0
T74	0	5	0	0
T76	0	5	0	0
T77	0	10	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	7	0	0
T242	0	14	0	0
T254	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	821	0	0
T19	17432	9	0	0
T20	87664	0	0	0
T21	16135	31	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T44	0	26	0	0
T54	2881	0	0	0
T74	0	5	0	0
T77	0	10	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	7	0	0
T210	0	11	0	0
T242	0	14	0	0
T254	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	821	0	0
T19	17432	9	0	0
T20	87664	0	0	0
T21	16135	31	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T44	0	26	0	0
T54	2881	0	0	0
T74	0	5	0	0
T77	0	10	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	7	0	0
T210	0	11	0	0
T242	0	14	0	0
T254	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	66652	0	0
T19	17432	376	0	0
T20	87664	0	0	0
T21	16135	3278	0	0
T22	918069	0	0	0
T23	14118	441	0	0
T44	0	2305	0	0
T54	2881	0	0	0
T74	0	326	0	0
T77	0	250	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	541	0	0
T210	0	559	0	0
T242	0	397	0	0
T254	0	454	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	664	0	0
T19	17432	8	0	0
T20	87664	0	0	0
T21	16135	29	0	0
T22	918069	0	0	0
T23	14118	3	0	0
T44	0	23	0	0
T54	2881	0	0	0
T74	0	5	0	0
T77	0	10	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	4	0	0
T210	0	10	0	0
T242	0	13	0	0
T254	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T19
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T18,T19,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T18,T19,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T18,T19,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T16,T17,T18
1	1	Covered	T18,T19,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T21
0	1	Covered	T231,T233,T95
1	0	Covered	T69,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T21
0	1	Covered	T18,T19,T21
1	0	Covered	T261

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T19,T21
1	-	Covered	T18,T19,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T19,T21
0	1	Covered	T18,T19,T21
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T21
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T19,T21
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T19,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T56,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T19,T21
DetectSt	-	-	-	-	1	-	-	Covered	T231,T233,T95
DetectSt	-	-	-	-	0	1	-	Covered	T18,T19,T21
DetectSt	-	-	-	-	0	0	-	Covered	T18,T19,T21
StableSt	-	-	-	-	-	-	1	Covered	T18,T19,T21
StableSt	-	-	-	-	-	-	0	Covered	T18,T19,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	842	0	0
CntIncr_A	8322531	46303	0	0
CntNoWrap_A	8322531	7633666	0	0
DetectStDropOut_A	8322531	43	0	0
DetectedOut_A	8322531	16283	0	0
DetectedPulseOut_A	8322531	353	0	0
DisabledIdleSt_A	8322531	7228416	0	0
DisabledNoDetection_A	8322531	7230175	0	0
EnterDebounceSt_A	8322531	443	0	0
EnterDetectSt_A	8322531	399	0	0
EnterStableSt_A	8322531	353	0	0
PulseIsPulse_A	8322531	353	0	0
StayInStableSt	8322531	15892	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	313	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	842	0	0
T18	35857	12	0	0
T19	17432	2	0	0
T20	87664	0	0	0
T21	16135	4	0	0
T23	0	2	0	0
T44	0	4	0	0
T45	0	5	0	0
T56	0	10	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	2	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	46303	0	0
T18	35857	576	0	0
T19	17432	93	0	0
T20	87664	0	0	0
T21	16135	148	0	0
T23	0	56	0	0
T44	0	146	0	0
T45	0	323	0	0
T56	0	625	0	0
T57	0	429	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	42	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	128	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7633666	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	43	0	0
T64	3891	0	0	0
T70	0	1	0	0
T89	783	0	0	0
T95	5076	3	0	0
T102	0	4	0	0
T109	0	1	0	0
T231	40667	8	0	0
T232	493	0	0	0
T233	22342	1	0	0
T234	492	0	0	0
T235	1873	0	0	0
T236	522	0	0	0
T242	21228	0	0	0
T262	0	6	0	0
T263	0	3	0	0
T264	0	4	0	0
T265	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	16283	0	0
T18	35857	560	0	0
T19	17432	54	0	0
T20	87664	0	0	0
T21	16135	129	0	0
T23	0	80	0	0
T44	0	89	0	0
T45	0	169	0	0
T56	0	179	0	0
T57	0	16	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	47	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	66	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	353	0	0
T18	35857	6	0	0
T19	17432	1	0	0
T20	87664	0	0	0
T21	16135	2	0	0
T23	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0
T56	0	4	0	0
T57	0	3	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7228416	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	15480	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7230175	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	15504	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	443	0	0
T18	35857	6	0	0
T19	17432	1	0	0
T20	87664	0	0	0
T21	16135	2	0	0
T23	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T56	0	6	0	0
T57	0	3	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	399	0	0
T18	35857	6	0	0
T19	17432	1	0	0
T20	87664	0	0	0
T21	16135	2	0	0
T23	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0
T56	0	4	0	0
T57	0	3	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	353	0	0
T18	35857	6	0	0
T19	17432	1	0	0
T20	87664	0	0	0
T21	16135	2	0	0
T23	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0
T56	0	4	0	0
T57	0	3	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	353	0	0
T18	35857	6	0	0
T19	17432	1	0	0
T20	87664	0	0	0
T21	16135	2	0	0
T23	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0
T56	0	4	0	0
T57	0	3	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	15892	0	0
T18	35857	554	0	0
T19	17432	53	0	0
T20	87664	0	0	0
T21	16135	127	0	0
T23	0	79	0	0
T44	0	87	0	0
T45	0	167	0	0
T56	0	175	0	0
T57	0	13	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	46	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	64	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	313	0	0
T18	35857	6	0	0
T19	17432	1	0	0
T20	87664	0	0	0
T21	16135	2	0	0
T23	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0
T56	0	4	0	0
T57	0	3	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	1	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T94	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T21,T23
1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T23
1	0	Covered	T19,T21,T23
1	1	Covered	T19,T21,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T23
0	1	Covered	T75,T76,T242
1	0	Covered	T44,T77,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T23
0	1	Covered	T19,T21,T23
1	0	Covered	T69,T219,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T23
1	-	Covered	T19,T21,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T23
0	1	Covered	T19,T21,T23
0	0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T23
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T23
IdleSt	0	-	-	-	-	-	-	Covered	T19,T21,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T21,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T75,T69
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T23
DetectSt	-	-	-	-	1	-	-	Covered	T44,T77,T75
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T23
DetectSt	-	-	-	-	0	0	-	Covered	T19,T21,T23
StableSt	-	-	-	-	-	-	1	Covered	T19,T21,T23
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	3135	0	0
CntIncr_A	8322531	117395	0	0
CntNoWrap_A	8322531	7631373	0	0
DetectStDropOut_A	8322531	464	0	0
DetectedOut_A	8322531	73968	0	0
DetectedPulseOut_A	8322531	861	0	0
DisabledIdleSt_A	8322531	7159563	0	0
DisabledNoDetection_A	8322531	7161864	0	0
EnterDebounceSt_A	8322531	1596	0	0
EnterDetectSt_A	8322531	1540	0	0
EnterStableSt_A	8322531	861	0	0
PulseIsPulse_A	8322531	861	0	0
StayInStableSt	8322531	73014	0	0
gen_high_event_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	760	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	3135	0	0
T19	17432	60	0	0
T20	87664	0	0	0
T21	16135	56	0	0
T22	918069	0	0	0
T23	14118	10	0	0
T44	0	18	0	0
T54	2881	0	0	0
T74	0	16	0	0
T75	0	25	0	0
T76	0	34	0	0
T77	0	8	0	0
T84	0	1	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	117395	0	0
T19	17432	2460	0	0
T20	87664	0	0	0
T21	16135	1652	0	0
T22	918069	0	0	0
T23	14118	410	0	0
T44	0	729	0	0
T54	2881	0	0	0
T74	0	672	0	0
T75	0	6108	0	0
T76	0	1030	0	0
T77	0	214	0	0
T84	0	40	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	1547	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7631373	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	464	0	0
T63	1186	0	0	0
T69	0	1	0	0
T75	13267	8	0	0
T76	0	10	0	0
T87	585	0	0	0
T96	0	20	0	0
T97	0	17	0	0
T98	0	3	0	0
T99	0	14	0	0
T119	28279	0	0	0
T121	55022	0	0	0
T242	0	3	0	0
T244	0	20	0	0
T245	0	26	0	0
T266	899	0	0	0
T267	502	0	0	0
T268	494	0	0	0
T269	8402	0	0	0
T270	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	73968	0	0
T19	17432	1664	0	0
T20	87664	0	0	0
T21	16135	2326	0	0
T22	918069	0	0	0
T23	14118	468	0	0
T54	2881	0	0	0
T71	0	4639	0	0
T74	0	384	0	0
T78	0	4646	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	1512	0	0
T210	0	1177	0	0
T214	0	3202	0	0
T254	0	209	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	861	0	0
T19	17432	30	0	0
T20	87664	0	0	0
T21	16135	28	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T54	2881	0	0	0
T71	0	14	0	0
T74	0	8	0	0
T78	0	25	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	17	0	0
T210	0	16	0	0
T214	0	23	0	0
T254	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7159563	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7161864	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1596	0	0
T19	17432	30	0	0
T20	87664	0	0	0
T21	16135	28	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T44	0	9	0	0
T54	2881	0	0	0
T74	0	8	0	0
T75	0	17	0	0
T76	0	17	0	0
T77	0	4	0	0
T84	0	1	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1540	0	0
T19	17432	30	0	0
T20	87664	0	0	0
T21	16135	28	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T44	0	9	0	0
T54	2881	0	0	0
T74	0	8	0	0
T75	0	8	0	0
T76	0	17	0	0
T77	0	4	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	17	0	0
T254	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	861	0	0
T19	17432	30	0	0
T20	87664	0	0	0
T21	16135	28	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T54	2881	0	0	0
T71	0	14	0	0
T74	0	8	0	0
T78	0	25	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	17	0	0
T210	0	16	0	0
T214	0	23	0	0
T254	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	861	0	0
T19	17432	30	0	0
T20	87664	0	0	0
T21	16135	28	0	0
T22	918069	0	0	0
T23	14118	5	0	0
T54	2881	0	0	0
T71	0	14	0	0
T74	0	8	0	0
T78	0	25	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	17	0	0
T210	0	16	0	0
T214	0	23	0	0
T254	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	73014	0	0
T19	17432	1630	0	0
T20	87664	0	0	0
T21	16135	2296	0	0
T22	918069	0	0	0
T23	14118	461	0	0
T54	2881	0	0	0
T71	0	4625	0	0
T74	0	376	0	0
T78	0	4620	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	1491	0	0
T210	0	1160	0	0
T214	0	3174	0	0
T254	0	203	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	760	0	0
T19	17432	26	0	0
T20	87664	0	0	0
T21	16135	26	0	0
T22	918069	0	0	0
T23	14118	3	0	0
T54	2881	0	0	0
T71	0	14	0	0
T74	0	8	0	0
T78	0	24	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	13	0	0
T210	0	15	0	0
T214	0	18	0	0
T254	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T19
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T16,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T16,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T16,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T56,T271,T157
1	0	Covered	T69,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
1	0	Covered	T71,T72,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T19
1	-	Covered	T16,T18,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T19
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T19
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T94,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T19
DetectSt	-	-	-	-	1	-	-	Covered	T56,T271,T69
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T19
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T19
StableSt	-	-	-	-	-	-	1	Covered	T16,T18,T19
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	870	0	0
CntIncr_A	8322531	47956	0	0
CntNoWrap_A	8322531	7633638	0	0
DetectStDropOut_A	8322531	28	0	0
DetectedOut_A	8322531	17208	0	0
DetectedPulseOut_A	8322531	379	0	0
DisabledIdleSt_A	8322531	7220020	0	0
DisabledNoDetection_A	8322531	7221798	0	0
EnterDebounceSt_A	8322531	460	0	0
EnterDetectSt_A	8322531	412	0	0
EnterStableSt_A	8322531	379	0	0
PulseIsPulse_A	8322531	379	0	0
StayInStableSt	8322531	16794	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	338	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	870	0	0
T16	26856	6	0	0
T17	14784	0	0	0
T18	35857	24	0	0
T19	0	8	0	0
T21	0	4	0	0
T23	0	2	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	2	0	0
T56	0	18	0	0
T57	0	12	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	11	0	0
T121	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	47956	0	0
T16	26856	248	0	0
T17	14784	0	0	0
T18	35857	1968	0	0
T19	0	288	0	0
T21	0	112	0	0
T23	0	84	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	139	0	0
T56	0	1420	0	0
T57	0	618	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	388	0	0
T121	0	276	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7633638	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19150	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	28	0	0
T46	11232	0	0	0
T56	51834	2	0	0
T57	18948	0	0	0
T62	1040	0	0	0
T77	14756	0	0	0
T83	1102	0	0	0
T85	671	0	0	0
T130	496	0	0	0
T149	0	5	0	0
T157	0	1	0	0
T263	0	4	0	0
T271	0	3	0	0
T272	0	5	0	0
T273	0	5	0	0
T274	0	2	0	0
T275	0	1	0	0
T276	427	0	0	0
T277	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	17208	0	0
T16	26856	33	0	0
T17	14784	0	0	0
T18	35857	316	0	0
T19	0	291	0	0
T21	0	165	0	0
T23	0	53	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	57	0	0
T56	0	26	0	0
T57	0	273	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	143	0	0
T121	0	255	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	379	0	0
T16	26856	3	0	0
T17	14784	0	0	0
T18	35857	12	0	0
T19	0	4	0	0
T21	0	2	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	1	0	0
T56	0	6	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	5	0	0
T121	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7220020	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	15480	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7221798	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	15504	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	460	0	0
T16	26856	3	0	0
T17	14784	0	0	0
T18	35857	12	0	0
T19	0	4	0	0
T21	0	2	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	1	0	0
T56	0	10	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	6	0	0
T121	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	412	0	0
T16	26856	3	0	0
T17	14784	0	0	0
T18	35857	12	0	0
T19	0	4	0	0
T21	0	2	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	1	0	0
T56	0	8	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	5	0	0
T121	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	379	0	0
T16	26856	3	0	0
T17	14784	0	0	0
T18	35857	12	0	0
T19	0	4	0	0
T21	0	2	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	1	0	0
T56	0	6	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	5	0	0
T121	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	379	0	0
T16	26856	3	0	0
T17	14784	0	0	0
T18	35857	12	0	0
T19	0	4	0	0
T21	0	2	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	1	0	0
T56	0	6	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	5	0	0
T121	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	16794	0	0
T16	26856	30	0	0
T17	14784	0	0	0
T18	35857	304	0	0
T19	0	284	0	0
T21	0	163	0	0
T23	0	52	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	56	0	0
T56	0	20	0	0
T57	0	267	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	138	0	0
T121	0	252	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	338	0	0
T16	26856	3	0	0
T17	14784	0	0	0
T18	35857	12	0	0
T19	0	1	0	0
T21	0	2	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T45	0	1	0	0
T56	0	6	0	0
T57	0	6	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T94	0	5	0	0
T121	0	3	0	0