Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T21,T23
1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T19,T21,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T23
1	0	Covered	T19,T21,T23
1	1	Covered	T19,T21,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T23
0	1	Covered	T76,T96,T98
1	0	Covered	T76,T96,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T23
0	1	Covered	T19,T21,T23
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T23
1	-	Covered	T19,T21,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T23
0	1	Covered	T19,T21,T23
0	0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T23
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T23
IdleSt	0	-	-	-	-	-	-	Covered	T19,T21,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T21,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T75,T69
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T23
DetectSt	-	-	-	-	1	-	-	Covered	T76,T96,T98
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T23
DetectSt	-	-	-	-	0	0	-	Covered	T19,T21,T23
StableSt	-	-	-	-	-	-	1	Covered	T19,T21,T23
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	3243	0	0
CntIncr_A	8322531	108423	0	0
CntNoWrap_A	8322531	7631265	0	0
DetectStDropOut_A	8322531	435	0	0
DetectedOut_A	8322531	78774	0	0
DetectedPulseOut_A	8322531	1000	0	0
DisabledIdleSt_A	8322531	7156682	0	0
DisabledNoDetection_A	8322531	7158972	0	0
EnterDebounceSt_A	8322531	1639	0	0
EnterDetectSt_A	8322531	1605	0	0
EnterStableSt_A	8322531	1000	0	0
PulseIsPulse_A	8322531	1000	0	0
StayInStableSt	8322531	77670	0	0
gen_high_event_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	892	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	3243	0	0
T19	17432	56	0	0
T20	87664	0	0	0
T21	16135	40	0	0
T22	918069	0	0	0
T23	14118	16	0	0
T44	0	58	0	0
T54	2881	0	0	0
T74	0	58	0	0
T75	0	25	0	0
T76	0	16	0	0
T77	0	44	0	0
T84	0	7	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	32	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	108423	0	0
T19	17432	2044	0	0
T20	87664	0	0	0
T21	16135	1240	0	0
T22	918069	0	0	0
T23	14118	728	0	0
T44	0	1827	0	0
T54	2881	0	0	0
T74	0	2552	0	0
T75	0	5141	0	0
T76	0	484	0	0
T77	0	594	0	0
T84	0	280	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	1136	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7631265	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	435	0	0
T65	2604	0	0	0
T69	0	1	0	0
T72	0	4	0	0
T76	15496	4	0	0
T88	664	0	0	0
T96	8228	8	0	0
T97	6104	0	0	0
T98	12450	4	0	0
T99	0	6	0	0
T142	0	4	0	0
T243	0	16	0	0
T245	0	26	0	0
T252	505	0	0	0
T253	871	0	0	0
T257	496	0	0	0
T258	404	0	0	0
T278	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	78774	0	0
T19	17432	1751	0	0
T20	87664	0	0	0
T21	16135	1266	0	0
T22	918069	0	0	0
T23	14118	1739	0	0
T44	0	1430	0	0
T54	2881	0	0	0
T74	0	2795	0	0
T75	0	799	0	0
T77	0	1456	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	1107	0	0
T242	0	2576	0	0
T254	0	398	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1000	0	0
T19	17432	28	0	0
T20	87664	0	0	0
T21	16135	20	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T44	0	29	0	0
T54	2881	0	0	0
T74	0	29	0	0
T75	0	9	0	0
T77	0	22	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	16	0	0
T242	0	31	0	0
T254	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7156682	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19156	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7158972	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1639	0	0
T19	17432	28	0	0
T20	87664	0	0	0
T21	16135	20	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T44	0	29	0	0
T54	2881	0	0	0
T74	0	29	0	0
T75	0	16	0	0
T76	0	8	0	0
T77	0	22	0	0
T84	0	7	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1605	0	0
T19	17432	28	0	0
T20	87664	0	0	0
T21	16135	20	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T44	0	29	0	0
T54	2881	0	0	0
T74	0	29	0	0
T75	0	9	0	0
T76	0	8	0	0
T77	0	22	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	16	0	0
T254	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1000	0	0
T19	17432	28	0	0
T20	87664	0	0	0
T21	16135	20	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T44	0	29	0	0
T54	2881	0	0	0
T74	0	29	0	0
T75	0	9	0	0
T77	0	22	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	16	0	0
T242	0	31	0	0
T254	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	1000	0	0
T19	17432	28	0	0
T20	87664	0	0	0
T21	16135	20	0	0
T22	918069	0	0	0
T23	14118	8	0	0
T44	0	29	0	0
T54	2881	0	0	0
T74	0	29	0	0
T75	0	9	0	0
T77	0	22	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	16	0	0
T242	0	31	0	0
T254	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	77670	0	0
T19	17432	1720	0	0
T20	87664	0	0	0
T21	16135	1245	0	0
T22	918069	0	0	0
T23	14118	1730	0	0
T44	0	1397	0	0
T54	2881	0	0	0
T74	0	2766	0	0
T75	0	790	0	0
T77	0	1431	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	1087	0	0
T242	0	2540	0	0
T254	0	388	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	892	0	0
T19	17432	25	0	0
T20	87664	0	0	0
T21	16135	19	0	0
T22	918069	0	0	0
T23	14118	7	0	0
T44	0	25	0	0
T54	2881	0	0	0
T74	0	29	0	0
T75	0	9	0	0
T77	0	19	0	0
T90	505	0	0	0
T91	411	0	0	0
T92	525	0	0	0
T93	426	0	0	0
T119	0	12	0	0
T242	0	26	0	0
T254	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T19
1	Covered	T43,T14,T31

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T43,T14,T31
1	1	Covered	T43,T14,T31

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T16,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T43,T14,T31	VC_COV_UNR
1	Covered	T16,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T43,T14,T31
1	Covered	T16,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T57,T94,T95
1	0	Covered	T69,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T23
1	0	Covered	T279

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T19
1	-	Covered	T16,T18,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
0	0	Excluded	T43,T14,T31	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T19
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T19
IdleSt	0	-	-	-	-	-	-	Covered	T43,T14,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T70
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T46,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T19
DetectSt	-	-	-	-	1	-	-	Covered	T57,T94,T95
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T19
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T19
StableSt	-	-	-	-	-	-	1	Covered	T16,T18,T23
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T43,T14,T31
0	Covered	T43,T14,T31

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8322531	904	0	0
CntIncr_A	8322531	48883	0	0
CntNoWrap_A	8322531	7633604	0	0
DetectStDropOut_A	8322531	67	0	0
DetectedOut_A	8322531	16828	0	0
DetectedPulseOut_A	8322531	359	0	0
DisabledIdleSt_A	8322531	7223087	0	0
DisabledNoDetection_A	8322531	7224871	0	0
EnterDebounceSt_A	8322531	475	0	0
EnterDetectSt_A	8322531	430	0	0
EnterStableSt_A	8322531	359	0	0
PulseIsPulse_A	8322531	359	0	0
StayInStableSt	8322531	16426	0	0
gen_high_level_sva.HighLevelEvent_A	8322531	7636997	0	0
gen_not_sticky_sva.StableStDropOut_A	8322531	310	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	904	0	0
T16	26856	18	0	0
T17	14784	0	0	0
T18	35857	6	0	0
T19	0	2	0	0
T23	0	2	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	8	0	0
T45	0	14	0	0
T46	0	3	0	0
T56	0	17	0	0
T57	0	8	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	48883	0	0
T16	26856	516	0	0
T17	14784	0	0	0
T18	35857	294	0	0
T19	0	76	0	0
T23	0	91	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	192	0	0
T45	0	1330	0	0
T46	0	117	0	0
T56	0	989	0	0
T57	0	592	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	129	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7633604	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	19138	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	67	0	0
T57	18948	4	0	0
T86	751	0	0	0
T94	6006	2	0	0
T95	0	8	0	0
T102	0	1	0	0
T105	0	8	0	0
T126	0	1	0	0
T131	749	0	0	0
T132	502	0	0	0
T133	437	0	0	0
T280	0	4	0	0
T281	0	7	0	0
T282	0	11	0	0
T283	0	5	0	0
T284	566	0	0	0
T285	422	0	0	0
T286	523	0	0	0
T287	452	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	16828	0	0
T16	26856	329	0	0
T17	14784	0	0	0
T18	35857	274	0	0
T19	0	68	0	0
T23	0	45	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	274	0	0
T45	0	47	0	0
T46	0	4	0	0
T56	0	368	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	134	0	0
T121	0	857	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	359	0	0
T16	26856	9	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	4	0	0
T45	0	7	0	0
T46	0	1	0	0
T56	0	7	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	3	0	0
T121	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7223087	0	0
T14	848	447	0	0
T15	939	538	0	0
T16	26856	15480	0	0
T17	14784	5262	0	0
T31	504	103	0	0
T32	414	13	0	0
T33	525	124	0	0
T34	493	92	0	0
T35	601	200	0	0
T43	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7224871	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	15504	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	475	0	0
T16	26856	9	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	4	0	0
T45	0	7	0	0
T46	0	3	0	0
T56	0	10	0	0
T57	0	4	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	430	0	0
T16	26856	9	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	4	0	0
T45	0	7	0	0
T46	0	1	0	0
T56	0	7	0	0
T57	0	4	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	359	0	0
T16	26856	9	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	4	0	0
T45	0	7	0	0
T46	0	1	0	0
T56	0	7	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	3	0	0
T121	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	359	0	0
T16	26856	9	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T19	0	1	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	4	0	0
T45	0	7	0	0
T46	0	1	0	0
T56	0	7	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	3	0	0
T121	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	16426	0	0
T16	26856	320	0	0
T17	14784	0	0	0
T18	35857	271	0	0
T19	0	66	0	0
T23	0	44	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	267	0	0
T45	0	40	0	0
T46	0	3	0	0
T56	0	361	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T77	0	128	0	0
T121	0	847	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	7636997	0	0
T14	848	448	0	0
T15	939	539	0	0
T16	26856	19186	0	0
T17	14784	5290	0	0
T31	504	104	0	0
T32	414	14	0	0
T33	525	125	0	0
T34	493	93	0	0
T35	601	201	0	0
T43	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8322531	310	0	0
T16	26856	8	0	0
T17	14784	0	0	0
T18	35857	3	0	0
T23	0	1	0	0
T33	525	0	0	0
T34	493	0	0	0
T35	601	0	0	0
T36	427	0	0	0
T44	0	1	0	0
T45	0	7	0	0
T46	0	1	0	0
T56	0	7	0	0
T59	448	0	0	0
T60	498	0	0	0
T61	652	0	0	0
T119	0	4	0	0
T121	0	10	0	0
T231	0	2	0	0