Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1397799430	9072	0	0
auto_block_debounce_ctl_rd_A	1397799430	2259	0	0
auto_block_out_ctl_rd_A	1397799430	3514	0	0
com_det_ctl_0_rd_A	1397799430	4535	0	0
com_det_ctl_1_rd_A	1397799430	4532	0	0
com_det_ctl_2_rd_A	1397799430	4601	0	0
com_det_ctl_3_rd_A	1397799430	4540	0	0
com_out_ctl_0_rd_A	1397799430	5352	0	0
com_out_ctl_1_rd_A	1397799430	5381	0	0
com_out_ctl_2_rd_A	1397799430	5384	0	0
com_out_ctl_3_rd_A	1397799430	5581	0	0
com_pre_det_ctl_0_rd_A	1397799430	1839	0	0
com_pre_det_ctl_1_rd_A	1397799430	1835	0	0
com_pre_det_ctl_2_rd_A	1397799430	1852	0	0
com_pre_det_ctl_3_rd_A	1397799430	1839	0	0
com_pre_sel_ctl_0_rd_A	1397799430	5705	0	0
com_pre_sel_ctl_1_rd_A	1397799430	5563	0	0
com_pre_sel_ctl_2_rd_A	1397799430	5301	0	0
com_pre_sel_ctl_3_rd_A	1397799430	5468	0	0
com_sel_ctl_0_rd_A	1397799430	5658	0	0
com_sel_ctl_1_rd_A	1397799430	5700	0	0
com_sel_ctl_2_rd_A	1397799430	5686	0	0
com_sel_ctl_3_rd_A	1397799430	5489	0	0
ec_rst_ctl_rd_A	1397799430	2971	0	0
intr_enable_rd_A	1397799430	2526	0	0
key_intr_ctl_rd_A	1397799430	5058	0	0
key_intr_debounce_ctl_rd_A	1397799430	1855	0	0
key_invert_ctl_rd_A	1397799430	6529	0	0
pin_allowed_ctl_rd_A	1397799430	6804	0	0
pin_out_ctl_rd_A	1397799430	5337	0	0
pin_out_value_rd_A	1397799430	5634	0	0
regwen_rd_A	1397799430	1934	0	0
ulp_ac_debounce_ctl_rd_A	1397799430	1828	0	0
ulp_ctl_rd_A	1397799430	1995	0	0
ulp_lid_debounce_ctl_rd_A	1397799430	1841	0	0
ulp_pwrb_debounce_ctl_rd_A	1397799430	1819	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	9072	0	0
T6	25641	0	0	0
T10	107193	9	0	0
T11	420293	9	0	0
T12	203785	0	0	0
T288	194438	358	0	0
T290	0	2	0	0
T291	52888	162	0	0
T292	112123	581	0	0
T293	0	330	0	0
T294	0	258	0	0
T295	0	139	0	0
T303	0	1	0	0
T304	48879	0	0	0
T305	48586	0	0	0
T306	99171	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	2259	0	0
T1	51077	0	0	0
T2	33610	1	0	0
T3	197487	0	0	0
T5	0	5	0	0
T7	277204	3	0	0
T8	202787	222	0	0
T10	0	111	0	0
T11	0	104	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	114	0	0
T28	195156	0	0	0
T291	0	6	0	0
T292	0	2	0	0
T294	0	1	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	3514	0	0
T1	51077	0	0	0
T2	33610	20	0	0
T3	197487	29	0	0
T5	0	6	0	0
T7	277204	6	0	0
T8	202787	215	0	0
T10	0	255	0	0
T11	0	232	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	103	0	0
T28	195156	0	0	0
T291	0	1	0	0
T292	0	18	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	4535	0	0
T1	51077	0	0	0
T2	33610	4	0	0
T3	197487	0	0	0
T7	277204	8	0	0
T8	202787	227	0	0
T10	0	79	0	0
T11	0	52	0	0
T13	0	4	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	143	0	0
T28	195156	0	0	0
T37	0	37	0	0
T291	0	10	0	0
T292	0	13	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	4532	0	0
T2	33610	1	0	0
T3	197487	2	0	0
T5	0	9	0	0
T8	202787	234	0	0
T10	0	78	0	0
T11	0	83	0	0
T13	0	4	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	145	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T37	0	6	0	0
T292	0	18	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	4601	0	0
T2	33610	5	0	0
T3	197487	2	0	0
T8	202787	228	0	0
T10	0	50	0	0
T11	0	69	0	0
T13	0	6	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	108	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T291	0	5	0	0
T292	0	16	0	0
T294	0	7	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	4540	0	0
T1	51077	0	0	0
T2	33610	8	0	0
T3	197487	0	0	0
T7	277204	5	0	0
T8	202787	245	0	0
T10	0	63	0	0
T11	0	69	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	111	0	0
T28	195156	0	0	0
T37	0	37	0	0
T290	0	49	0	0
T291	0	8	0	0
T292	0	10	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5352	0	0
T2	33610	19	0	0
T3	197487	26	0	0
T5	0	13	0	0
T8	202787	215	0	0
T10	0	235	0	0
T11	0	176	0	0
T13	0	4	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	54	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T291	0	1	0	0
T292	0	8	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5381	0	0
T2	33610	6	0	0
T3	197487	9	0	0
T5	0	10	0	0
T8	202787	236	0	0
T10	0	167	0	0
T11	0	99	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	92	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T37	0	47	0	0
T291	0	11	0	0
T292	0	21	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5384	0	0
T2	33610	8	0	0
T3	197487	13	0	0
T5	0	18	0	0
T8	202787	221	0	0
T10	0	155	0	0
T11	0	187	0	0
T13	0	1	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	138	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T291	0	1	0	0
T292	0	8	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5581	0	0
T1	51077	0	0	0
T2	33610	0	0	0
T3	197487	9	0	0
T7	277204	5	0	0
T8	202787	203	0	0
T10	0	216	0	0
T11	0	175	0	0
T13	0	25	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	106	0	0
T28	195156	0	0	0
T37	0	53	0	0
T291	0	1	0	0
T292	0	20	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1839	0	0
T1	51077	0	0	0
T2	33610	2	0	0
T3	197487	3	0	0
T5	0	1	0	0
T7	277204	9	0	0
T8	202787	203	0	0
T10	0	69	0	0
T11	0	68	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	120	0	0
T28	195156	0	0	0
T291	0	5	0	0
T292	0	9	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1835	0	0
T1	51077	0	0	0
T2	33610	2	0	0
T3	197487	0	0	0
T5	0	4	0	0
T7	277204	9	0	0
T8	202787	264	0	0
T10	0	88	0	0
T11	0	62	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	128	0	0
T28	195156	0	0	0
T291	0	9	0	0
T292	0	36	0	0
T294	0	3	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1852	0	0
T1	51077	0	0	0
T2	33610	0	0	0
T3	197487	2	0	0
T5	0	4	0	0
T7	277204	2	0	0
T8	202787	198	0	0
T10	0	91	0	0
T11	0	83	0	0
T13	0	4	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	94	0	0
T28	195156	0	0	0
T37	0	42	0	0
T292	0	24	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1839	0	0
T1	51077	0	0	0
T2	33610	2	0	0
T3	197487	2	0	0
T5	0	9	0	0
T7	277204	6	0	0
T8	202787	234	0	0
T10	0	92	0	0
T11	0	75	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	84	0	0
T28	195156	0	0	0
T291	0	4	0	0
T292	0	6	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5705	0	0
T2	33610	27	0	0
T3	197487	2	0	0
T5	0	21	0	0
T8	202787	248	0	0
T10	0	219	0	0
T11	0	176	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	94	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T291	0	1	0	0
T292	0	23	0	0
T294	0	4	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5563	0	0
T2	33610	7	0	0
T3	197487	5	0	0
T5	0	6	0	0
T8	202787	186	0	0
T10	0	268	0	0
T11	0	216	0	0
T13	0	6	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	94	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T37	0	16	0	0
T292	0	37	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5301	0	0
T1	51077	0	0	0
T2	33610	22	0	0
T3	197487	2	0	0
T5	0	9	0	0
T7	277204	9	0	0
T8	202787	213	0	0
T10	0	179	0	0
T11	0	207	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	120	0	0
T28	195156	0	0	0
T37	0	71	0	0
T292	0	16	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5468	0	0
T2	33610	15	0	0
T3	197487	27	0	0
T5	0	8	0	0
T8	202787	208	0	0
T10	0	296	0	0
T11	0	175	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	103	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T291	0	7	0	0
T292	0	5	0	0
T294	0	2	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5658	0	0
T1	51077	0	0	0
T2	33610	0	0	0
T3	197487	5	0	0
T5	0	9	0	0
T7	277204	6	0	0
T8	202787	240	0	0
T10	0	196	0	0
T11	0	193	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	124	0	0
T28	195156	0	0	0
T37	0	52	0	0
T291	0	4	0	0
T292	0	22	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5700	0	0
T2	33610	17	0	0
T3	197487	19	0	0
T8	202787	171	0	0
T10	0	239	0	0
T11	0	219	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	75	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T37	0	78	0	0
T290	0	138	0	0
T291	0	23	0	0
T292	0	1	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5686	0	0
T2	33610	19	0	0
T3	197487	17	0	0
T5	0	12	0	0
T8	202787	213	0	0
T10	0	267	0	0
T11	0	197	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	113	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T291	0	8	0	0
T292	0	2	0	0
T294	0	5	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5489	0	0
T1	51077	0	0	0
T2	33610	7	0	0
T3	197487	21	0	0
T5	0	23	0	0
T7	277204	7	0	0
T8	202787	244	0	0
T10	0	192	0	0
T11	0	142	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	110	0	0
T28	195156	0	0	0
T291	0	5	0	0
T292	0	13	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	2971	0	0
T1	51077	0	0	0
T2	33610	3	0	0
T3	197487	9	0	0
T5	0	1	0	0
T7	277204	3	0	0
T8	202787	217	0	0
T10	0	70	0	0
T11	0	63	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	113	0	0
T28	195156	0	0	0
T292	0	14	0	0
T294	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	2526	0	0
T1	51077	0	0	0
T2	33610	8	0	0
T3	197487	6	0	0
T5	0	1	0	0
T7	277204	2	0	0
T8	202787	454	0	0
T10	0	74	0	0
T11	0	78	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	95	0	0
T28	195156	0	0	0
T292	0	23	0	0
T307	0	10	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5058	0	0
T1	51077	0	0	0
T2	33610	2	0	0
T3	197487	2	0	0
T5	0	27	0	0
T7	277204	4	0	0
T8	202787	198	0	0
T10	0	445	0	0
T11	0	560	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	90	0	0
T28	195156	0	0	0
T292	0	13	0	0
T294	0	6	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1855	0	0
T1	51077	0	0	0
T2	33610	6	0	0
T3	197487	1	0	0
T5	0	4	0	0
T7	277204	8	0	0
T8	202787	189	0	0
T10	0	86	0	0
T11	0	56	0	0
T13	0	9	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	128	0	0
T28	195156	0	0	0
T292	0	23	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	6529	0	0
T1	51077	0	0	0
T2	33610	48	0	0
T3	197487	40	0	0
T5	0	47	0	0
T7	277204	2	0	0
T8	202787	219	0	0
T10	0	371	0	0
T11	0	472	0	0
T13	0	2	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	107	0	0
T28	195156	0	0	0
T292	0	9	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	6804	0	0
T2	33610	80	0	0
T3	197487	54	0	0
T5	0	66	0	0
T8	202787	236	0	0
T10	0	399	0	0
T11	0	465	0	0
T13	0	27	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	115	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T37	0	48	0	0
T292	0	13	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5337	0	0
T1	51077	0	0	0
T2	33610	2	0	0
T3	197487	15	0	0
T5	0	16	0	0
T7	277204	5	0	0
T8	202787	224	0	0
T10	0	459	0	0
T11	0	271	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	119	0	0
T28	195156	0	0	0
T291	0	3	0	0
T292	0	17	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	5634	0	0
T2	33610	34	0	0
T3	197487	6	0	0
T5	0	6	0	0
T8	202787	219	0	0
T10	0	294	0	0
T11	0	363	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	106	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T37	0	83	0	0
T291	0	11	0	0
T292	0	26	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1934	0	0
T2	33610	8	0	0
T3	197487	2	0	0
T5	0	1	0	0
T8	202787	449	0	0
T10	0	88	0	0
T11	0	84	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	114	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T37	0	67	0	0
T290	0	32	0	0
T292	0	34	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1828	0	0
T1	51077	0	0	0
T2	33610	6	0	0
T3	197487	0	0	0
T5	0	2	0	0
T7	277204	3	0	0
T8	202787	197	0	0
T10	0	94	0	0
T11	0	61	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	113	0	0
T28	195156	0	0	0
T37	0	47	0	0
T290	0	27	0	0
T292	0	25	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1995	0	0
T2	33610	5	0	0
T3	197487	8	0	0
T5	0	6	0	0
T8	202787	293	0	0
T10	0	83	0	0
T11	0	61	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	122	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T37	0	42	0	0
T290	0	50	0	0
T292	0	6	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1841	0	0
T2	33610	4	0	0
T3	197487	0	0	0
T5	0	1	0	0
T8	202787	232	0	0
T10	0	51	0	0
T11	0	90	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	106	0	0
T28	195156	0	0	0
T29	51083	0	0	0
T30	99313	0	0	0
T37	0	25	0	0
T290	0	49	0	0
T291	0	10	0	0
T292	0	6	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1397799430	1819	0	0
T1	51077	0	0	0
T2	33610	0	0	0
T3	197487	2	0	0
T5	0	1	0	0
T7	277204	1	0	0
T8	202787	197	0	0
T10	0	81	0	0
T11	0	75	0	0
T24	48619	0	0	0
T25	98893	0	0	0
T26	193084	0	0	0
T27	367066	112	0	0
T28	195156	0	0	0
T291	0	3	0	0
T292	0	11	0	0
T294	0	1	0	0