SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
sysrst_ctrl_combo_precondition_det_cg0 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_precondition_det_cg1 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_precondition_det_cg2 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_precondition_det_cg3 | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_precondition_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_precondition_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_precondition_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_precondition_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 18 | 1 | T323 | 1 | T324 | 8 | T325 | 9 | ||||
mid_range | 1 | 1 | T54 | 1 | - | - | - | - | ||||
min_range | 286 | 1 | T14 | 8 | T48 | 3 | T49 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 1 | 1 | T326 | 1 | - | - | - | - | ||||
mid_range | 5 | 1 | T50 | 4 | T327 | 1 | - | - | ||||
min_range | 299 | 1 | T14 | 8 | T48 | 3 | T49 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 7 | 1 | T224 | 4 | T226 | 1 | T303 | 2 | ||||
mid_range | 1 | 1 | T327 | 1 | - | - | - | - | ||||
min_range | 297 | 1 | T14 | 8 | T48 | 3 | T49 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 6 | 1 | T296 | 3 | T328 | 2 | T327 | 1 | ||||
mid_range | 1 | 1 | T329 | 1 | - | - | - | - | ||||
min_range | 298 | 1 | T14 | 8 | T48 | 3 | T49 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |