Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 75.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_auto_blk_out_ctl_cg_(3) 0.00 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(4) 79.17 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(2) 95.83 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg 100.00 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(1) 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(3)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 12 0 0.00
Crosses 12 12 0 0.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 2 0 0.00 100 1 1 2
cp_key0_out_value 2 2 0 0.00 100 1 1 2
cp_key1_out_sel 2 2 0 0.00 100 1 1 2
cp_key1_out_value 2 2 0 0.00 100 1 1 2
cp_key2_out_sel 2 2 0 0.00 100 1 1 2
cp_key2_out_value 2 2 0 0.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 4 0 0.00 100 1 1 0
cross_key1_out_sel_value 4 4 0 0.00 100 1 1 0
cross_key2_out_sel_value 4 4 0 0.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(4)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
79.17 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 1 11 91.67
Crosses 12 4 8 66.67


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 1 1 50.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 2 2 50.00 100 1 1 0
cross_key1_out_sel_value 4 1 3 75.00 100 1 1 0
cross_key2_out_sel_value 4 1 3 75.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(2)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 1 11 91.67


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 1 3 75.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key0_out_sel

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key0_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key1_out_sel

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key1_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key2_out_sel

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key2_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 4 0 0.00 4


Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTNUMBERSTATUS
* * -- -- 4



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 4 0 0.00 4


Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTNUMBERSTATUS
* * -- -- 4



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 4 0 0.00 4


Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
* * -- -- 4


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T330 1
auto[1] 2 1 T330 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_key0_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 3 1 T330 3



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 2 1 T330 2
auto[1] 1 1 T330 1



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 2 1 T330 2
auto[1] 1 1 T330 1



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T330 1
auto[1] 2 1 T330 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 2 1 T330 2
auto[1] 1 1 T330 1



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cross_key0_out_sel_value

Element holes
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] * -- -- 2


Covered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[0] 1 1 T330 1
auto[0] auto[1] 2 1 T330 2



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] 0 1 1


Covered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[0] 1 1 T330 1
auto[0] auto[1] 1 1 T330 1
auto[1] auto[0] 1 1 T330 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[0] 1 1 T330 1
auto[0] auto[1] 1 1 T330 1
auto[1] auto[1] 1 1 T330 1


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4 1 T83 1 T80 2 T331 1
auto[1] 5 1 T83 2 T80 1 T331 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4 1 T83 1 T80 1 T331 2
auto[1] 5 1 T83 2 T80 2 T331 1



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5 1 T83 2 T80 1 T331 2
auto[1] 4 1 T83 1 T80 2 T331 1



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4 1 T80 2 T331 2 - -
auto[1] 5 1 T83 3 T80 1 T331 1



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8 1 T83 3 T80 2 T331 3
auto[1] 1 1 T80 1 - - - -



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7 1 T83 2 T80 3 T331 2
auto[1] 2 1 T83 1 T331 1 - -



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2 1 T80 1 T331 1 - -
auto[0] auto[1] 2 1 T83 1 T331 1 - -
auto[1] auto[0] 2 1 T83 1 T80 1 - -
auto[1] auto[1] 3 1 T83 1 T80 1 T331 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 2 1 T331 2 - -
auto[0] auto[1] 2 1 T80 2 - -
auto[1] auto[0] 3 1 T83 2 T80 1
auto[1] auto[1] 2 1 T83 1 T331 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] 0 1 1


Covered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 6 1 T83 2 T80 2 T331 2
auto[0] auto[1] 1 1 T80 1 - - - -
auto[1] auto[0] 2 1 T83 1 T331 1 - -


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 129 1 T12 3 T85 3 T86 1
auto[1] 118 1 T86 2 T44 2 T87 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 120 1 T12 2 T85 1 T86 2
auto[1] 127 1 T12 1 T85 2 T86 1



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 125 1 T85 2 T86 1 T44 1
auto[1] 122 1 T12 3 T85 1 T86 2



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 118 1 T85 1 T86 2 T87 1
auto[1] 129 1 T12 3 T85 2 T86 1



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 123 1 T85 1 T87 3 T88 1
auto[1] 124 1 T12 3 T85 2 T86 3



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 121 1 T12 2 T85 2 T86 2
auto[1] 126 1 T12 1 T85 1 T86 1



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 63 1 T12 2 T85 1 T86 1
auto[0] auto[1] 57 1 T86 1 T44 1 T87 2
auto[1] auto[0] 66 1 T12 1 T85 2 T44 1
auto[1] auto[1] 61 1 T86 1 T44 1 T88 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 63 1 T85 1 T86 1 T88 1
auto[0] auto[1] 55 1 T86 1 T87 1 T88 1
auto[1] auto[0] 62 1 T85 1 T44 1 T87 1
auto[1] auto[1] 67 1 T12 3 T85 1 T86 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 59 1 T85 1 T87 2 T89 1
auto[0] auto[1] 62 1 T12 2 T85 1 T86 2
auto[1] auto[0] 64 1 T87 1 T88 1 T90 1
auto[1] auto[1] 62 1 T12 1 T85 1 T86 1


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12 1 T45 2 T83 2 T332 3
auto[1] 15 1 T45 1 T64 3 T83 1



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14 1 T45 3 T83 3 T332 1
auto[1] 13 1 T64 3 T332 2 T80 2



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14 1 T45 2 T64 3 T83 2
auto[1] 13 1 T45 1 T83 1 T332 1



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13 1 T45 1 T64 1 T83 1
auto[1] 14 1 T45 2 T64 2 T83 2



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11 1 T45 1 T64 2 T83 1
auto[1] 16 1 T45 2 T64 1 T83 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12 1 T45 1 T83 3 T80 1
auto[1] 15 1 T45 2 T64 3 T332 3



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 7 1 T45 2 T83 2 T332 1
auto[0] auto[1] 7 1 T45 1 T83 1 T80 1
auto[1] auto[0] 5 1 T332 2 T80 1 T102 1
auto[1] auto[1] 8 1 T64 3 T80 1 T330 3



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 7 1 T45 1 T64 1 T83 1
auto[0] auto[1] 6 1 T332 1 T80 1 T330 1
auto[1] auto[0] 7 1 T45 1 T64 2 T83 1
auto[1] auto[1] 7 1 T45 1 T83 1 T80 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 7 1 T45 1 T83 1 T330 1
auto[0] auto[1] 5 1 T83 2 T80 1 T330 1
auto[1] auto[0] 4 1 T64 2 T332 1 T80 1
auto[1] auto[1] 11 1 T45 2 T64 1 T332 2

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