Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	1	30	96.77	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1712

1

T12

9

T13

36

T14

38

auto[1]

552

1

T14

18

T17

20

T18

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1695

1

T12

9

T13

21

T14

56

auto[1]

569

1

T13

15

T18

2

T48

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1710

1

T12

8

T13

36

T14

41

auto[1]

554

1

T12

1

T14

15

T17

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T13

27

T14

30

T17

18

auto[1]

661

1

T12

9

T13

9

T14

26

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1998

1

T12

9

T13

36

T14

54

auto[1]

266

1

T14

2

T48

1

T52

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2107

1

T12

9

T13

36

T14

28

auto[1]

157

1

T14

28

T48

1

T50

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2125

1

T12

9

T13

36

T14

51

auto[1]

139

1

T14

5

T48

2

T50

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2130

1

T12

9

T13

36

T14

49

auto[1]

134

1

T14

7

T48

2

T50

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2132

1

T12

9

T13

36

T14

28

auto[1]

132

1

T14

28

T48

1

T53

7

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1531

1

T12

1

T13

15

T14

56

auto[1]

733

1

T12

8

T13

21

T17

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	976	1			T12	9		T13	36		T17	25
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	166	1			T52	2		T227	5		T230	13
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	44	1			T53	7		T224	4		T229	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	15	1			T296	4		T297	2		T295	9
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	48	1			T52	4		T92	1		T224	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	26	1			T52	1		T227	3		T298	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	4	1			T52	3		T220	1		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	4	1			T299	2		T300	2		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	52	1			T220	4		T223	3		T229	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	23	1			T225	6		T230	7		T221	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T245	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T301	4		T302	2		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	7	1			T14	5		T303	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	4	1			T48	1		T226	3		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	49	1			T245	2		T230	26		T304	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	9	1			T221	4		T305	4		T293	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	38	1			T14	26		T50	2		T302	8
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T285	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	10	1			T228	1		T306	3		T307	2
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T227	3		T308	2		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T14	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	12	1			T298	3		T305	3		T285	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	5	1			T301	3		T309	2		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	7	1			T50	3		T302	4		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T48	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T298	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	1	30	96.77	1
Automatically Generated Cross Bins	31	1	30	96.77	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Uncovered bins

cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

57

1

T14

5

T17

11

T50

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

158

1

T13

12

T17

5

T48

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

81

1

T38

6

T40

6

T235

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

136

1

T44

1

T220

4

T95

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

73

1

T14

13

T17

7

T40

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

102

1

T12

8

T13

9

T44

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T231

4

T71

1

T247

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

123

1

T14

2

T18

9

T19

16

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

46

1

T18

5

T224

4

T227

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T44

1

T155

5

T73

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

36

1

T17

2

T19

2

T38

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T12

1

T14

13

T50

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T41

2

T64

1

T73

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41

1

T38

2

T71

1

T283

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T41

1

T236

2

T310

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

90

1

T13

15

T52

1

T179

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

56

1

T48

1

T40

4

T41

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T248

1

T179

2

T311

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T40

1

T223

3

T224

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

79

1

T38

3

T53

7

T52

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T236

1

T64

3

T237

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

15

1

T312

3

T313

4

T314

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T38

2

T155

2

T175

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T45

1

T220

1

T175

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T18

2

T247

4

T297

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T52

4

T124

2

T227

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T92

1

T64

3

T315

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

20

1

T292

5

T296

4

T316

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T38

1

T236

1

T310

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T235

3

T64

2

T72

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded