Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1123

1

T21

7

T38

28

T45

35

auto[1]

1093

1

T21

13

T38

32

T45

25

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T21

5

T38

18

T45

13

from_0to1

532

1

T21

6

T38

17

T45

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T21

10

T38

29

T45

27

auto[1]

1104

1

T21

10

T38

31

T45

33

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T21

8

T38

31

T45

25

auto[1]

1128

1

T21

12

T38

29

T45

35

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

82

1

T21

1

T38

1

T45

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T21

1

T38

2

T45

2

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T38

3

T45

5

T126

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T38

2

T45

2

T339

2

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T38

1

T45

2

T339

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T21

2

T38

1

T45

3

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T38

3

T340

1

T339

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T45

4

T340

2

T341

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T21

1

T340

3

T339

2

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T21

1

T38

4

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T38

2

T45

2

T339

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T21

1

T38

4

T342

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T21

1

T38

3

T45

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T38

2

T45

1

T340

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T38

4

T339

1

T342

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T21

3

T38

3

T45

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1111

1

T21

13

T38

35

T45

27

auto[1]

1105

1

T21

7

T38

25

T45

33

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T21

6

T38

14

T45

13

from_0to1

520

1

T21

5

T38

14

T45

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T21

9

T38

33

T45

27

auto[1]

1080

1

T21

11

T38

27

T45

33

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T21

10

T38

31

T45

29

auto[1]

1092

1

T21

10

T38

29

T45

31

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T21

1

T45

1

T340

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T21

1

T38

3

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T21

1

T38

1

T45

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T21

2

T38

3

T45

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T38

2

T45

4

T339

2

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T21

1

T45

1

T340

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T38

3

T45

3

T339

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T38

2

T340

2

T341

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T21

1

T38

2

T45

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T38

3

T45

1

T339

1

auto[1]

from_1to0

auto[1]

auto[0]

85

1

T45

5

T340

1

T341

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T38

2

T340

2

T342

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T45

1

T339

1

T126

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T21

1

T38

2

T45

2

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T21

2

T38

4

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T21

1

T38

1

T339

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T21

10

T38

23

T45

32

auto[1]

1075

1

T21

10

T38

37

T45

28

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

553

1

T21

5

T38

12

T45

18

from_0to1

551

1

T21

5

T38

12

T45

18

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T21

10

T38

34

T45

30

auto[1]

1115

1

T21

10

T38

26

T45

30

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T21

9

T38

30

T45

35

auto[1]

1125

1

T21

11

T38

30

T45

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T21

2

T38

3

T45

2

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T45

3

T126

1

T129

1

auto[0]

from_1to0

auto[1]

auto[0]

48

1

T38

2

T45

1

T342

1

auto[0]

from_1to0

auto[1]

auto[1]

87

1

T38

1

T45

3

T340

3

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T21

1

T45

1

T341

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T21

1

T45

2

T340

2

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T38

1

T45

6

T341

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T38

2

T45

2

T340

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T38

1

T45

3

T340

1

auto[1]

from_1to0

auto[0]

auto[1]

81

1

T21

1

T38

1

T339

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T21

2

T38

2

T45

5

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T38

2

T45

1

T340

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T21

1

T38

2

T45

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T21

1

T38

5

T45

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T45

2

T340

1

T90

1

auto[1]

from_0to1

auto[1]

auto[1]

90

1

T21

1

T38

2

T45

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T21

6

T38

25

T45

36

auto[1]

1103

1

T21

14

T38

35

T45

24

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T21

4

T38

16

T45

15

from_0to1

527

1

T21

4

T38

15

T45

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T21

10

T38

33

T45

25

auto[1]

1109

1

T21

10

T38

27

T45

35

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T21

10

T38

26

T45

30

auto[1]

1109

1

T21

10

T38

34

T45

30

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T38

2

T45

1

T340

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T38

1

T45

3

T341

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T38

3

T45

4

T342

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T21

1

T38

2

T45

2

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T38

2

T45

2

T341

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T38

3

T45

1

T340

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T126

1

T342

2

T343

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T21

1

T38

2

T45

5

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T21

1

T38

3

T45

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T21

1

T38

3

T340

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T45

1

T340

1

T129

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T21

1

T38

2

T45

3

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T21

1

T45

1

T126

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T38

3

T340

1

T339

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T21

1

T38

3

T45

3

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T21

1

T38

2

T45

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T21

12

T38

23

T45

28

auto[1]

1130

1

T21

8

T38

37

T45

32

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

525

1

T21

5

T38

14

T45

11

from_0to1

528

1

T21

5

T38

15

T45

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T21

9

T38

25

T45

30

auto[1]

1130

1

T21

11

T38

35

T45

30

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T21

7

T38

34

T45

35

auto[1]

1104

1

T21

13

T38

26

T45

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T38

2

T45

3

T339

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T21

1

T45

1

T340

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T38

1

T45

2

T340

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T21

2

T38

1

T339

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T21

1

T38

2

T45

4

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T38

1

T45

2

T339

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T21

1

T340

1

T341

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T21

1

T38

3

T45

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T38

3

T45

1

T126

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T21

1

T38

2

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T38

1

T45

1

T341

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T21

1

T38

4

T45

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T21

1

T45

1

T339

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T38

4

T45

2

T342

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T38

4

T45

1

T339

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T21

1

T38

1

T45

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T21

12

T38

36

T45

24

auto[1]

1094

1

T21

8

T38

24

T45

36

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

546

1

T21

6

T38

16

T45

13

from_0to1

539

1

T21

5

T38

15

T45

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T21

9

T38

40

T45

32

auto[1]

1063

1

T21

11

T38

20

T45

28

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T21

10

T38

35

T45

38

auto[1]

1069

1

T21

10

T38

25

T45

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T38

4

T45

1

T339

1

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T21

1

T38

1

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T21

3

T38

2

T45

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T21

1

T38

1

T45

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T21

1

T38

4

T45

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T38

3

T45

1

T340

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T45

3

T341

1

T126

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T21

1

T38

1

T45

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T38

2

T45

3

T340

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T38

2

T45

3

T344

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T38

2

T45

2

T339

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T21

1

T38

2

T340

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T21

1

T45

3

T340

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T38

4

T45

1

T129

2

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T38

2

T340

1

T126

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T21

2

T38

1

T45

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T21

8

T38

31

T45

29

auto[1]

1117

1

T21

12

T38

29

T45

31

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

521

1

T21

6

T38

15

T45

12

from_0to1

510

1

T21

5

T38

14

T45

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1119

1

T21

14

T38

33

T45

34

auto[1]

1097

1

T21

6

T38

27

T45

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T21

11

T38

27

T45

35

auto[1]

1094

1

T21

9

T38

33

T45

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T21

1

T38

3

T45

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T38

2

T45

4

T339

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T21

1

T38

1

T45

3

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T21

1

T38

3

T45

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T38

1

T340

2

T341

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T38

2

T45

1

T340

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T21

1

T38

1

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T21

1

T38

2

T45

2

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T21

2

T38

2

T45

2

auto[1]

from_1to0

auto[0]

auto[1]

84

1

T21

1

T45

1

T341

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T38

2

T339

1

T341

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T38

2

T340

2

T341

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T21

1

T38

2

T45

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T21

2

T38

4

T45

2

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T38

2

T45

3

T339

2

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T45

2

T339

1

T341

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T21

8

T38

33

T45

29

auto[1]

1121

1

T21

12

T38

27

T45

31

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T21

6

T38

10

T45

12

from_0to1

521

1

T21

5

T38

11

T45

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T21

10

T38

29

T45

28

auto[1]

1103

1

T21

10

T38

31

T45

32

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T21

10

T38

38

T45

36

auto[1]

1101

1

T21

10

T38

22

T45

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T21

1

T45

2

T340

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T38

3

T45

1

T339

2

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T21

2

T38

1

T45

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T21

1

T38

1

T45

2

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T21

1

T38

4

T45

4

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T340

1

T126

1

T90

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T38

1

T45

2

T341

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T339

1

T341

1

T162

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T38

1

T340

2

T342

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T21

2

T38

2

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T38

2

T45

3

T340

2

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T45

1

T126

1

T129

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T21

1

T38

3

T45

2

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T38

1

T45

2

T340

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T21

2

T38

2

T45

2

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T21

1

T339

1

T126

1