Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.58	57.58	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_wkup_event_cg	57.58	1	100	1	64	64

---

Group Instance : sysrst_ctrl_wkup_event_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.58	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_wkup_event_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	23	14	9	39.13

Variables for Group Instance sysrst_ctrl_wkup_event_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_h2l_pwrb	2	0	2	100.00	100	1	1	2
cp_h_ac_present	2	0	2	100.00	100	1	1	2
cp_interrupt_gen	2	0	2	100.00	100	1	1	2
cp_l2h_lid_open	2	0	2	100.00	100	1	1	2
cp_wakeup_sts	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_wkup_event_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_wkup_sts	23	14	9	39.13	100	1	1	0

Summary for Variable cp_h2l_pwrb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_h2l_pwrb

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

859

1

T2

1

T3

1

T4

6

auto[1]

757

1

T12

2

T16

3

T59

1

---

Summary for Variable cp_h_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_h_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

998

1

T2

1

T3

1

T4

6

auto[1]

618

1

T12

1

T16

2

T21

9

---

Summary for Variable cp_interrupt_gen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt_gen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1554

1

T2

1

T3

1

T4

6

auto[1]

62

1

T60

2

T63

4

T65

2

---

Summary for Variable cp_l2h_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_l2h_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T2

1

T3

1

T4

6

auto[1]

644

1

T12

1

T56

1

T21

10

---

Summary for Variable cp_wakeup_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wakeup_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1543

1

T2

1

T3

1

T4

6

auto[1]

73

1

T16

2

T38

1

T39

3

---

Summary for Cross cross_wkup_sts

Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	23	14	9	39.13	14
Automatically Generated Cross Bins	23	14	9	39.13	14
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_wkup_sts

Element holes

cp_wakeup_sts	cp_h2l_pwrb	cp_l2h_lid_open	cp_h_ac_present	cp_interrupt_gen	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	*	*	--	--	4

Covered bins

cp_wakeup_sts

cp_h2l_pwrb

cp_l2h_lid_open

cp_h_ac_present

cp_interrupt_gen

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

372

1

T2

1

T3

1

T4

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

143

1

T16

2

T21

3

T38

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

155

1

T56

1

T21

3

T68

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

181

1

T21

4

T38

2

T45

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

229

1

T16

1

T59

1

T21

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

140

1

T12

1

T21

1

T38

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

154

1

T12

1

T21

2

T68

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

147

1

T21

1

T38

4

T45

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

40

1

T60

1

T63

2

T65

2

User Defined Cross Bins for cross_wkup_sts

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded