Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117652

1

T1

1452

T7

293

T2

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141759	1			T1	2873		T7	74		T2	101
values[0x0]	63762	1			T1	42		T7	99		T2	23
values[0x1]	65094	1			T1	40		T7	194		T2	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

146431

1

T1

1733

T7

347

T2

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	890	1			T1	10		T7	1		T2	1
valid_sources[0x01]	1040	1			T1	7		T7	2		T2	1
valid_sources[0x02]	1028	1			T1	12		T7	2		T4	3
valid_sources[0x03]	1778	1			T1	13		T2	2		T3	1
valid_sources[0x04]	980	1			T1	9		T7	1		T2	1
valid_sources[0x05]	1031	1			T1	11		T7	1		T2	1
valid_sources[0x06]	976	1			T1	13		T7	3		T3	1
valid_sources[0x07]	912	1			T1	12		T3	3		T4	4
valid_sources[0x08]	2366	1			T1	17		T3	2		T4	4
valid_sources[0x09]	1677	1			T1	11		T7	3		T2	1
valid_sources[0x0a]	1255	1			T1	14		T4	8		T23	13
valid_sources[0x0b]	1219	1			T1	13		T2	1		T3	2
valid_sources[0x0c]	945	1			T1	9		T7	4		T3	1
valid_sources[0x0d]	834	1			T1	12		T3	1		T4	4
valid_sources[0x0e]	1273	1			T1	16		T7	1		T3	1
valid_sources[0x0f]	823	1			T1	14		T7	2		T3	3
valid_sources[0x10]	980	1			T1	18		T7	1		T3	1
valid_sources[0x11]	1446	1			T1	13		T7	5		T2	3
valid_sources[0x12]	990	1			T1	11		T7	1		T2	1
valid_sources[0x13]	988	1			T1	15		T7	1		T4	3
valid_sources[0x14]	813	1			T1	13		T7	1		T4	5
valid_sources[0x15]	959	1			T1	8		T7	2		T2	1
valid_sources[0x16]	898	1			T1	7		T7	1		T2	2
valid_sources[0x17]	2135	1			T1	17		T7	1		T3	1
valid_sources[0x18]	966	1			T1	13		T7	1		T4	10
valid_sources[0x19]	907	1			T1	10		T7	3		T4	4
valid_sources[0x1a]	1270	1			T1	11		T7	1		T2	2
valid_sources[0x1b]	844	1			T1	7		T7	1		T3	1
valid_sources[0x1c]	966	1			T1	10		T2	1		T3	1
valid_sources[0x1d]	947	1			T1	14		T7	2		T3	1
valid_sources[0x1e]	902	1			T1	13		T7	1		T4	1
valid_sources[0x1f]	886	1			T1	4		T4	3		T23	12
valid_sources[0x20]	952	1			T1	18		T7	1		T4	1
valid_sources[0x21]	902	1			T1	10		T7	2		T3	3
valid_sources[0x22]	1089	1			T1	8		T7	1		T2	2
valid_sources[0x23]	947	1			T1	10		T7	1		T2	1
valid_sources[0x24]	927	1			T1	15		T7	1		T3	1
valid_sources[0x25]	989	1			T1	4		T7	3		T2	2
valid_sources[0x26]	835	1			T1	13		T7	1		T3	1
valid_sources[0x27]	808	1			T1	15		T7	2		T3	1
valid_sources[0x28]	978	1			T1	6		T7	1		T4	3
valid_sources[0x29]	1047	1			T1	8		T7	3		T2	1
valid_sources[0x2a]	795	1			T1	16		T7	1		T3	1
valid_sources[0x2b]	909	1			T1	14		T7	1		T2	2
valid_sources[0x2c]	955	1			T1	14		T3	1		T4	2
valid_sources[0x2d]	799	1			T1	11		T7	1		T3	2
valid_sources[0x2e]	856	1			T1	8		T2	2		T3	1
valid_sources[0x2f]	950	1			T1	12		T7	2		T4	2
valid_sources[0x30]	813	1			T1	16		T7	2		T2	2
valid_sources[0x31]	985	1			T1	11		T4	13		T23	10
valid_sources[0x32]	1221	1			T1	13		T7	1		T2	1
valid_sources[0x33]	1193	1			T1	10		T7	1		T4	10
valid_sources[0x34]	974	1			T1	19		T7	1		T3	1
valid_sources[0x35]	963	1			T1	17		T2	1		T3	2
valid_sources[0x36]	901	1			T1	17		T7	2		T2	1
valid_sources[0x37]	905	1			T1	14		T2	1		T4	2
valid_sources[0x38]	924	1			T1	10		T2	1		T4	2
valid_sources[0x39]	1157	1			T1	9		T4	1		T23	5
valid_sources[0x3a]	1103	1			T1	11		T7	2		T4	4
valid_sources[0x3b]	1002	1			T1	6		T7	1		T3	1
valid_sources[0x3c]	871	1			T1	9		T7	3		T2	1
valid_sources[0x3d]	840	1			T1	9		T4	6		T23	7
valid_sources[0x3e]	972	1			T1	5		T7	3		T4	4
valid_sources[0x3f]	936	1			T1	9		T2	2		T4	3
valid_sources[0x40]	922	1			T1	12		T7	3		T2	1
valid_sources[0x41]	1110	1			T1	8		T2	1		T4	9
valid_sources[0x42]	1005	1			T1	12		T7	6		T3	1
valid_sources[0x43]	823	1			T1	9		T3	2		T23	16
valid_sources[0x44]	931	1			T1	11		T7	3		T4	4
valid_sources[0x45]	945	1			T1	14		T7	1		T2	1
valid_sources[0x46]	2042	1			T1	10		T7	1		T3	1
valid_sources[0x47]	1039	1			T1	20		T7	3		T2	1
valid_sources[0x48]	777	1			T1	14		T4	2		T23	7
valid_sources[0x49]	842	1			T1	8		T2	1		T22	21
valid_sources[0x4a]	1924	1			T1	15		T7	5		T4	16
valid_sources[0x4b]	934	1			T1	6		T7	1		T2	1
valid_sources[0x4c]	912	1			T1	4		T7	1		T3	1
valid_sources[0x4d]	860	1			T1	13		T4	9		T23	12
valid_sources[0x4e]	819	1			T1	6		T7	2		T2	2
valid_sources[0x4f]	1155	1			T1	16		T7	1		T3	2
valid_sources[0x50]	913	1			T1	14		T7	1		T4	2
valid_sources[0x51]	1272	1			T1	9		T7	1		T3	1
valid_sources[0x52]	870	1			T1	10		T7	2		T4	4
valid_sources[0x53]	1900	1			T1	10		T2	1		T4	2
valid_sources[0x54]	1010	1			T1	9		T7	3		T3	1
valid_sources[0x55]	1106	1			T1	8		T7	2		T4	4
valid_sources[0x56]	957	1			T1	16		T2	1		T3	1
valid_sources[0x57]	1251	1			T1	6		T3	3		T4	1
valid_sources[0x58]	882	1			T1	10		T7	1		T3	1
valid_sources[0x59]	1016	1			T1	12		T7	3		T4	13
valid_sources[0x5a]	926	1			T1	15		T3	1		T4	6
valid_sources[0x5b]	789	1			T1	11		T7	1		T4	2
valid_sources[0x5c]	1245	1			T1	17		T2	2		T3	2
valid_sources[0x5d]	1023	1			T1	16		T4	4		T23	12
valid_sources[0x5e]	999	1			T1	7		T7	7		T3	1
valid_sources[0x5f]	1072	1			T1	9		T7	1		T4	2
valid_sources[0x60]	1501	1			T1	13		T7	1		T3	1
valid_sources[0x61]	887	1			T1	12		T7	3		T2	1
valid_sources[0x62]	1514	1			T1	10		T3	1		T4	3
valid_sources[0x63]	1118	1			T1	12		T4	4		T23	11
valid_sources[0x64]	932	1			T1	7		T7	2		T2	3
valid_sources[0x65]	967	1			T1	15		T2	2		T3	1
valid_sources[0x66]	911	1			T1	18		T7	1		T4	3
valid_sources[0x67]	879	1			T1	9		T7	3		T2	1
valid_sources[0x68]	1454	1			T1	5		T4	5		T23	5
valid_sources[0x69]	837	1			T1	8		T7	2		T2	1
valid_sources[0x6a]	946	1			T1	14		T7	1		T2	1
valid_sources[0x6b]	927	1			T1	8		T7	1		T4	7
valid_sources[0x6c]	869	1			T1	7		T7	6		T4	8
valid_sources[0x6d]	1742	1			T1	19		T7	4		T3	1
valid_sources[0x6e]	912	1			T1	6		T7	1		T2	1
valid_sources[0x6f]	865	1			T1	14		T7	1		T4	7
valid_sources[0x70]	1127	1			T1	9		T7	1		T2	2
valid_sources[0x71]	1329	1			T1	15		T7	1		T4	2
valid_sources[0x72]	1638	1			T1	13		T7	1		T2	1
valid_sources[0x73]	1348	1			T1	11		T3	1		T4	4
valid_sources[0x74]	1601	1			T1	16		T7	3		T2	2
valid_sources[0x75]	875	1			T1	17		T2	1		T3	1
valid_sources[0x76]	848	1			T1	11		T7	3		T4	5
valid_sources[0x77]	830	1			T1	10		T3	4		T4	3
valid_sources[0x78]	1413	1			T1	6		T4	5		T23	18
valid_sources[0x79]	912	1			T1	11		T4	4		T23	14
valid_sources[0x7a]	1040	1			T1	12		T7	2		T3	1
valid_sources[0x7b]	931	1			T1	20		T7	1		T2	2
valid_sources[0x7c]	952	1			T1	20		T7	1		T2	2
valid_sources[0x7d]	2055	1			T1	6		T7	3		T3	1
valid_sources[0x7e]	866	1			T1	15		T7	4		T2	1
valid_sources[0x7f]	890	1			T1	13		T7	3		T3	1
valid_sources[0x80]	896	1			T1	6		T2	1		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64912

1

T1

1417

T7

72

T2

11

values[0x0]

all_enables

biggest_size

30941

1

T1

23

T7

97

T2

10

values[0x1]

all_enables

biggest_size

21799

1

T1

12

T7

124

T2

8