4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 0 | 50 | 0.00 | ||
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 0 | 5 | 0.00 | ||
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 0 | 5 | 0.00 | ||
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 165 | 0.00 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 0 | 50 | 0.00 | ||
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 0 | 100 | 0.00 | ||
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 0 | 50 | 0.00 | ||
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 0 | 50 | 0.00 | ||
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 0 | 50 | 0.00 | ||
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 0 | 50 | 0.00 | ||
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 0 | 50 | 0.00 | ||
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 0 | 50 | 0.00 | ||
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 0 | 50 | 0.00 | ||
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 0 | 2 | 0.00 | ||
| V2 | stress_all | sysrst_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | sysrst_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | sysrst_ctrl_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 692 | 0.00 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| sysrst_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 932 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 0 | 0.00 |
| V2 | 15 | 15 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 934 failures:
0.sysrst_ctrl_smoke.76792288370846688269110488475828606785741631827728389235471956696190465752805
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest/run.log
1.sysrst_ctrl_smoke.40224196154881987884013826404007327167046440954127362617608215680330165127158
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest/run.log
... and 48 more failures.
0.sysrst_ctrl_in_out_inverted.57179111804166912018432181482846018861156283058332256559239468001850456858815
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest/run.log
1.sysrst_ctrl_in_out_inverted.17291632496872225110913360610598599645359320831672373791078456068601227816586
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest/run.log
... and 48 more failures.
0.sysrst_ctrl_combo_detect_ec_rst.54446035327595138279535678514214809544620303053174408438424818575362039976548
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest/run.log
1.sysrst_ctrl_combo_detect_ec_rst.44858740502888733204375877064107959393639749152360121187543788764391354749824
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest/run.log
... and 3 more failures.
0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.83659214828228495083356203368355319164982873323001957798769789093138539130628
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest/run.log
1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.100596267819905580894743907320434157825360431514780279408052341946459999744608
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest/run.log
... and 3 more failures.
0.sysrst_ctrl_pin_access_test.89876662499617372389945596233134846020122777011593751045083360214173900620720
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest/run.log
1.sysrst_ctrl_pin_access_test.94850533235308591067987263099092175973530506340121778092096900143058240601019
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.