SYSRST_CTRL Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: cf38c1d296

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.330s 2.108ms 49 50 98.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 8.470s 2.444ms 48 50 96.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.450s 2.181ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.380s 2.510ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 14.200s 6.055ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.150s 2.035ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 3.066m 39.471ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 9.380s 2.512ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.350s 2.087ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.150s 2.035ms 20 20 100.00
sysrst_ctrl_csr_aliasing 9.380s 2.512ms 5 5 100.00
V1 TOTAL 162 165 98.18
V2 combo_detect sysrst_ctrl_combo_detect 8.053m 188.508ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 9.605m 218.635ms 89 100 89.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 12.110m 281.670ms 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 4.682m 273.999ms 49 50 98.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.720s 2.515ms 49 50 98.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.620s 2.243ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 14.152m 1.292s 49 50 98.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.660s 2.612ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 4.024m 8.194s 46 50 92.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.423m 35.024ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 16.750m 421.448ms 48 50 96.00
V2 alert_test sysrst_ctrl_alert_test 6.200s 2.011ms 49 50 98.00
V2 intr_test sysrst_ctrl_intr_test 6.070s 2.010ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 7.250s 2.222ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 7.250s 2.222ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 14.200s 6.055ms 5 5 100.00
sysrst_ctrl_csr_rw 6.150s 2.035ms 20 20 100.00
sysrst_ctrl_csr_aliasing 9.380s 2.512ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 35.440s 10.396ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 14.200s 6.055ms 5 5 100.00
sysrst_ctrl_csr_rw 6.150s 2.035ms 20 20 100.00
sysrst_ctrl_csr_aliasing 9.380s 2.512ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 35.440s 10.396ms 20 20 100.00
V2 TOTAL 671 692 96.97
V2S tl_intg_err sysrst_ctrl_sec_cm 1.010m 22.014ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.850m 42.358ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.850m 42.358ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 6.052m 1.336s 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 905 932 97.10

Testplan Progress

Items Total Written Passing Progress
V1 9 9 7 77.78
V2 15 15 8 53.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.73 99.34 96.00 100.00 96.15 98.75 99.44 94.41

Failure Buckets

Past Results