Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.34	96.34	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	96.34	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.34	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	3	59	95.16

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	3	28	90.32	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2113

1

T16

12

T18

8

T20

25

auto[1]

702

1

T16

13

T18

4

T20

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2150

1

T16

20

T18

9

T20

32

auto[1]

665

1

T16

5

T18

3

T56

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2169

1

T16

13

T18

12

T20

31

auto[1]

646

1

T16

12

T20

1

T44

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2143

1

T16

25

T18

11

T20

28

auto[1]

672

1

T18

1

T20

4

T56

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2569

1

T16

25

T18

12

T20

31

auto[1]

246

1

T20

1

T44

4

T57

9

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2476

1

T16

25

T18

12

T20

24

auto[1]

339

1

T20

8

T60

2

T57

17

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2540

1

T16

25

T18

11

T20

28

auto[1]

275

1

T18

1

T20

4

T44

5

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2655

1

T16

25

T18

9

T20

32

auto[1]

160

1

T18

3

T60

2

T57

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2593

1

T16

25

T18

11

T20

28

auto[1]

222

1

T18

1

T20

4

T60

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2117

1

T16

7

T18

12

T20

32

auto[1]

698

1

T16

18

T56

12

T43

21

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	3	28	90.32	3
Automatically Generated Cross Bins	31	3	28	90.32	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	928	1			T16	25		T56	12		T43	29
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	85	1			T44	3		T342	3		T348	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	57	1			T78	11		T57	10		T196	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	3	1			T280	2		T361	1		-	-
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	33	1			T18	3		T104	7		T362	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	13	1			T104	4		T340	4		T363	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	16	1			T60	2		T255	2		T104	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T364	1		T363	5		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	87	1			T44	4		T255	1		T257	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	25	1			T44	1		T57	4		T58	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	36	1			T18	1		T20	2		T365	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T366	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	14	1			T237	2		T367	2		T368	7
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	8	1			T58	2		T281	3		T369	3
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	10	1			T99	6		T368	4		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T370	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	112	1			T20	2		T57	11		T256	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	36	1			T20	1		T278	10		T105	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	53	1			T95	2		T257	2		T278	9
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	3	1			T347	3		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	24	1			T135	2		T371	4		T362	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	7	1			T57	4		T341	1		T372	2
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T364	1		T373	4		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	27	1			T255	1		T280	2		T101	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	5	1			T281	1		T374	4		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T347	4		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T375	1		T355	2		T376	1
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T355	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

129

1

T20

2

T78

11

T191

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

112

1

T56

11

T43

9

T44

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

39

1

T16

8

T43

7

T192

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

123

1

T20

2

T255

2

T257

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

117

1

T18

1

T43

8

T284

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T44

2

T377

4

T342

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T257

2

T371

3

T378

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

139

1

T16

7

T20

1

T53

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

47

1

T278

9

T337

7

T364

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

92

1

T16

5

T44

3

T57

11

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T284

1

T104

7

T274

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T95

2

T336

10

T276

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T256

1

T70

5

T379

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

29

1

T260

1

T222

3

T345

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T176

2

T260

1

T380

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

121

1

T53

5

T193

7

T365

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

101

1

T18

3

T60

2

T45

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

74

1

T43

5

T53

4

T96

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T16

5

T93

2

T265

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T44

1

T58

5

T280

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T45

1

T275

4

T71

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T56

1

T72

4

T102

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T193

3

T377

1

T259

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

61

1

T53

2

T265

4

T70

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T93

1

T255

2

T102

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

24

1

T381

3

T104

4

T348

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T338

1

T71

3

T382

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

12

1

T193

2

T383

2

T378

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T102

2

T384

1

T183

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T192

1

T222

2

T385

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T337

1

T177

1

T386

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded