Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

984

1

T86

22

T42

14

T53

33

auto[1]

1021

1

T86

18

T42

6

T53

27

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

456

1

T86

12

T42

4

T53

16

from_0to1

459

1

T86

12

T42

5

T53

17

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T86

21

T42

12

T53

30

auto[1]

978

1

T86

19

T42

8

T53

30

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T86

18

T42

12

T53

29

auto[1]

989

1

T86

22

T42

8

T53

31

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T86

3

T42

1

T53

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T86

2

T42

1

T53

4

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T42

1

T53

2

T45

4

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T86

2

T53

1

T45

2

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T86

1

T42

1

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T86

1

T53

2

T45

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T42

1

T53

2

T121

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T86

2

T53

3

T121

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T86

1

T53

2

T121

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T86

2

T42

1

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T53

3

T403

1

T45

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T86

2

T53

1

T121

2

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T86

2

T53

3

T121

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T86

4

T42

1

T53

4

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T86

1

T42

2

T53

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T86

1

T121

2

T45

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T86

24

T42

12

T53

28

auto[1]

979

1

T86

16

T42

8

T53

32

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

470

1

T86

8

T42

5

T53

12

from_0to1

475

1

T86

8

T42

6

T53

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

965

1

T86

20

T42

16

T53

37

auto[1]

1040

1

T86

20

T42

4

T53

23

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T86

24

T42

7

T53

38

auto[1]

975

1

T86

16

T42

13

T53

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T86

1

T53

1

T121

2

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T86

1

T42

2

T53

2

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T86

1

T53

3

T121

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T86

1

T42

1

T45

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T86

1

T53

1

T121

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T86

2

T42

2

T53

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T86

3

T42

1

T121

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T53

1

T121

1

T403

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T86

2

T42

1

T53

3

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T86

1

T42

1

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T53

2

T45

2

T115

1

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T86

1

T403

1

T45

4

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T42

1

T53

1

T45

3

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T42

2

T53

2

T403

2

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T53

3

T121

1

T45

2

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T86

2

T53

1

T45

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T86

18

T42

12

T53

32

auto[1]

977

1

T86

22

T42

8

T53

28

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

471

1

T86

9

T42

6

T53

13

from_0to1

475

1

T86

9

T42

6

T53

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

993

1

T86

23

T42

10

T53

38

auto[1]

1012

1

T86

17

T42

10

T53

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

962

1

T86

15

T42

8

T53

30

auto[1]

1043

1

T86

25

T42

12

T53

30

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T86

1

T42

1

T403

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T86

2

T53

4

T45

2

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T86

1

T53

2

T121

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T86

1

T42

4

T53

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T86

2

T42

1

T53

4

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T86

1

T42

1

T53

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T86

1

T53

1

T45

4

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T86

1

T42

1

T53

3

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T86

2

T53

3

T45

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T86

2

T42

1

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T53

1

T45

1

T115

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T53

1

T121

1

T403

2

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T53

3

T121

1

T403

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T86

2

T42

1

T121

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T86

1

T42

2

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T86

1

T53

1

T115

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T86

16

T42

11

T53

30

auto[1]

973

1

T86

24

T42

9

T53

30

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

477

1

T86

9

T42

4

T53

17

from_0to1

480

1

T86

9

T42

4

T53

17

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

965

1

T86

17

T42

9

T53

26

auto[1]

1040

1

T86

23

T42

11

T53

34

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

997

1

T86

23

T42

5

T53

31

auto[1]

1008

1

T86

17

T42

15

T53

29

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T53

2

T45

4

T115

2

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T86

1

T53

3

T403

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T42

1

T53

5

T403

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T86

1

T45

4

T48

2

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T53

1

T121

1

T45

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T86

2

T42

3

T53

2

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T86

1

T53

2

T403

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T86

1

T53

3

T403

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T53

1

T121

1

T45

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T86

2

T53

3

T121

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T86

3

T42

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T86

2

T42

2

T53

2

auto[1]

from_0to1

auto[0]

auto[0]

43

1

T86

1

T53

1

T403

2

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T42

1

T53

1

T45

3

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T86

3

T53

3

T121

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T86

1

T53

4

T45

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T86

20

T42

9

T53

29

auto[1]

999

1

T86

20

T42

11

T53

31

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

483

1

T86

7

T42

4

T53

15

from_0to1

483

1

T86

7

T42

5

T53

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T86

18

T42

8

T53

33

auto[1]

1014

1

T86

22

T42

12

T53

27

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T86

18

T42

11

T53

43

auto[1]

989

1

T86

22

T42

9

T53

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T86

2

T45

2

T48

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T53

1

T121

1

T45

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T42

2

T53

4

T403

3

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T86

3

T53

2

T121

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T86

1

T53

4

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T53

1

T403

1

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T86

1

T42

1

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T86

1

T53

2

T121

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T53

4

T115

1

T48

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T42

1

T53

1

T45

3

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T86

1

T42

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T86

1

T53

2

T121

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T53

2

T403

2

T269

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T86

2

T42

2

T53

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T86

2

T53

2

T121

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T42

2

T53

2

T45

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T86

17

T42

9

T53

27

auto[1]

984

1

T86

23

T42

11

T53

33

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

492

1

T86

12

T42

5

T53

14

from_0to1

491

1

T86

12

T42

6

T53

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T86

24

T42

12

T53

39

auto[1]

989

1

T86

16

T42

8

T53

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1004

1

T86

20

T42

8

T53

29

auto[1]

1001

1

T86

20

T42

12

T53

31

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T42

3

T53

3

T403

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T86

1

T42

1

T53

4

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T86

2

T53

1

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T86

1

T42

1

T53

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T86

1

T42

1

T53

3

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T86

3

T53

1

T121

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T86

2

T42

1

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T121

2

T45

2

T115

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T86

1

T121

2

T45

3

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T86

4

T53

4

T45

4

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T86

2

T403

1

T45

2

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T86

1

T53

1

T403

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T86

3

T42

1

T53

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T86

1

T53

2

T45

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T86

2

T42

1

T53

2

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T42

2

T53

4

T45

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T86

17

T42

11

T53

28

auto[1]

1000

1

T86

23

T42

9

T53

32

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

478

1

T86

10

T42

6

T53

14

from_0to1

482

1

T86

10

T42

6

T53

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T86

16

T42

8

T53

29

auto[1]

1009

1

T86

24

T42

12

T53

31

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T86

23

T42

13

T53

30

auto[1]

1006

1

T86

17

T42

7

T53

30

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T86

2

T42

1

T53

2

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T86

2

T42

1

T403

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T86

2

T42

2

T121

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T86

1

T53

1

T121

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T42

1

T53

2

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T53

3

T121

2

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T86

3

T53

3

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T42

2

T53

2

T115

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T86

1

T42

1

T53

3

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T53

3

T121

1

T115

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T86

1

T53

3

T45

2

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T86

1

T42

1

T53

2

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T86

3

T42

1

T53

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T121

1

T403

2

T45

2

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T86

3

T42

2

T45

4

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T86

1

T53

3

T45

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T86

25

T42

13

T53

29

auto[1]

953

1

T86

15

T42

7

T53

31

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

488

1

T86

11

T42

4

T53

15

from_0to1

494

1

T86

11

T42

4

T53

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002

1

T86

25

T42

11

T53

31

auto[1]

1003

1

T86

15

T42

9

T53

29

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1011

1

T86

21

T42

9

T53

29

auto[1]

994

1

T86

19

T42

11

T53

31

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T86

2

T53

2

T121

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T86

2

T53

2

T121

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T86

3

T42

1

T53

2

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T86

2

T42

1

T53

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T86

1

T53

3

T121

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T86

3

T42

3

T53

3

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T86

1

T53

1

T121

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T86

1

T53

1

T403

2

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T86

1

T42

1

T53

3

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T86

1

T42

1

T53

3

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T53

1

T403

3

T45

2

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T53

1

T121

2

T45

2

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T86

3

T403

1

T45

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T86

1

T53

1

T121

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T86

1

T42

1

T53

3

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T53

3

T121

1

T115

1