Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152570	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120485

1

T6

7

T7

13

T8

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	139481	1			T6	11		T7	20		T8	20
values[0x0]	66343	1			T6	3		T7	10		T8	7
values[0x1]	67231	1			T6	7		T7	9		T8	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	123884	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149171

1

T6

8

T7

18

T8

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	917	1			T6	1		T2	1		T4	6
valid_sources[0x01]	1021	1			T8	1		T1	1		T2	1
valid_sources[0x02]	959	1			T4	6		T26	2		T27	3
valid_sources[0x03]	1204	1			T2	2		T4	2		T28	2
valid_sources[0x04]	901	1			T1	4		T4	2		T10	5
valid_sources[0x05]	1114	1			T7	1		T2	2		T4	3
valid_sources[0x06]	931	1			T2	2		T4	8		T28	1
valid_sources[0x07]	892	1			T2	4		T4	5		T10	7
valid_sources[0x08]	931	1			T4	5		T10	1		T11	5
valid_sources[0x09]	995	1			T7	1		T2	1		T4	5
valid_sources[0x0a]	887	1			T2	1		T10	3		T11	10
valid_sources[0x0b]	1209	1			T1	11		T2	3		T4	4
valid_sources[0x0c]	1054	1			T2	1		T4	4		T26	1
valid_sources[0x0d]	1303	1			T4	8		T28	2		T10	9
valid_sources[0x0e]	875	1			T2	1		T4	7		T28	2
valid_sources[0x0f]	991	1			T4	8		T10	13		T11	4
valid_sources[0x10]	773	1			T2	1		T4	6		T10	1
valid_sources[0x11]	835	1			T26	1		T11	2		T12	3
valid_sources[0x12]	906	1			T4	1		T24	1		T11	4
valid_sources[0x13]	994	1			T7	2		T1	21		T4	14
valid_sources[0x14]	1521	1			T6	1		T1	6		T2	1
valid_sources[0x15]	953	1			T4	1		T10	5		T11	4
valid_sources[0x16]	908	1			T1	5		T4	10		T28	3
valid_sources[0x17]	824	1			T2	1		T4	6		T10	3
valid_sources[0x18]	958	1			T6	1		T7	1		T4	8
valid_sources[0x19]	931	1			T2	1		T4	16		T10	7
valid_sources[0x1a]	972	1			T1	24		T4	4		T10	12
valid_sources[0x1b]	1219	1			T4	8		T24	3		T10	6
valid_sources[0x1c]	1800	1			T4	5		T10	2		T11	14
valid_sources[0x1d]	823	1			T1	3		T2	1		T4	8
valid_sources[0x1e]	1181	1			T7	1		T1	2		T4	10
valid_sources[0x1f]	984	1			T8	1		T1	7		T2	1
valid_sources[0x20]	1008	1			T2	1		T4	3		T10	2
valid_sources[0x21]	1336	1			T1	14		T2	1		T4	3
valid_sources[0x22]	949	1			T8	1		T2	3		T4	3
valid_sources[0x23]	785	1			T7	1		T8	3		T2	1
valid_sources[0x24]	875	1			T1	22		T4	2		T28	1
valid_sources[0x25]	1512	1			T4	11		T10	5		T11	1
valid_sources[0x26]	899	1			T2	1		T4	3		T10	8
valid_sources[0x27]	911	1			T4	14		T10	7		T11	4
valid_sources[0x28]	1766	1			T1	13		T2	3		T10	2
valid_sources[0x29]	994	1			T1	12		T2	1		T4	8
valid_sources[0x2a]	1206	1			T2	2		T4	2		T26	1
valid_sources[0x2b]	967	1			T4	8		T10	6		T12	8
valid_sources[0x2c]	1115	1			T8	2		T4	8		T10	5
valid_sources[0x2d]	824	1			T7	1		T2	1		T4	11
valid_sources[0x2e]	993	1			T2	1		T4	6		T10	2
valid_sources[0x2f]	1430	1			T4	3		T24	12		T10	5
valid_sources[0x30]	2323	1			T2	1		T4	3		T10	9
valid_sources[0x31]	860	1			T4	4		T11	2		T12	5
valid_sources[0x32]	888	1			T4	17		T10	1		T11	8
valid_sources[0x33]	940	1			T4	4		T10	1		T11	3
valid_sources[0x34]	815	1			T6	1		T4	6		T10	1
valid_sources[0x35]	1119	1			T1	2		T2	1		T4	5
valid_sources[0x36]	885	1			T7	1		T2	4		T4	3
valid_sources[0x37]	812	1			T8	1		T1	9		T2	2
valid_sources[0x38]	967	1			T7	1		T4	6		T10	1
valid_sources[0x39]	1171	1			T2	3		T4	1		T11	2
valid_sources[0x3a]	897	1			T10	4		T11	7		T12	3
valid_sources[0x3b]	1843	1			T2	1		T4	12		T10	12
valid_sources[0x3c]	939	1			T4	17		T10	2		T11	3
valid_sources[0x3d]	1846	1			T2	1		T4	1		T10	6
valid_sources[0x3e]	951	1			T8	2		T2	1		T10	10
valid_sources[0x3f]	841	1			T2	2		T4	1		T10	9
valid_sources[0x40]	997	1			T1	33		T4	9		T11	3
valid_sources[0x41]	1006	1			T1	29		T4	7		T10	8
valid_sources[0x42]	1157	1			T8	2		T4	13		T10	22
valid_sources[0x43]	1487	1			T4	5		T24	23		T10	4
valid_sources[0x44]	837	1			T8	1		T2	2		T3	20
valid_sources[0x45]	1332	1			T8	1		T2	2		T4	14
valid_sources[0x46]	938	1			T6	1		T8	1		T4	8
valid_sources[0x47]	857	1			T2	1		T4	2		T10	3
valid_sources[0x48]	811	1			T1	10		T2	1		T4	13
valid_sources[0x49]	769	1			T4	2		T10	4		T11	10
valid_sources[0x4a]	1007	1			T7	1		T1	10		T4	6
valid_sources[0x4b]	833	1			T1	2		T2	1		T4	4
valid_sources[0x4c]	898	1			T7	1		T4	15		T10	5
valid_sources[0x4d]	1852	1			T6	2		T8	2		T2	1
valid_sources[0x4e]	977	1			T7	1		T4	1		T28	1
valid_sources[0x4f]	1122	1			T4	6		T26	1		T10	4
valid_sources[0x50]	1117	1			T4	9		T10	17		T11	6
valid_sources[0x51]	1966	1			T1	9		T4	6		T27	2
valid_sources[0x52]	1634	1			T2	1		T4	7		T11	2
valid_sources[0x53]	971	1			T1	20		T4	3		T10	1
valid_sources[0x54]	797	1			T2	1		T4	2		T10	4
valid_sources[0x55]	2095	1			T4	1		T10	4		T11	5
valid_sources[0x56]	1177	1			T6	1		T2	1		T4	24
valid_sources[0x57]	1106	1			T7	1		T2	1		T4	10
valid_sources[0x58]	1281	1			T1	14		T4	8		T10	3
valid_sources[0x59]	771	1			T2	1		T4	10		T10	7
valid_sources[0x5a]	1324	1			T2	2		T4	3		T28	2
valid_sources[0x5b]	1010	1			T2	1		T4	13		T10	4
valid_sources[0x5c]	886	1			T2	3		T4	6		T10	5
valid_sources[0x5d]	763	1			T1	7		T2	6		T4	6
valid_sources[0x5e]	1254	1			T1	10		T2	7		T3	20
valid_sources[0x5f]	1473	1			T4	3		T10	5		T11	1
valid_sources[0x60]	1214	1			T6	1		T7	1		T4	5
valid_sources[0x61]	868	1			T8	1		T1	3		T4	2
valid_sources[0x62]	978	1			T2	1		T4	2		T11	2
valid_sources[0x63]	1012	1			T4	7		T10	7		T11	7
valid_sources[0x64]	835	1			T2	1		T4	6		T10	1
valid_sources[0x65]	1033	1			T6	2		T2	1		T4	1
valid_sources[0x66]	1013	1			T2	1		T4	4		T26	1
valid_sources[0x67]	870	1			T7	1		T8	1		T1	1
valid_sources[0x68]	836	1			T1	3		T4	8		T10	19
valid_sources[0x69]	1034	1			T4	4		T10	3		T11	3
valid_sources[0x6a]	1042	1			T6	1		T2	2		T4	5
valid_sources[0x6b]	880	1			T7	1		T2	1		T4	11
valid_sources[0x6c]	985	1			T4	6		T10	2		T11	10
valid_sources[0x6d]	846	1			T6	1		T8	1		T2	1
valid_sources[0x6e]	855	1			T2	3		T4	2		T10	6
valid_sources[0x6f]	1591	1			T1	2		T4	1		T10	9
valid_sources[0x70]	889	1			T2	4		T4	4		T10	2
valid_sources[0x71]	836	1			T2	3		T4	1		T10	18
valid_sources[0x72]	1000	1			T2	2		T4	3		T10	1
valid_sources[0x73]	862	1			T10	7		T11	8		T12	4
valid_sources[0x74]	946	1			T1	8		T4	7		T28	4
valid_sources[0x75]	1033	1			T7	1		T8	1		T2	5
valid_sources[0x76]	1222	1			T1	15		T2	2		T4	2
valid_sources[0x77]	891	1			T1	3		T2	1		T4	3
valid_sources[0x78]	833	1			T4	3		T28	2		T10	2
valid_sources[0x79]	936	1			T4	6		T10	16		T11	5
valid_sources[0x7a]	1121	1			T4	7		T26	1		T11	3
valid_sources[0x7b]	1110	1			T4	17		T10	1		T11	5
valid_sources[0x7c]	896	1			T4	2		T11	1		T12	7
valid_sources[0x7d]	831	1			T7	1		T4	3		T10	10
valid_sources[0x7e]	957	1			T1	4		T4	6		T11	1
valid_sources[0x7f]	843	1			T2	1		T4	3		T10	11
valid_sources[0x80]	2048	1			T2	1		T11	4		T291	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64620

1

T6

5

T7

10

T8

5

values[0x0]

all_enables

biggest_size

32542

1

T6

1

T8

1

T1

204

values[0x1]

all_enables

biggest_size

23323

1

T6

1

T7

3

T8

1