Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T31,T62,T86

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T31,T62,T86

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T62,T86,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T62,T86
1	0	Covered	T39,T40,T41
1	1	Covered	T31,T62,T86

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T62,T86,T42
0	1	Covered	T110
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T62,T86,T42
0	1	Covered	T62,T86,T42
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T62,T86,T42
1	-	Covered	T62,T86,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T62,T86
0	1	Covered	T31,T62,T86
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T86,T42
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T62,T86
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T62,T86,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T45,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T62,T86
DetectSt	-	-	-	-	1	-	-	Covered	T110
DetectSt	-	-	-	-	0	1	-	Covered	T62,T86,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T62,T86,T42
StableSt	-	-	-	-	-	-	0	Covered	T62,T86,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	295	0	0
CntIncr_A	7802265	146823	0	0
CntNoWrap_A	7802265	7134609	0	0
DetectStDropOut_A	7802265	1	0	0
DetectedOut_A	7802265	955	0	0
DetectedPulseOut_A	7802265	135	0	0
DisabledIdleSt_A	7802265	6981153	0	0
DisabledNoDetection_A	7802265	6983545	0	0
EnterDebounceSt_A	7802265	166	0	0
EnterDetectSt_A	7802265	136	0	0
EnterStableSt_A	7802265	135	0	0
PulseIsPulse_A	7802265	135	0	0
StayInStableSt	7802265	820	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802265	6941	0	0
gen_low_level_sva.LowLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	134	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	295	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T31	670	2	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	4	0	0
T45	0	7	0	0
T48	0	1	0	0
T62	736	4	0	0
T63	522	0	0	0
T66	0	4	0	0
T86	0	4	0	0
T87	0	4	0	0
T88	0	2	0	0
T89	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	146823	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T31	670	102	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	55	0	0
T45	0	200	0	0
T48	0	83	0	0
T62	736	174	0	0
T63	522	0	0	0
T66	0	651	0	0
T86	0	37	0	0
T87	0	3907	0	0
T88	0	35	0	0
T89	0	144	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134609	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	267	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1	0	0
T110	663	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	955	0	0
T19	668	0	0	0
T20	10025	0	0	0
T42	138002	22	0	0
T43	32546	0	0	0
T45	0	10	0	0
T54	0	35	0	0
T55	470	0	0	0
T62	736	11	0	0
T63	522	0	0	0
T66	0	17	0	0
T86	15713	4	0	0
T87	0	9	0	0
T88	0	9	0	0
T89	0	13	0	0
T90	615	0	0	0
T111	434	0	0	0
T120	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	135	0	0
T19	668	0	0	0
T20	10025	0	0	0
T42	138002	2	0	0
T43	32546	0	0	0
T45	0	2	0	0
T54	0	4	0	0
T55	470	0	0	0
T62	736	2	0	0
T63	522	0	0	0
T66	0	2	0	0
T86	15713	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	615	0	0	0
T111	434	0	0	0
T120	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6981153	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	81	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6983545	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	81	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	166	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T31	670	2	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T45	0	5	0	0
T48	0	1	0	0
T62	736	2	0	0
T63	522	0	0	0
T66	0	3	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	136	0	0
T19	668	0	0	0
T20	10025	0	0	0
T42	138002	2	0	0
T43	32546	0	0	0
T45	0	2	0	0
T54	0	4	0	0
T55	470	0	0	0
T62	736	2	0	0
T63	522	0	0	0
T66	0	2	0	0
T86	15713	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	615	0	0	0
T111	434	0	0	0
T120	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	135	0	0
T19	668	0	0	0
T20	10025	0	0	0
T42	138002	2	0	0
T43	32546	0	0	0
T45	0	2	0	0
T54	0	4	0	0
T55	470	0	0	0
T62	736	2	0	0
T63	522	0	0	0
T66	0	2	0	0
T86	15713	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	615	0	0	0
T111	434	0	0	0
T120	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	135	0	0
T19	668	0	0	0
T20	10025	0	0	0
T42	138002	2	0	0
T43	32546	0	0	0
T45	0	2	0	0
T54	0	4	0	0
T55	470	0	0	0
T62	736	2	0	0
T63	522	0	0	0
T66	0	2	0	0
T86	15713	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	615	0	0	0
T111	434	0	0	0
T120	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	820	0	0
T19	668	0	0	0
T20	10025	0	0	0
T42	138002	20	0	0
T43	32546	0	0	0
T45	0	8	0	0
T54	0	31	0	0
T55	470	0	0	0
T62	736	9	0	0
T63	522	0	0	0
T66	0	15	0	0
T86	15713	2	0	0
T87	0	7	0	0
T88	0	8	0	0
T89	0	11	0	0
T90	615	0	0	0
T111	434	0	0	0
T120	0	4	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6941	0	0
T14	1083	2	0	0
T15	686	2	0	0
T16	29480	17	0	0
T29	490	8	0	0
T30	2238	15	0	0
T31	670	3	0	0
T32	407	0	0	0
T33	0	3	0	0
T39	423	3	0	0
T40	522	5	0	0
T41	423	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	134	0	0
T19	668	0	0	0
T20	10025	0	0	0
T42	138002	2	0	0
T43	32546	0	0	0
T45	0	2	0	0
T54	0	4	0	0
T55	470	0	0	0
T62	736	2	0	0
T63	522	0	0	0
T66	0	2	0	0
T86	15713	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	615	0	0	0
T111	434	0	0	0
T120	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T15,T17,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T15,T17,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T15,T42,T65

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T22
1	0	Covered	T39,T40,T41
1	1	Covered	T15,T17,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T65,T80
0	1	Covered	T42,T65,T68
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T65,T80
0	1	Unreachable
1	0	Covered	T15,T65,T80

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T17,T22
0	1	Covered	T15,T17,T22
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T42,T65
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T17,T22
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T42,T65
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T22,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T17,T22
DetectSt	-	-	-	-	1	-	-	Covered	T42,T65,T68
DetectSt	-	-	-	-	0	1	-	Covered	T15,T65,T80
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T65,T80
StableSt	-	-	-	-	-	-	0	Covered	T15,T65,T80
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	184	0	0
CntIncr_A	7802265	13314	0	0
CntNoWrap_A	7802265	7134720	0	0
DetectStDropOut_A	7802265	22	0	0
DetectedOut_A	7802265	39276	0	0
DetectedPulseOut_A	7802265	48	0	0
DisabledIdleSt_A	7802265	6373884	0	0
DisabledNoDetection_A	7802265	6376331	0	0
EnterDebounceSt_A	7802265	115	0	0
EnterDetectSt_A	7802265	70	0	0
EnterStableSt_A	7802265	48	0	0
PulseIsPulse_A	7802265	48	0	0
StayInStableSt	7802265	39228	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802265	6941	0	0
gen_low_level_sva.LowLevelEvent_A	7802265	7137351	0	0
gen_sticky_sva.StableStDropOut_A	7802265	42935	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	184	0	0
T15	686	2	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T22	0	3	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T55	470	0	0	0
T61	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	4	0	0
T65	0	6	0	0
T66	0	5	0	0
T67	0	3	0	0
T68	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	13314	0	0
T15	686	34	0	0
T16	29480	0	0	0
T17	1479	49	0	0
T18	9276	0	0	0
T22	0	285	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	33	0	0
T55	470	0	0	0
T61	0	168	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	256	0	0
T65	0	66	0	0
T66	0	155	0	0
T67	0	210	0	0
T68	0	205	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134720	0	0
T14	1083	682	0	0
T15	686	283	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	22	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T53	47415	0	0	0
T60	15751	0	0	0
T65	0	2	0	0
T68	0	3	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T126	0	5	0	0
T127	0	5	0	0
T128	0	2	0	0
T129	0	3	0	0
T130	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	39276	0	0
T15	686	54	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T55	470	0	0	0
T62	736	0	0	0
T63	522	0	0	0
T65	0	49	0	0
T80	0	190	0	0
T81	0	159	0	0
T82	0	151	0	0
T84	0	18	0	0
T122	0	76	0	0
T123	0	176	0	0
T124	0	477	0	0
T125	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	48	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T55	470	0	0	0
T62	736	0	0	0
T63	522	0	0	0
T65	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T84	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6373884	0	0
T14	1083	682	0	0
T15	686	50	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6376331	0	0
T14	1083	683	0	0
T15	686	51	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	115	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T22	0	3	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	4	0	0
T65	0	3	0	0
T66	0	5	0	0
T67	0	3	0	0
T68	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	70	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T62	736	0	0	0
T63	522	0	0	0
T65	0	3	0	0
T68	0	3	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	48	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T55	470	0	0	0
T62	736	0	0	0
T63	522	0	0	0
T65	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T84	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	48	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T55	470	0	0	0
T62	736	0	0	0
T63	522	0	0	0
T65	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T84	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	39228	0	0
T15	686	53	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T55	470	0	0	0
T62	736	0	0	0
T63	522	0	0	0
T65	0	48	0	0
T80	0	189	0	0
T81	0	158	0	0
T82	0	149	0	0
T84	0	17	0	0
T122	0	75	0	0
T123	0	175	0	0
T124	0	476	0	0
T125	0	50	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6941	0	0
T14	1083	2	0	0
T15	686	2	0	0
T16	29480	17	0	0
T29	490	8	0	0
T30	2238	15	0	0
T31	670	3	0	0
T32	407	0	0	0
T33	0	3	0	0
T39	423	3	0	0
T40	522	5	0	0
T41	423	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	42935	0	0
T15	686	134	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T55	470	0	0	0
T62	736	0	0	0
T63	522	0	0	0
T65	0	266	0	0
T80	0	119	0	0
T81	0	55	0	0
T82	0	178	0	0
T84	0	72	0	0
T122	0	62	0	0
T123	0	43	0	0
T124	0	84	0	0
T125	0	29	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T15,T17,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T15,T17,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T15,T17,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T22
1	0	Covered	T39,T40,T41
1	1	Covered	T15,T17,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T17,T42
0	1	Covered	T82,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T17,T42
0	1	Unreachable
1	0	Covered	T15,T17,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T17,T22
0	1	Covered	T15,T17,T22
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T17,T42
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T17,T22
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T17,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T68,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T17,T22
DetectSt	-	-	-	-	1	-	-	Covered	T82,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T15,T17,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T17,T42
StableSt	-	-	-	-	-	-	0	Covered	T15,T17,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	175	0	0
CntIncr_A	7802265	37662	0	0
CntNoWrap_A	7802265	7134729	0	0
DetectStDropOut_A	7802265	13	0	0
DetectedOut_A	7802265	52666	0	0
DetectedPulseOut_A	7802265	47	0	0
DisabledIdleSt_A	7802265	6373884	0	0
DisabledNoDetection_A	7802265	6376331	0	0
EnterDebounceSt_A	7802265	116	0	0
EnterDetectSt_A	7802265	60	0	0
EnterStableSt_A	7802265	47	0	0
PulseIsPulse_A	7802265	47	0	0
StayInStableSt	7802265	52619	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_sticky_sva.StableStDropOut_A	7802265	628292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	175	0	0
T15	686	2	0	0
T16	29480	0	0	0
T17	1479	2	0	0
T18	9276	0	0	0
T22	0	3	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T55	470	0	0	0
T61	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	4	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	37662	0	0
T15	686	49	0	0
T16	29480	0	0	0
T17	1479	19	0	0
T18	9276	0	0	0
T22	0	252	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	65	0	0
T55	470	0	0	0
T61	0	10	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	32	0	0
T65	0	45	0	0
T66	0	4025	0	0
T67	0	84	0	0
T68	0	195	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134729	0	0
T14	1083	682	0	0
T15	686	283	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	13	0	0
T82	920	1	0	0
T83	1090	1	0	0
T84	0	1	0	0
T108	0	3	0	0
T123	8812	0	0	0
T126	0	3	0	0
T131	0	3	0	0
T132	0	1	0	0
T133	518	0	0	0
T134	424	0	0	0
T135	18192	0	0	0
T136	48945	0	0	0
T137	502	0	0	0
T138	497	0	0	0
T139	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	52666	0	0
T15	686	134	0	0
T16	29480	0	0	0
T17	1479	5	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	11	0	0
T55	470	0	0	0
T61	0	24	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	70	0	0
T65	0	306	0	0
T66	0	35829	0	0
T67	0	275	0	0
T81	0	164	0	0
T122	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	47	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	1	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T81	0	1	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6373884	0	0
T14	1083	682	0	0
T15	686	50	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6376331	0	0
T14	1083	683	0	0
T15	686	51	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	116	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T22	0	3	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	1	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	60	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	1	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	47	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	1	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T81	0	1	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	47	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	1	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T81	0	1	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	52619	0	0
T15	686	133	0	0
T16	29480	0	0	0
T17	1479	4	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	10	0	0
T55	470	0	0	0
T61	0	23	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	68	0	0
T65	0	305	0	0
T66	0	35828	0	0
T67	0	274	0	0
T81	0	163	0	0
T122	0	53	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	628292	0	0
T15	686	44	0	0
T16	29480	0	0	0
T17	1479	104	0	0
T18	9276	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	28	0	0
T55	470	0	0	0
T61	0	78400	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	243	0	0
T65	0	200	0	0
T66	0	283781	0	0
T67	0	226	0	0
T81	0	169	0	0
T122	0	92	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T15,T17,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T15,T17,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T15,T17,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T22
1	0	Covered	T39,T40,T41
1	1	Covered	T15,T17,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T17,T22
0	1	Covered	T61,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T17,T22
0	1	Unreachable
1	0	Covered	T15,T17,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T17,T22
0	1	Covered	T15,T17,T22
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T17,T22
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T17,T22
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T17,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T65,T80,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T17,T22
DetectSt	-	-	-	-	1	-	-	Covered	T61,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T15,T17,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T17,T22
StableSt	-	-	-	-	-	-	0	Covered	T15,T17,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	173	0	0
CntIncr_A	7802265	162403	0	0
CntNoWrap_A	7802265	7134731	0	0
DetectStDropOut_A	7802265	10	0	0
DetectedOut_A	7802265	511298	0	0
DetectedPulseOut_A	7802265	50	0	0
DisabledIdleSt_A	7802265	6373884	0	0
DisabledNoDetection_A	7802265	6376331	0	0
EnterDebounceSt_A	7802265	114	0	0
EnterDetectSt_A	7802265	60	0	0
EnterStableSt_A	7802265	50	0	0
PulseIsPulse_A	7802265	50	0	0
StayInStableSt	7802265	511248	0	0
gen_high_event_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_sticky_sva.StableStDropOut_A	7802265	81908	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	173	0	0
T15	686	2	0	0
T16	29480	0	0	0
T17	1479	2	0	0
T18	9276	0	0	0
T22	0	2	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T55	470	0	0	0
T61	0	4	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	4	0	0
T65	0	5	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	162403	0	0
T15	686	14	0	0
T16	29480	0	0	0
T17	1479	85	0	0
T18	9276	0	0	0
T22	0	59	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	33	0	0
T55	470	0	0	0
T61	0	78290	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	34	0	0
T65	0	395	0	0
T66	0	38746	0	0
T67	0	42	0	0
T68	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134731	0	0
T14	1083	682	0	0
T15	686	283	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	10	0	0
T57	37129	0	0	0
T61	196514	1	0	0
T80	1171	1	0	0
T81	0	2	0	0
T125	0	1	0	0
T141	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	32228	0	0	0
T146	4415	0	0	0
T147	655	0	0	0
T148	492	0	0	0
T149	492	0	0	0
T150	502	0	0	0
T151	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	511298	0	0
T15	686	38	0	0
T16	29480	0	0	0
T17	1479	13	0	0
T18	9276	0	0	0
T22	0	217	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	15	0	0
T55	470	0	0	0
T61	0	1	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	72	0	0
T66	0	284836	0	0
T67	0	139	0	0
T68	0	410	0	0
T82	0	229	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	50	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T22	0	1	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	1	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T82	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6373884	0	0
T14	1083	682	0	0
T15	686	50	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6376331	0	0
T14	1083	683	0	0
T15	686	51	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	114	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T22	0	1	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T65	0	5	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	60	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T22	0	1	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T80	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	50	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T22	0	1	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	1	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T82	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	50	0	0
T15	686	1	0	0
T16	29480	0	0	0
T17	1479	1	0	0
T18	9276	0	0	0
T22	0	1	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T55	470	0	0	0
T61	0	1	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T82	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	511248	0	0
T15	686	37	0	0
T16	29480	0	0	0
T17	1479	12	0	0
T18	9276	0	0	0
T22	0	216	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	14	0	0
T55	470	0	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	70	0	0
T66	0	284835	0	0
T67	0	138	0	0
T68	0	409	0	0
T81	0	85	0	0
T82	0	227	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	81908	0	0
T15	686	176	0	0
T16	29480	0	0	0
T17	1479	48	0	0
T18	9276	0	0	0
T22	0	172	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	63	0	0
T55	470	0	0	0
T61	0	83	0	0
T62	736	0	0	0
T63	522	0	0	0
T64	0	258	0	0
T66	0	72	0	0
T67	0	416	0	0
T68	0	154	0	0
T82	0	76	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T45,T46,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T45,T46,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T45,T46,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T45,T48,T51
1	0	Covered	T39,T40,T41
1	1	Covered	T45,T46,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T54
0	1	Covered	T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T54
0	1	Covered	T46,T54,T153
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T54
1	-	Covered	T46,T54,T153

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T46,T54
0	1	Covered	T45,T46,T54
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T46,T54
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T46,T54
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T46,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T154
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T46,T54
DetectSt	-	-	-	-	1	-	-	Covered	T152
DetectSt	-	-	-	-	0	1	-	Covered	T45,T46,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T54,T153
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	72	0	0
CntIncr_A	7802265	62259	0	0
CntNoWrap_A	7802265	7134832	0	0
DetectStDropOut_A	7802265	1	0	0
DetectedOut_A	7802265	2089	0	0
DetectedPulseOut_A	7802265	34	0	0
DisabledIdleSt_A	7802265	6832265	0	0
DisabledNoDetection_A	7802265	6834665	0	0
EnterDebounceSt_A	7802265	38	0	0
EnterDetectSt_A	7802265	35	0	0
EnterStableSt_A	7802265	34	0	0
PulseIsPulse_A	7802265	34	0	0
StayInStableSt	7802265	2038	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	72	0	0
T45	13894	2	0	0
T46	0	4	0	0
T48	7038	0	0	0
T54	0	2	0	0
T77	0	6	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	4	0	0
T153	0	4	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	4	0	0
T158	0	4	0	0
T159	671	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	62259	0	0
T45	13894	33	0	0
T46	0	166	0	0
T48	7038	0	0	0
T54	0	50	0	0
T77	0	108	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	162	0	0
T153	0	106	0	0
T155	0	14	0	0
T156	0	93	0	0
T157	0	162	0	0
T159	671	0	0	0
T160	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134832	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1	0	0
T152	1080	1	0	0
T161	408	0	0	0
T162	751	0	0	0
T163	429	0	0	0
T164	51503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	2089	0	0
T45	13894	42	0	0
T46	0	67	0	0
T48	7038	0	0	0
T54	0	40	0	0
T77	0	129	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	43	0	0
T153	0	264	0	0
T155	0	48	0	0
T156	0	42	0	0
T157	0	42	0	0
T158	0	86	0	0
T159	671	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34	0	0
T45	13894	1	0	0
T46	0	2	0	0
T48	7038	0	0	0
T54	0	1	0	0
T77	0	3	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	671	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6832265	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6834665	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	38	0	0
T45	13894	1	0	0
T46	0	2	0	0
T48	7038	0	0	0
T54	0	1	0	0
T77	0	3	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	2	0	0
T153	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T159	671	0	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	35	0	0
T45	13894	1	0	0
T46	0	2	0	0
T48	7038	0	0	0
T54	0	1	0	0
T77	0	3	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	2	0	0
T153	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	671	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34	0	0
T45	13894	1	0	0
T46	0	2	0	0
T48	7038	0	0	0
T54	0	1	0	0
T77	0	3	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	671	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34	0	0
T45	13894	1	0	0
T46	0	2	0	0
T48	7038	0	0	0
T54	0	1	0	0
T77	0	3	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	671	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	2038	0	0
T45	13894	40	0	0
T46	0	64	0	0
T48	7038	0	0	0
T54	0	39	0	0
T77	0	125	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	41	0	0
T153	0	261	0	0
T155	0	46	0	0
T156	0	40	0	0
T157	0	39	0	0
T158	0	83	0	0
T159	671	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	16	0	0
T46	2680	1	0	0
T47	761	0	0	0
T54	0	1	0	0
T58	18739	0	0	0
T64	1247	0	0	0
T65	1115	0	0	0
T77	0	2	0	0
T89	739	0	0	0
T93	9431	0	0	0
T126	0	1	0	0
T153	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	423	0	0	0
T169	490	0	0	0
T170	524	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T19,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T14,T19,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T19,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T19,T53
1	0	Covered	T39,T40,T41
1	1	Covered	T14,T19,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T48
0	1	Covered	T53,T171,T172
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T48
0	1	Covered	T14,T19,T46
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T19,T48
1	-	Covered	T14,T19,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T19,T53
0	1	Covered	T14,T19,T53
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T19,T53
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T19,T53
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T19,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T173
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T19,T53
DetectSt	-	-	-	-	1	-	-	Covered	T53,T171,T172
DetectSt	-	-	-	-	0	1	-	Covered	T14,T19,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T19,T46
StableSt	-	-	-	-	-	-	0	Covered	T14,T19,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	130	0	0
CntIncr_A	7802265	86247	0	0
CntNoWrap_A	7802265	7134774	0	0
DetectStDropOut_A	7802265	4	0	0
DetectedOut_A	7802265	93928	0	0
DetectedPulseOut_A	7802265	60	0	0
DisabledIdleSt_A	7802265	6836434	0	0
DisabledNoDetection_A	7802265	6838827	0	0
EnterDebounceSt_A	7802265	66	0	0
EnterDetectSt_A	7802265	64	0	0
EnterStableSt_A	7802265	60	0	0
PulseIsPulse_A	7802265	60	0	0
StayInStableSt	7802265	93840	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802265	2580	0	0
gen_low_level_sva.LowLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	130	0	0
T14	1083	4	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	2	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	4	0	0
T47	0	2	0	0
T48	0	4	0	0
T49	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	6	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	86247	0	0
T14	1083	184	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	22	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	166	0	0
T47	0	71	0	0
T48	0	192	0	0
T49	0	14	0	0
T52	0	20	0	0
T53	0	83	0	0
T54	0	180	0	0
T76	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134774	0	0
T14	1083	678	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	4	0	0
T53	47415	1	0	0
T121	505	0	0	0
T171	674	1	0	0
T172	12656	1	0	0
T174	0	1	0	0
T175	426	0	0	0
T176	18497	0	0	0
T177	19172	0	0	0
T178	606	0	0	0
T179	545	0	0	0
T180	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	93928	0	0
T14	1083	177	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	157	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	216	0	0
T47	0	96	0	0
T48	0	79	0	0
T49	0	43	0	0
T52	0	38	0	0
T54	0	639	0	0
T76	0	241	0	0
T155	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	60	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	3	0	0
T76	0	1	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6836434	0	0
T14	1083	3	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6838827	0	0
T14	1083	3	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	66	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	3	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	64	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	3	0	0
T76	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	60	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	3	0	0
T76	0	1	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	60	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	3	0	0
T76	0	1	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	93840	0	0
T14	1083	174	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	156	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	214	0	0
T47	0	95	0	0
T48	0	75	0	0
T49	0	41	0	0
T52	0	36	0	0
T54	0	634	0	0
T76	0	240	0	0
T155	0	11	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	2580	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	6	0	0
T17	0	5	0	0
T29	490	6	0	0
T30	2238	9	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	0	5	0	0
T39	423	4	0	0
T40	522	7	0	0
T41	423	4	0	0
T63	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	31	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T76	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T160	0	1	0	0