Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T42,T48,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T42,T48,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T42,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T21,T42
1	0	Covered	T39,T40,T41
1	1	Covered	T42,T48,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T46,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T46,T47
0	1	Covered	T46,T76,T77
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T46,T47
1	-	Covered	T46,T76,T77

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T48,T46
0	1	Covered	T42,T48,T46
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T46,T47
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T48,T46
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T48
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T48,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T42,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T76,T77
StableSt	-	-	-	-	-	-	0	Covered	T42,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	74	0	0
CntIncr_A	7802265	59880	0	0
CntNoWrap_A	7802265	7134830	0	0
DetectStDropOut_A	7802265	0	0	0
DetectedOut_A	7802265	64383	0	0
DetectedPulseOut_A	7802265	36	0	0
DisabledIdleSt_A	7802265	6650188	0	0
DisabledNoDetection_A	7802265	6652581	0	0
EnterDebounceSt_A	7802265	38	0	0
EnterDetectSt_A	7802265	36	0	0
EnterStableSt_A	7802265	36	0	0
PulseIsPulse_A	7802265	36	0	0
StayInStableSt	7802265	64327	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	74	0	0
T42	138002	2	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T53	47415	0	0	0
T54	0	2	0	0
T60	15751	0	0	0
T76	0	4	0	0
T77	0	6	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T157	0	2	0	0
T181	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	59880	0	0
T42	138002	53	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T46	0	83	0	0
T47	0	71	0	0
T48	0	93	0	0
T53	47415	0	0	0
T54	0	80	0	0
T60	15751	0	0	0
T76	0	96	0	0
T77	0	81	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T157	0	81	0	0
T181	0	14	0	0
T182	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134830	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	64383	0	0
T42	138002	37	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T46	0	40	0	0
T47	0	112	0	0
T53	47415	0	0	0
T54	0	40	0	0
T60	15751	0	0	0
T76	0	86	0	0
T77	0	197	0	0
T81	0	43	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T157	0	1	0	0
T181	0	42	0	0
T182	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	36	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	47415	0	0	0
T54	0	1	0	0
T60	15751	0	0	0
T76	0	2	0	0
T77	0	3	0	0
T81	0	1	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T157	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6650188	0	0
T14	1083	3	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6652581	0	0
T14	1083	3	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	38	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T53	47415	0	0	0
T54	0	1	0	0
T60	15751	0	0	0
T76	0	2	0	0
T77	0	3	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T157	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	36	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	47415	0	0	0
T54	0	1	0	0
T60	15751	0	0	0
T76	0	2	0	0
T77	0	3	0	0
T81	0	1	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T157	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	36	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	47415	0	0	0
T54	0	1	0	0
T60	15751	0	0	0
T76	0	2	0	0
T77	0	3	0	0
T81	0	1	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T157	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	36	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	47415	0	0	0
T54	0	1	0	0
T60	15751	0	0	0
T76	0	2	0	0
T77	0	3	0	0
T81	0	1	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T157	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	64327	0	0
T42	138002	35	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T46	0	39	0	0
T47	0	110	0	0
T53	47415	0	0	0
T54	0	38	0	0
T60	15751	0	0	0
T76	0	83	0	0
T77	0	193	0	0
T81	0	41	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T181	0	40	0	0
T182	0	36	0	0
T183	0	82	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	15	0	0
T46	2680	1	0	0
T47	761	0	0	0
T58	18739	0	0	0
T64	1247	0	0	0
T65	1115	0	0	0
T76	0	1	0	0
T77	0	2	0	0
T89	739	0	0	0
T93	9431	0	0	0
T123	0	1	0	0
T157	0	1	0	0
T165	0	1	0	0
T168	423	0	0	0
T169	490	0	0	0
T170	524	0	0	0
T174	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T21,T42,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T21,T42,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T21,T42,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T42,T53
1	0	Covered	T39,T40,T41
1	1	Covered	T21,T42,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T42,T48
0	1	Covered	T76,T171,T167
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T48,T47
0	1	Covered	T42,T48,T47
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T48,T47
1	-	Covered	T42,T48,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T42,T48
0	1	Covered	T21,T42,T48
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T42,T48
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T42,T48
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T42,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T182,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T42,T48
DetectSt	-	-	-	-	1	-	-	Covered	T76,T171,T167
DetectSt	-	-	-	-	0	1	-	Covered	T21,T42,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T48,T47
StableSt	-	-	-	-	-	-	0	Covered	T21,T48,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	129	0	0
CntIncr_A	7802265	91806	0	0
CntNoWrap_A	7802265	7134775	0	0
DetectStDropOut_A	7802265	4	0	0
DetectedOut_A	7802265	34971	0	0
DetectedPulseOut_A	7802265	59	0	0
DisabledIdleSt_A	7802265	6651153	0	0
DisabledNoDetection_A	7802265	6653550	0	0
EnterDebounceSt_A	7802265	66	0	0
EnterDetectSt_A	7802265	63	0	0
EnterStableSt_A	7802265	59	0	0
PulseIsPulse_A	7802265	59	0	0
StayInStableSt	7802265	34885	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802265	2935	0	0
gen_low_level_sva.LowLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	129	0	0
T21	809	2	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	2	0	0
T47	0	2	0	0
T48	0	4	0	0
T49	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T56	28081	0	0	0
T76	0	4	0	0
T86	15713	0	0	0
T155	0	2	0	0
T186	0	2	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	91806	0	0
T21	809	77	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	53	0	0
T47	0	71	0	0
T48	0	186	0	0
T49	0	14	0	0
T52	0	20	0	0
T54	0	80	0	0
T56	28081	0	0	0
T76	0	96	0	0
T86	15713	0	0	0
T155	0	14	0	0
T186	0	79	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134775	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	4	0	0
T76	844	1	0	0
T94	4965	0	0	0
T167	0	1	0	0
T171	0	1	0	0
T184	0	1	0	0
T186	639	0	0	0
T191	38399	0	0	0
T192	8885	0	0	0
T193	38169	0	0	0
T194	506	0	0	0
T195	493	0	0	0
T196	18543	0	0	0
T197	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34971	0	0
T21	809	147	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	1	0	0
T47	0	44	0	0
T48	0	204	0	0
T49	0	58	0	0
T52	0	38	0	0
T54	0	268	0	0
T56	28081	0	0	0
T76	0	98	0	0
T86	15713	0	0	0
T155	0	49	0	0
T186	0	39	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	59	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	28081	0	0	0
T76	0	1	0	0
T86	15713	0	0	0
T155	0	1	0	0
T186	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6651153	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6653550	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	66	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	28081	0	0	0
T76	0	2	0	0
T86	15713	0	0	0
T155	0	1	0	0
T186	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	63	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	28081	0	0	0
T76	0	2	0	0
T86	15713	0	0	0
T155	0	1	0	0
T186	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	59	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	28081	0	0	0
T76	0	1	0	0
T86	15713	0	0	0
T155	0	1	0	0
T186	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	59	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	28081	0	0	0
T76	0	1	0	0
T86	15713	0	0	0
T155	0	1	0	0
T186	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34885	0	0
T21	809	145	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T47	0	43	0	0
T48	0	201	0	0
T49	0	56	0	0
T52	0	36	0	0
T54	0	267	0	0
T56	28081	0	0	0
T76	0	97	0	0
T86	15713	0	0	0
T155	0	47	0	0
T186	0	37	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	153	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	2935	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	6	0	0
T17	0	4	0	0
T29	490	3	0	0
T30	2238	11	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	0	6	0	0
T39	423	3	0	0
T40	522	6	0	0
T41	423	2	0	0
T63	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	31	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T53	47415	0	0	0
T54	0	1	0	0
T60	15751	0	0	0
T76	0	1	0	0
T77	0	2	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T121	505	0	0	0
T153	0	2	0	0
T156	0	1	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T19,T42,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T19,T42,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T19,T42,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T42,T53
1	0	Covered	T39,T40,T41
1	1	Covered	T19,T42,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T42,T53
0	1	Covered	T19,T199,T200
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T42,T53
0	1	Covered	T19,T48,T152
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T42,T53
1	-	Covered	T19,T48,T152

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T42,T53
0	1	Covered	T19,T42,T53
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T42,T53
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T42,T53
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T42,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T201
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T42,T53
DetectSt	-	-	-	-	1	-	-	Covered	T19,T199,T200
DetectSt	-	-	-	-	0	1	-	Covered	T19,T42,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T48,T152
StableSt	-	-	-	-	-	-	0	Covered	T19,T42,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	103	0	0
CntIncr_A	7802265	87915	0	0
CntNoWrap_A	7802265	7134801	0	0
DetectStDropOut_A	7802265	4	0	0
DetectedOut_A	7802265	89712	0	0
DetectedPulseOut_A	7802265	46	0	0
DisabledIdleSt_A	7802265	6834110	0	0
DisabledNoDetection_A	7802265	6836512	0	0
EnterDebounceSt_A	7802265	53	0	0
EnterDetectSt_A	7802265	50	0	0
EnterStableSt_A	7802265	46	0	0
PulseIsPulse_A	7802265	46	0	0
StayInStableSt	7802265	89642	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	103	0	0
T19	668	6	0	0
T20	10025	0	0	0
T42	138002	2	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	6	0	0
T53	0	2	0	0
T54	0	3	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T152	0	2	0	0
T181	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	87915	0	0
T19	668	66	0	0
T20	10025	0	0	0
T42	138002	53	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T45	0	33	0	0
T46	0	83	0	0
T48	0	285	0	0
T53	0	83	0	0
T54	0	130	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T152	0	81	0	0
T181	0	14	0	0
T202	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134801	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	4	0	0
T19	668	1	0	0
T20	10025	0	0	0
T90	615	0	0	0
T172	0	1	0	0
T199	1074	1	0	0
T200	0	1	0	0
T203	540	0	0	0
T204	444	0	0	0
T205	616	0	0	0
T206	883	0	0	0
T207	521	0	0	0
T208	485	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	89712	0	0
T19	668	58	0	0
T20	10025	0	0	0
T42	138002	92	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T45	0	41	0	0
T46	0	179	0	0
T48	0	219	0	0
T53	0	56	0	0
T54	0	308	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T152	0	1	0	0
T181	0	42	0	0
T202	0	98	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	46	0	0
T19	668	2	0	0
T20	10025	0	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T152	0	1	0	0
T181	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6834110	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6836512	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	53	0	0
T19	668	3	0	0
T20	10025	0	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T152	0	1	0	0
T181	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	50	0	0
T19	668	3	0	0
T20	10025	0	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T152	0	1	0	0
T181	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	46	0	0
T19	668	2	0	0
T20	10025	0	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T152	0	1	0	0
T181	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	46	0	0
T19	668	2	0	0
T20	10025	0	0	0
T42	138002	1	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T152	0	1	0	0
T181	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	89642	0	0
T19	668	55	0	0
T20	10025	0	0	0
T42	138002	90	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T45	0	39	0	0
T46	0	177	0	0
T48	0	215	0	0
T53	0	54	0	0
T54	0	306	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T111	434	0	0	0
T112	429	0	0	0
T153	0	39	0	0
T181	0	40	0	0
T202	0	96	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	21	0	0
T19	668	1	0	0
T20	10025	0	0	0
T48	7038	2	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T77	0	1	0	0
T90	615	0	0	0
T119	524	0	0	0
T123	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T159	671	0	0	0
T171	0	1	0	0
T199	0	1	0	0
T205	0	1	0	0
T209	0	1	0	0
T210	408	0	0	0
T211	412	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T48,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T14,T48,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T48,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T42,T45
1	0	Covered	T39,T40,T41
1	1	Covered	T14,T48,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T48,T51
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T48,T51
0	1	Covered	T48,T50,T77
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T48,T51
1	-	Covered	T48,T50,T77

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T48,T51
0	1	Covered	T14,T48,T51
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T48,T51
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T48,T51
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T48,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T212
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T48,T51
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T14,T48,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T50,T77
StableSt	-	-	-	-	-	-	0	Covered	T14,T48,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	64	0	0
CntIncr_A	7802265	1909	0	0
CntNoWrap_A	7802265	7134840	0	0
DetectStDropOut_A	7802265	0	0	0
DetectedOut_A	7802265	1973	0	0
DetectedPulseOut_A	7802265	31	0	0
DisabledIdleSt_A	7802265	7069269	0	0
DisabledNoDetection_A	7802265	7071669	0	0
EnterDebounceSt_A	7802265	33	0	0
EnterDetectSt_A	7802265	31	0	0
EnterStableSt_A	7802265	31	0	0
PulseIsPulse_A	7802265	31	0	0
StayInStableSt	7802265	1922	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802265	6655	0	0
gen_low_level_sva.LowLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	64	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T48	0	4	0	0
T50	0	4	0	0
T51	0	2	0	0
T54	0	2	0	0
T77	0	4	0	0
T123	0	2	0	0
T153	0	2	0	0
T213	0	2	0	0
T214	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1909	0	0
T14	1083	92	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T48	0	192	0	0
T50	0	106	0	0
T51	0	67	0	0
T54	0	50	0	0
T77	0	36	0	0
T123	0	66	0	0
T153	0	53	0	0
T213	0	96	0	0
T214	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134840	0	0
T14	1083	680	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1973	0	0
T14	1083	44	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T48	0	81	0	0
T50	0	167	0	0
T51	0	37	0	0
T54	0	37	0	0
T77	0	74	0	0
T123	0	39	0	0
T153	0	321	0	0
T213	0	175	0	0
T214	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	31	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T77	0	2	0	0
T123	0	1	0	0
T153	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7069269	0	0
T14	1083	3	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7071669	0	0
T14	1083	3	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	33	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T77	0	2	0	0
T123	0	1	0	0
T153	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	31	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T77	0	2	0	0
T123	0	1	0	0
T153	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	31	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T77	0	2	0	0
T123	0	1	0	0
T153	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	31	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T77	0	2	0	0
T123	0	1	0	0
T153	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1922	0	0
T14	1083	42	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T48	0	78	0	0
T50	0	164	0	0
T51	0	35	0	0
T54	0	35	0	0
T77	0	72	0	0
T123	0	37	0	0
T153	0	319	0	0
T213	0	174	0	0
T214	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6655	0	0
T14	1083	1	0	0
T15	686	2	0	0
T16	29480	18	0	0
T17	0	9	0	0
T29	490	9	0	0
T30	2238	9	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	0	5	0	0
T39	423	3	0	0
T40	522	4	0	0
T41	423	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	10	0	0
T48	7038	1	0	0
T50	3579	1	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T77	3353	2	0	0
T102	19183	0	0	0
T119	524	0	0	0
T154	0	1	0	0
T158	0	1	0	0
T159	671	0	0	0
T172	0	1	0	0
T201	0	1	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	1	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T21,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T14,T21,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T21,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T21,T48
1	0	Covered	T39,T40,T41
1	1	Covered	T14,T21,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T48
0	1	Covered	T167
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T48
0	1	Covered	T14,T21,T48
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T21,T48
1	-	Covered	T14,T21,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T21,T48
0	1	Covered	T14,T21,T48
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T21,T48
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T21,T48
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T21,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T81,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T21,T48
DetectSt	-	-	-	-	1	-	-	Covered	T167
DetectSt	-	-	-	-	0	1	-	Covered	T14,T21,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T21,T48
StableSt	-	-	-	-	-	-	0	Covered	T14,T21,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	92	0	0
CntIncr_A	7802265	33805	0	0
CntNoWrap_A	7802265	7134812	0	0
DetectStDropOut_A	7802265	1	0	0
DetectedOut_A	7802265	119879	0	0
DetectedPulseOut_A	7802265	43	0	0
DisabledIdleSt_A	7802265	6884654	0	0
DisabledNoDetection_A	7802265	6887063	0	0
EnterDebounceSt_A	7802265	50	0	0
EnterDetectSt_A	7802265	44	0	0
EnterStableSt_A	7802265	43	0	0
PulseIsPulse_A	7802265	43	0	0
StayInStableSt	7802265	119816	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	92	0	0
T14	1083	4	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	2	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	4	0	0
T47	0	1	0	0
T48	0	4	0	0
T54	0	4	0	0
T76	0	2	0	0
T155	0	2	0	0
T186	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	33805	0	0
T14	1083	184	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	77	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	166	0	0
T47	0	71	0	0
T48	0	186	0	0
T54	0	160	0	0
T76	0	48	0	0
T155	0	14	0	0
T160	0	51	0	0
T186	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134812	0	0
T14	1083	678	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1	0	0
T167	6495	1	0	0
T215	654	0	0	0
T216	2850	0	0	0
T217	422	0	0	0
T218	855	0	0	0
T219	405	0	0	0
T220	500	0	0	0
T221	6366	0	0	0
T222	13345	0	0	0
T223	632	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	119879	0	0
T14	1083	263	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	98	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	219	0	0
T48	0	77	0	0
T54	0	84	0	0
T76	0	7	0	0
T155	0	75	0	0
T182	0	38	0	0
T186	0	151	0	0
T202	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	43	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T48	0	2	0	0
T54	0	2	0	0
T76	0	1	0	0
T155	0	1	0	0
T182	0	1	0	0
T186	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6884654	0	0
T14	1083	3	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6887063	0	0
T14	1083	3	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	50	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T54	0	2	0	0
T76	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0
T186	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	44	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T48	0	2	0	0
T54	0	2	0	0
T76	0	1	0	0
T155	0	1	0	0
T182	0	1	0	0
T186	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	43	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T48	0	2	0	0
T54	0	2	0	0
T76	0	1	0	0
T155	0	1	0	0
T182	0	1	0	0
T186	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	43	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	2	0	0
T48	0	2	0	0
T54	0	2	0	0
T76	0	1	0	0
T155	0	1	0	0
T182	0	1	0	0
T186	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	119816	0	0
T14	1083	260	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	97	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	216	0	0
T48	0	74	0	0
T54	0	81	0	0
T76	0	6	0	0
T155	0	73	0	0
T182	0	36	0	0
T186	0	149	0	0
T202	0	97	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	22	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T54	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T157	0	2	0	0
T199	0	1	0	0
T224	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T21,T45,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T21,T45,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T21,T45,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T53,T45
1	0	Covered	T39,T40,T41
1	1	Covered	T21,T45,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T45,T50
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T45,T50
0	1	Covered	T50,T152,T225
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T45,T50
1	-	Covered	T50,T152,T225

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T45,T48
0	1	Covered	T21,T45,T48
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T45,T50
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T45,T48
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T45,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T48
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T45,T48
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T21,T45,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T50,T152,T225
StableSt	-	-	-	-	-	-	0	Covered	T21,T45,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	48	0	0
CntIncr_A	7802265	26284	0	0
CntNoWrap_A	7802265	7134856	0	0
DetectStDropOut_A	7802265	0	0	0
DetectedOut_A	7802265	1977	0	0
DetectedPulseOut_A	7802265	23	0	0
DisabledIdleSt_A	7802265	7070000	0	0
DisabledNoDetection_A	7802265	7072403	0	0
EnterDebounceSt_A	7802265	25	0	0
EnterDetectSt_A	7802265	23	0	0
EnterStableSt_A	7802265	23	0	0
PulseIsPulse_A	7802265	23	0	0
StayInStableSt	7802265	1940	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802265	6284	0	0
gen_low_level_sva.LowLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	48	0	0
T21	809	2	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T45	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T56	28081	0	0	0
T77	0	2	0	0
T81	0	2	0	0
T86	15713	0	0	0
T152	0	2	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	2	0	0
T225	0	4	0	0
T226	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	26284	0	0
T21	809	77	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T45	0	33	0	0
T48	0	93	0	0
T50	0	53	0	0
T56	28081	0	0	0
T77	0	45	0	0
T81	0	88	0	0
T86	15713	0	0	0
T152	0	81	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	96	0	0
T225	0	54	0	0
T226	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134856	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1977	0	0
T21	809	147	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T45	0	42	0	0
T50	0	40	0	0
T56	28081	0	0	0
T77	0	93	0	0
T81	0	316	0	0
T86	15713	0	0	0
T152	0	258	0	0
T165	0	126	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	171	0	0
T225	0	83	0	0
T226	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	23	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T45	0	1	0	0
T50	0	1	0	0
T56	28081	0	0	0
T77	0	1	0	0
T81	0	1	0	0
T86	15713	0	0	0
T152	0	1	0	0
T165	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0
T225	0	2	0	0
T226	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7070000	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7072403	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	25	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T56	28081	0	0	0
T77	0	1	0	0
T81	0	1	0	0
T86	15713	0	0	0
T152	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0
T225	0	2	0	0
T226	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	23	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T45	0	1	0	0
T50	0	1	0	0
T56	28081	0	0	0
T77	0	1	0	0
T81	0	1	0	0
T86	15713	0	0	0
T152	0	1	0	0
T165	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0
T225	0	2	0	0
T226	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	23	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T45	0	1	0	0
T50	0	1	0	0
T56	28081	0	0	0
T77	0	1	0	0
T81	0	1	0	0
T86	15713	0	0	0
T152	0	1	0	0
T165	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0
T225	0	2	0	0
T226	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	23	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T45	0	1	0	0
T50	0	1	0	0
T56	28081	0	0	0
T77	0	1	0	0
T81	0	1	0	0
T86	15713	0	0	0
T152	0	1	0	0
T165	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0
T225	0	2	0	0
T226	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1940	0	0
T21	809	145	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T45	0	40	0	0
T50	0	39	0	0
T56	28081	0	0	0
T77	0	91	0	0
T81	0	314	0	0
T86	15713	0	0	0
T152	0	257	0	0
T165	0	124	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	169	0	0
T225	0	80	0	0
T226	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6284	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	16	0	0
T17	0	7	0	0
T18	0	29	0	0
T29	490	7	0	0
T30	2238	11	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	0	3	0	0
T39	423	2	0	0
T40	522	4	0	0
T41	423	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	8	0	0
T50	3579	1	0	0
T152	1080	1	0	0
T161	408	0	0	0
T162	751	0	0	0
T163	429	0	0	0
T164	51503	0	0	0
T166	2706	1	0	0
T201	0	2	0	0
T225	698	1	0	0
T227	0	1	0	0
T228	0	1	0	0
T229	671	0	0	0
T230	20986	0	0	0