Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T42,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T14,T42,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T42,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T42,T45
1	0	Covered	T39,T40,T41
1	1	Covered	T14,T42,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T48,T46
0	1	Covered	T14,T42,T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T48,T46
0	1	Covered	T45,T48,T46
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T48,T46
1	-	Covered	T45,T48,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T42,T45
0	1	Covered	T14,T42,T45
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T42,T45
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T42,T45
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T42,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T46,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T42,T45
DetectSt	-	-	-	-	1	-	-	Covered	T14,T42,T171
DetectSt	-	-	-	-	0	1	-	Covered	T45,T48,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T48,T46
StableSt	-	-	-	-	-	-	0	Covered	T45,T48,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	91	0	0
CntIncr_A	7802265	33218	0	0
CntNoWrap_A	7802265	7134813	0	0
DetectStDropOut_A	7802265	5	0	0
DetectedOut_A	7802265	30945	0	0
DetectedPulseOut_A	7802265	37	0	0
DisabledIdleSt_A	7802265	6885296	0	0
DisabledNoDetection_A	7802265	6887704	0	0
EnterDebounceSt_A	7802265	50	0	0
EnterDetectSt_A	7802265	42	0	0
EnterStableSt_A	7802265	37	0	0
PulseIsPulse_A	7802265	37	0	0
StayInStableSt	7802265	30895	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	91	0	0
T14	1083	3	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T45	0	4	0	0
T46	0	3	0	0
T47	0	2	0	0
T48	0	2	0	0
T52	0	2	0	0
T54	0	6	0	0
T156	0	2	0	0
T186	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	33218	0	0
T14	1083	184	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	53	0	0
T45	0	66	0	0
T46	0	166	0	0
T47	0	71	0	0
T48	0	99	0	0
T52	0	20	0	0
T54	0	180	0	0
T156	0	93	0	0
T186	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134813	0	0
T14	1083	679	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	5	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T171	0	1	0	0
T172	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	30945	0	0
T45	13894	83	0	0
T46	0	35	0	0
T47	0	96	0	0
T48	7038	85	0	0
T50	0	211	0	0
T52	0	38	0	0
T54	0	270	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	251	0	0
T156	0	51	0	0
T159	671	0	0	0
T186	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	37	0	0
T45	13894	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	7038	1	0	0
T50	0	3	0	0
T52	0	1	0	0
T54	0	3	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	1	0	0
T156	0	1	0	0
T159	671	0	0	0
T186	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6885296	0	0
T14	1083	3	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6887704	0	0
T14	1083	3	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	50	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	3	0	0
T156	0	1	0	0
T186	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	42	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	3	0	0
T156	0	1	0	0
T186	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	37	0	0
T45	13894	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	7038	1	0	0
T50	0	3	0	0
T52	0	1	0	0
T54	0	3	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	1	0	0
T156	0	1	0	0
T159	671	0	0	0
T186	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	37	0	0
T45	13894	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	7038	1	0	0
T50	0	3	0	0
T52	0	1	0	0
T54	0	3	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	1	0	0
T156	0	1	0	0
T159	671	0	0	0
T186	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	30895	0	0
T45	13894	80	0	0
T46	0	34	0	0
T47	0	95	0	0
T48	7038	84	0	0
T50	0	207	0	0
T52	0	36	0	0
T54	0	267	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	250	0	0
T156	0	50	0	0
T159	671	0	0	0
T186	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	23	0	0
T45	13894	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	7038	1	0	0
T50	0	2	0	0
T54	0	3	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T152	0	1	0	0
T156	0	1	0	0
T159	671	0	0	0
T183	0	1	0	0
T225	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T19,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T19,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T19,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T48
1	0	Covered	T40,T41,T14
1	1	Covered	T19,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T48,T49
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T48,T49
0	1	Covered	T19,T50,T213
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T48,T49
1	-	Covered	T19,T50,T213

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T48,T49
0	1	Covered	T19,T48,T49
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T48,T49
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T54
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T48,T49
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T19,T48,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T50,T213
StableSt	-	-	-	-	-	-	0	Covered	T19,T48,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	70	0	0
CntIncr_A	7802265	30990	0	0
CntNoWrap_A	7802265	7134834	0	0
DetectStDropOut_A	7802265	0	0	0
DetectedOut_A	7802265	2079	0	0
DetectedPulseOut_A	7802265	34	0	0
DisabledIdleSt_A	7802265	6838059	0	0
DisabledNoDetection_A	7802265	6840460	0	0
EnterDebounceSt_A	7802265	36	0	0
EnterDetectSt_A	7802265	34	0	0
EnterStableSt_A	7802265	34	0	0
PulseIsPulse_A	7802265	34	0	0
StayInStableSt	7802265	2024	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802265	6135	0	0
gen_low_level_sva.LowLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	70	0	0
T19	668	2	0	0
T20	10025	0	0	0
T48	7038	2	0	0
T49	0	2	0	0
T50	0	4	0	0
T54	0	5	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T76	0	2	0	0
T90	615	0	0	0
T119	524	0	0	0
T156	0	2	0	0
T159	671	0	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	4	0	0
T231	0	2	0	0
T232	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	30990	0	0
T19	668	22	0	0
T20	10025	0	0	0
T48	7038	99	0	0
T49	0	14	0	0
T50	0	106	0	0
T54	0	180	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T76	0	48	0	0
T90	615	0	0	0
T119	524	0	0	0
T156	0	93	0	0
T159	671	0	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	192	0	0
T231	0	57	0	0
T232	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134834	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	2079	0	0
T19	668	42	0	0
T20	10025	0	0	0
T48	7038	42	0	0
T49	0	43	0	0
T50	0	41	0	0
T54	0	77	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T76	0	42	0	0
T90	615	0	0	0
T119	524	0	0	0
T156	0	42	0	0
T159	671	0	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	82	0	0
T231	0	38	0	0
T232	0	134	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34	0	0
T19	668	1	0	0
T20	10025	0	0	0
T48	7038	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	2	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T76	0	1	0	0
T90	615	0	0	0
T119	524	0	0	0
T156	0	1	0	0
T159	671	0	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	2	0	0
T231	0	1	0	0
T232	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6838059	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6840460	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	36	0	0
T19	668	1	0	0
T20	10025	0	0	0
T48	7038	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	3	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T76	0	1	0	0
T90	615	0	0	0
T119	524	0	0	0
T156	0	1	0	0
T159	671	0	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	2	0	0
T231	0	1	0	0
T232	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34	0	0
T19	668	1	0	0
T20	10025	0	0	0
T48	7038	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	2	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T76	0	1	0	0
T90	615	0	0	0
T119	524	0	0	0
T156	0	1	0	0
T159	671	0	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	2	0	0
T231	0	1	0	0
T232	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34	0	0
T19	668	1	0	0
T20	10025	0	0	0
T48	7038	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	2	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T76	0	1	0	0
T90	615	0	0	0
T119	524	0	0	0
T156	0	1	0	0
T159	671	0	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	2	0	0
T231	0	1	0	0
T232	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34	0	0
T19	668	1	0	0
T20	10025	0	0	0
T48	7038	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	2	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T76	0	1	0	0
T90	615	0	0	0
T119	524	0	0	0
T156	0	1	0	0
T159	671	0	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	2	0	0
T231	0	1	0	0
T232	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	2024	0	0
T19	668	41	0	0
T20	10025	0	0	0
T48	7038	40	0	0
T49	0	41	0	0
T50	0	39	0	0
T54	0	73	0	0
T57	37129	0	0	0
T61	196514	0	0	0
T76	0	40	0	0
T90	615	0	0	0
T119	524	0	0	0
T156	0	40	0	0
T159	671	0	0	0
T210	408	0	0	0
T211	412	0	0	0
T213	0	79	0	0
T231	0	36	0	0
T232	0	132	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6135	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	11	0	0
T17	0	7	0	0
T18	0	24	0	0
T29	490	8	0	0
T30	2238	14	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	4	0	0
T40	522	3	0	0
T41	423	2	0	0
T63	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	12	0	0
T19	668	1	0	0
T20	10025	0	0	0
T50	3579	2	0	0
T90	615	0	0	0
T123	0	1	0	0
T141	0	1	0	0
T157	1110	0	0	0
T158	0	1	0	0
T165	0	1	0	0
T213	914	1	0	0
T218	0	1	0	0
T233	0	1	0	0
T234	0	1	0	0
T235	407	0	0	0
T236	2333	0	0	0
T237	19857	0	0	0
T238	501	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T47,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T14,T47,T52

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T47,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T53,T47
1	0	Covered	T39,T40,T41
1	1	Covered	T14,T47,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T47,T52
0	1	Covered	T214,T200,T223
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T47,T52
0	1	Covered	T76,T152,T213
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T47,T52
1	-	Covered	T76,T152,T213

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T47,T52
0	1	Covered	T14,T47,T52
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T47,T52
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T47,T52
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T47,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T47,T52
DetectSt	-	-	-	-	1	-	-	Covered	T214,T200,T223
DetectSt	-	-	-	-	0	1	-	Covered	T14,T47,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T76,T152,T213
StableSt	-	-	-	-	-	-	0	Covered	T14,T47,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	85	0	0
CntIncr_A	7802265	60359	0	0
CntNoWrap_A	7802265	7134819	0	0
DetectStDropOut_A	7802265	3	0	0
DetectedOut_A	7802265	27199	0	0
DetectedPulseOut_A	7802265	38	0	0
DisabledIdleSt_A	7802265	6890072	0	0
DisabledNoDetection_A	7802265	6892479	0	0
EnterDebounceSt_A	7802265	44	0	0
EnterDetectSt_A	7802265	41	0	0
EnterStableSt_A	7802265	38	0	0
PulseIsPulse_A	7802265	38	0	0
StayInStableSt	7802265	27146	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	85	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T47	0	3	0	0
T52	0	2	0	0
T76	0	6	0	0
T152	0	2	0	0
T182	0	2	0	0
T213	0	2	0	0
T214	0	4	0	0
T225	0	4	0	0
T239	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	60359	0	0
T14	1083	92	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T47	0	142	0	0
T52	0	20	0	0
T76	0	144	0	0
T152	0	81	0	0
T182	0	48	0	0
T213	0	96	0	0
T214	0	28	0	0
T225	0	54	0	0
T239	0	23	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134819	0	0
T14	1083	680	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	3	0	0
T122	614	0	0	0
T171	674	0	0	0
T200	589	1	0	0
T214	558	1	0	0
T223	0	1	0	0
T240	415	0	0	0
T241	767	0	0	0
T242	491	0	0	0
T243	526	0	0	0
T244	424	0	0	0
T245	8841	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	27199	0	0
T14	1083	496	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T47	0	41	0	0
T52	0	39	0	0
T76	0	54	0	0
T152	0	249	0	0
T182	0	61	0	0
T213	0	175	0	0
T214	0	46	0	0
T225	0	107	0	0
T239	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	38	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T47	0	1	0	0
T52	0	1	0	0
T76	0	3	0	0
T152	0	1	0	0
T182	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T225	0	2	0	0
T239	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6890072	0	0
T14	1083	3	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6892479	0	0
T14	1083	3	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	44	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T47	0	2	0	0
T52	0	1	0	0
T76	0	3	0	0
T152	0	1	0	0
T182	0	1	0	0
T213	0	1	0	0
T214	0	2	0	0
T225	0	2	0	0
T239	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	41	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T47	0	1	0	0
T52	0	1	0	0
T76	0	3	0	0
T152	0	1	0	0
T182	0	1	0	0
T213	0	1	0	0
T214	0	2	0	0
T225	0	2	0	0
T239	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	38	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T47	0	1	0	0
T52	0	1	0	0
T76	0	3	0	0
T152	0	1	0	0
T182	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T225	0	2	0	0
T239	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	38	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T47	0	1	0	0
T52	0	1	0	0
T76	0	3	0	0
T152	0	1	0	0
T182	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T225	0	2	0	0
T239	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	27146	0	0
T14	1083	494	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T47	0	39	0	0
T52	0	37	0	0
T76	0	50	0	0
T152	0	248	0	0
T182	0	59	0	0
T213	0	174	0	0
T214	0	44	0	0
T225	0	105	0	0
T239	0	13	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	22	0	0
T76	844	2	0	0
T94	4965	0	0	0
T152	0	1	0	0
T158	0	1	0	0
T167	0	1	0	0
T186	639	0	0	0
T191	38399	0	0	0
T192	8885	0	0	0
T193	38169	0	0	0
T194	506	0	0	0
T195	493	0	0	0
T196	18543	0	0	0
T197	407	0	0	0
T199	0	1	0	0
T213	0	1	0	0
T225	0	2	0	0
T239	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T19,T21,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T19,T21,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T21,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T19,T21
1	0	Covered	T39,T40,T41
1	1	Covered	T19,T21,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T46,T47
0	1	Covered	T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T46,T47
0	1	Covered	T46,T47,T50
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T46,T47
1	-	Covered	T46,T47,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T21,T46
0	1	Covered	T19,T21,T46
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T46,T47
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T46
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T246,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T46
DetectSt	-	-	-	-	1	-	-	Covered	T77
DetectSt	-	-	-	-	0	1	-	Covered	T21,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T47,T50
StableSt	-	-	-	-	-	-	0	Covered	T21,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	89	0	0
CntIncr_A	7802265	91902	0	0
CntNoWrap_A	7802265	7134815	0	0
DetectStDropOut_A	7802265	1	0	0
DetectedOut_A	7802265	181097	0	0
DetectedPulseOut_A	7802265	41	0	0
DisabledIdleSt_A	7802265	6598297	0	0
DisabledNoDetection_A	7802265	6600693	0	0
EnterDebounceSt_A	7802265	47	0	0
EnterDetectSt_A	7802265	42	0	0
EnterStableSt_A	7802265	41	0	0
PulseIsPulse_A	7802265	41	0	0
StayInStableSt	7802265	181032	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802265	6260	0	0
gen_low_level_sva.LowLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	89	0	0
T19	668	1	0	0
T20	10025	0	0	0
T21	809	2	0	0
T22	1459	0	0	0
T23	486	0	0	0
T46	0	4	0	0
T47	0	2	0	0
T50	0	4	0	0
T54	0	2	0	0
T77	0	8	0	0
T90	615	0	0	0
T152	0	2	0	0
T157	0	2	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	91902	0	0
T19	668	22	0	0
T20	10025	0	0	0
T21	809	77	0	0
T22	1459	0	0	0
T23	486	0	0	0
T46	0	166	0	0
T47	0	71	0	0
T50	0	106	0	0
T54	0	80	0	0
T77	0	126	0	0
T90	615	0	0	0
T152	0	81	0	0
T157	0	81	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134815	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1	0	0
T77	3353	1	0	0
T82	920	0	0	0
T102	19183	0	0	0
T103	5216	0	0	0
T133	518	0	0	0
T134	424	0	0	0
T135	18192	0	0	0
T136	48945	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	181097	0	0
T21	809	38	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	99	0	0
T47	0	115	0	0
T50	0	165	0	0
T54	0	41	0	0
T56	28081	0	0	0
T77	0	75	0	0
T86	15713	0	0	0
T152	0	176	0	0
T157	0	158	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	39	0	0
T214	0	58	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	41	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	2	0	0
T54	0	1	0	0
T56	28081	0	0	0
T77	0	3	0	0
T86	15713	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0
T214	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6598297	0	0
T14	1083	3	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6600693	0	0
T14	1083	3	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	47	0	0
T19	668	1	0	0
T20	10025	0	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	2	0	0
T54	0	1	0	0
T77	0	4	0	0
T90	615	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	42	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	2	0	0
T54	0	1	0	0
T56	28081	0	0	0
T77	0	4	0	0
T86	15713	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0
T214	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	41	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	2	0	0
T54	0	1	0	0
T56	28081	0	0	0
T77	0	3	0	0
T86	15713	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0
T214	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	41	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	2	0	0
T54	0	1	0	0
T56	28081	0	0	0
T77	0	3	0	0
T86	15713	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	1	0	0
T214	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	181032	0	0
T21	809	36	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	96	0	0
T47	0	114	0	0
T50	0	162	0	0
T54	0	39	0	0
T56	28081	0	0	0
T77	0	71	0	0
T86	15713	0	0	0
T152	0	174	0	0
T157	0	156	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T213	0	37	0	0
T214	0	57	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6260	0	0
T14	1083	0	0	0
T15	686	0	0	0
T16	29480	20	0	0
T17	0	8	0	0
T18	0	29	0	0
T29	490	7	0	0
T30	2238	14	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	0	4	0	0
T39	423	3	0	0
T40	522	4	0	0
T41	423	5	0	0
T63	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	16	0	0
T46	2680	1	0	0
T47	761	1	0	0
T50	0	1	0	0
T58	18739	0	0	0
T64	1247	0	0	0
T65	1115	0	0	0
T77	0	2	0	0
T89	739	0	0	0
T93	9431	0	0	0
T123	0	1	0	0
T166	0	1	0	0
T168	423	0	0	0
T169	490	0	0	0
T170	524	0	0	0
T183	0	2	0	0
T184	0	1	0	0
T214	0	1	0	0
T248	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T21,T53,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T21,T53,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T21,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T53,T48
1	0	Covered	T39,T40,T41
1	1	Covered	T21,T53,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T46,T47
0	1	Covered	T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T46,T47
0	1	Covered	T21,T46,T54
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T46,T47
1	-	Covered	T21,T46,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T53,T46
0	1	Covered	T21,T53,T46
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T46,T47
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T53,T46
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T209,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T53,T46
DetectSt	-	-	-	-	1	-	-	Covered	T171
DetectSt	-	-	-	-	0	1	-	Covered	T21,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T46,T54
StableSt	-	-	-	-	-	-	0	Covered	T21,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	97	0	0
CntIncr_A	7802265	121384	0	0
CntNoWrap_A	7802265	7134807	0	0
DetectStDropOut_A	7802265	1	0	0
DetectedOut_A	7802265	118877	0	0
DetectedPulseOut_A	7802265	44	0	0
DisabledIdleSt_A	7802265	6600896	0	0
DisabledNoDetection_A	7802265	6603302	0	0
EnterDebounceSt_A	7802265	52	0	0
EnterDetectSt_A	7802265	45	0	0
EnterStableSt_A	7802265	44	0	0
PulseIsPulse_A	7802265	44	0	0
StayInStableSt	7802265	118816	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	97	0	0
T21	809	2	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T53	0	1	0	0
T54	0	4	0	0
T56	28081	0	0	0
T86	15713	0	0	0
T152	0	4	0	0
T156	0	2	0	0
T181	0	2	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	121384	0	0
T21	809	77	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	83	0	0
T47	0	71	0	0
T53	0	83	0	0
T54	0	160	0	0
T56	28081	0	0	0
T86	15713	0	0	0
T152	0	162	0	0
T156	0	93	0	0
T181	0	14	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	64	0	0
T202	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134807	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1	0	0
T171	674	1	0	0
T175	426	0	0	0
T176	18497	0	0	0
T177	19172	0	0	0
T178	606	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	118877	0	0
T21	809	206	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	25	0	0
T47	0	41	0	0
T54	0	83	0	0
T56	28081	0	0	0
T77	0	246	0	0
T86	15713	0	0	0
T152	0	218	0	0
T156	0	51	0	0
T181	0	61	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	49	0	0
T202	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	44	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0
T56	28081	0	0	0
T77	0	2	0	0
T86	15713	0	0	0
T152	0	2	0	0
T156	0	1	0	0
T181	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6600896	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6603302	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	52	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	28081	0	0	0
T86	15713	0	0	0
T152	0	2	0	0
T156	0	1	0	0
T181	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	45	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0
T56	28081	0	0	0
T77	0	2	0	0
T86	15713	0	0	0
T152	0	2	0	0
T156	0	1	0	0
T181	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	44	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0
T56	28081	0	0	0
T77	0	2	0	0
T86	15713	0	0	0
T152	0	2	0	0
T156	0	1	0	0
T181	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	44	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0
T56	28081	0	0	0
T77	0	2	0	0
T86	15713	0	0	0
T152	0	2	0	0
T156	0	1	0	0
T181	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	118816	0	0
T21	809	205	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	24	0	0
T47	0	39	0	0
T54	0	80	0	0
T56	28081	0	0	0
T77	0	243	0	0
T86	15713	0	0	0
T152	0	216	0	0
T156	0	50	0	0
T181	0	59	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	48	0	0
T202	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	26	0	0
T21	809	1	0	0
T22	1459	0	0	0
T23	486	0	0	0
T42	138002	0	0	0
T46	0	1	0	0
T54	0	1	0	0
T56	28081	0	0	0
T77	0	1	0	0
T86	15713	0	0	0
T152	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T165	0	1	0	0
T183	0	1	0	0
T187	402	0	0	0
T188	435	0	0	0
T189	432	0	0	0
T190	1253	0	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T19,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T14,T19,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T14,T19,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T19,T21
1	0	Covered	T39,T40,T41
1	1	Covered	T14,T19,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T21
0	1	Covered	T185
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T21
0	1	Covered	T14,T76,T54
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T19,T21
1	-	Covered	T14,T76,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T19,T21
0	1	Covered	T14,T19,T21
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T19,T21
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T19,T21
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T19,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T249
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T19,T21
DetectSt	-	-	-	-	1	-	-	Covered	T185
DetectSt	-	-	-	-	0	1	-	Covered	T14,T19,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T76,T54
StableSt	-	-	-	-	-	-	0	Covered	T14,T19,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	66	0	0
CntIncr_A	7802265	1705	0	0
CntNoWrap_A	7802265	7134838	0	0
DetectStDropOut_A	7802265	1	0	0
DetectedOut_A	7802265	2412	0	0
DetectedPulseOut_A	7802265	31	0	0
DisabledIdleSt_A	7802265	7069345	0	0
DisabledNoDetection_A	7802265	7071747	0	0
EnterDebounceSt_A	7802265	34	0	0
EnterDetectSt_A	7802265	32	0	0
EnterStableSt_A	7802265	31	0	0
PulseIsPulse_A	7802265	31	0	0
StayInStableSt	7802265	2361	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802265	6941	0	0
gen_low_level_sva.LowLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	66	0	0
T14	1083	4	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	2	0	0
T21	0	2	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T45	0	2	0	0
T48	0	2	0	0
T52	0	2	0	0
T54	0	4	0	0
T76	0	2	0	0
T77	0	6	0	0
T198	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1705	0	0
T14	1083	184	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	22	0	0
T21	0	77	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T45	0	33	0	0
T48	0	93	0	0
T52	0	20	0	0
T54	0	100	0	0
T76	0	48	0	0
T77	0	81	0	0
T198	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7134838	0	0
T14	1083	678	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1	0	0
T143	39899	0	0	0
T185	32947	1	0	0
T250	711	0	0	0
T251	11989	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	2412	0	0
T14	1083	85	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	213	0	0
T21	0	39	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T45	0	41	0	0
T48	0	38	0	0
T52	0	38	0	0
T54	0	127	0	0
T76	0	98	0	0
T77	0	112	0	0
T198	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	31	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T76	0	1	0	0
T77	0	3	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7069345	0	0
T14	1083	3	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7071747	0	0
T14	1083	3	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	34	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T76	0	1	0	0
T77	0	3	0	0
T198	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	32	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T76	0	1	0	0
T77	0	3	0	0
T198	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	31	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T76	0	1	0	0
T77	0	3	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	31	0	0
T14	1083	2	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	1	0	0
T21	0	1	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T76	0	1	0	0
T77	0	3	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	2361	0	0
T14	1083	82	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T19	0	211	0	0
T21	0	37	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T45	0	39	0	0
T48	0	36	0	0
T52	0	36	0	0
T54	0	124	0	0
T76	0	97	0	0
T77	0	108	0	0
T198	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6941	0	0
T14	1083	2	0	0
T15	686	2	0	0
T16	29480	17	0	0
T29	490	8	0	0
T30	2238	15	0	0
T31	670	3	0	0
T32	407	0	0	0
T33	0	3	0	0
T39	423	3	0	0
T40	522	5	0	0
T41	423	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	10	0	0
T14	1083	1	0	0
T15	686	0	0	0
T16	29480	0	0	0
T17	1479	0	0	0
T29	490	0	0	0
T30	2238	0	0	0
T31	670	0	0	0
T32	407	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T54	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T185	0	1	0	0
T212	0	1	0	0
T234	0	1	0	0
T252	0	1	0	0
T253	0	1	0	0