Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T20,T44
1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T18,T55,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T18,T55,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T18,T55,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T44
1	0	Covered	T18,T20,T44
1	1	Covered	T18,T55,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T55,T20
0	1	Covered	T78,T95,T97
1	0	Covered	T78,T95,T99

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T55,T20
0	1	Covered	T18,T20,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T55,T20
1	-	Covered	T18,T20,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T55,T20
0	1	Covered	T18,T55,T20
0	0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T55,T20
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T55,T20
IdleSt	0	-	-	-	-	-	-	Covered	T18,T20,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T55,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T73,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T55,T20
DetectSt	-	-	-	-	1	-	-	Covered	T78,T95,T97
DetectSt	-	-	-	-	0	1	-	Covered	T18,T55,T20
DetectSt	-	-	-	-	0	0	-	Covered	T18,T55,T20
StableSt	-	-	-	-	-	-	1	Covered	T18,T20,T44
StableSt	-	-	-	-	-	-	0	Covered	T18,T55,T20
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	3072	0	0
CntIncr_A	7802265	103742	0	0
CntNoWrap_A	7802265	7131832	0	0
DetectStDropOut_A	7802265	490	0	0
DetectedOut_A	7802265	89652	0	0
DetectedPulseOut_A	7802265	860	0	0
DisabledIdleSt_A	7802265	6642223	0	0
DisabledNoDetection_A	7802265	6644451	0	0
EnterDebounceSt_A	7802265	1542	0	0
EnterDetectSt_A	7802265	1530	0	0
EnterStableSt_A	7802265	860	0	0
PulseIsPulse_A	7802265	860	0	0
StayInStableSt	7802265	88669	0	0
gen_high_event_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	737	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	3072	0	0
T18	9276	22	0	0
T19	668	0	0	0
T20	10025	24	0	0
T44	14411	58	0	0
T55	470	2	0	0
T57	0	12	0	0
T58	0	22	0	0
T60	0	12	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	30	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	2	0	0
T254	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	103742	0	0
T18	9276	649	0	0
T19	668	0	0	0
T20	10025	912	0	0
T44	14411	2668	0	0
T55	470	21	0	0
T57	0	396	0	0
T58	0	759	0	0
T60	0	450	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	843	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	84	0	0
T254	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7131832	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	490	0	0
T45	13894	0	0	0
T48	7038	0	0	0
T78	30510	9	0	0
T95	0	16	0	0
T97	0	22	0	0
T98	0	13	0	0
T99	0	23	0	0
T100	0	27	0	0
T101	0	4	0	0
T103	0	13	0	0
T104	0	11	0	0
T105	0	10	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	89652	0	0
T18	9276	305	0	0
T19	668	0	0	0
T20	10025	161	0	0
T44	14411	1678	0	0
T55	470	45	0	0
T57	0	519	0	0
T58	0	2272	0	0
T60	0	1247	0	0
T62	736	0	0	0
T63	522	0	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	32	0	0
T254	0	78	0	0
T255	0	833	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	860	0	0
T18	9276	11	0	0
T19	668	0	0	0
T20	10025	12	0	0
T44	14411	29	0	0
T55	470	1	0	0
T57	0	6	0	0
T58	0	11	0	0
T60	0	6	0	0
T62	736	0	0	0
T63	522	0	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	1	0	0
T254	0	1	0	0
T255	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6642223	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6644451	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1542	0	0
T18	9276	11	0	0
T19	668	0	0	0
T20	10025	12	0	0
T44	14411	29	0	0
T55	470	1	0	0
T57	0	6	0	0
T58	0	11	0	0
T60	0	6	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	15	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	1	0	0
T254	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1530	0	0
T18	9276	11	0	0
T19	668	0	0	0
T20	10025	12	0	0
T44	14411	29	0	0
T55	470	1	0	0
T57	0	6	0	0
T58	0	11	0	0
T60	0	6	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	15	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	1	0	0
T254	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	860	0	0
T18	9276	11	0	0
T19	668	0	0	0
T20	10025	12	0	0
T44	14411	29	0	0
T55	470	1	0	0
T57	0	6	0	0
T58	0	11	0	0
T60	0	6	0	0
T62	736	0	0	0
T63	522	0	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	1	0	0
T254	0	1	0	0
T255	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	860	0	0
T18	9276	11	0	0
T19	668	0	0	0
T20	10025	12	0	0
T44	14411	29	0	0
T55	470	1	0	0
T57	0	6	0	0
T58	0	11	0	0
T60	0	6	0	0
T62	736	0	0	0
T63	522	0	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	1	0	0
T254	0	1	0	0
T255	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	88669	0	0
T18	9276	293	0	0
T19	668	0	0	0
T20	10025	148	0	0
T44	14411	1647	0	0
T55	470	43	0	0
T57	0	511	0	0
T58	0	2256	0	0
T60	0	1241	0	0
T62	736	0	0	0
T63	522	0	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	31	0	0
T254	0	76	0	0
T255	0	811	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	737	0	0
T18	9276	10	0	0
T19	668	0	0	0
T20	10025	11	0	0
T44	14411	27	0	0
T55	470	0	0	0
T57	0	4	0	0
T58	0	6	0	0
T60	0	6	0	0
T62	736	0	0	0
T63	522	0	0	0
T85	0	2	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	1	0	0
T255	0	20	0	0
T256	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T55
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T55
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T16,T18,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T16,T18,T55

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T16,T18,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T55
1	0	Covered	T30,T16,T17
1	1	Covered	T16,T18,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T56,T93,T94
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T16,T23,T42
1	0	Covered	T73,T75,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T20
1	-	Covered	T16,T23,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T55
0	1	Covered	T16,T18,T55
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T20
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T55
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T86,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T55
DetectSt	-	-	-	-	1	-	-	Covered	T56,T93,T94
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T20
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T20
StableSt	-	-	-	-	-	-	1	Covered	T16,T23,T42
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	924	0	0
CntIncr_A	7802265	46063	0	0
CntNoWrap_A	7802265	7133980	0	0
DetectStDropOut_A	7802265	66	0	0
DetectedOut_A	7802265	17273	0	0
DetectedPulseOut_A	7802265	350	0	0
DisabledIdleSt_A	7802265	6746224	0	0
DisabledNoDetection_A	7802265	6747884	0	0
EnterDebounceSt_A	7802265	508	0	0
EnterDetectSt_A	7802265	422	0	0
EnterStableSt_A	7802265	350	0	0
PulseIsPulse_A	7802265	350	0	0
StayInStableSt	7802265	16880	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	301	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	924	0	0
T16	29480	14	0	0
T17	1479	0	0	0
T18	9276	2	0	0
T19	668	0	0	0
T20	10025	2	0	0
T23	0	2	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	5	0	0
T43	0	10	0	0
T55	470	1	0	0
T56	0	10	0	0
T60	0	4	0	0
T62	736	0	0	0
T63	522	0	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	46063	0	0
T16	29480	1442	0	0
T17	1479	0	0	0
T18	9276	48	0	0
T19	668	0	0	0
T20	10025	86	0	0
T23	0	25	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	70	0	0
T43	0	480	0	0
T55	470	20	0	0
T56	0	602	0	0
T60	0	112	0	0
T62	736	0	0	0
T63	522	0	0	0
T86	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7133980	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28188	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	66	0	0
T42	138002	0	0	0
T43	32546	0	0	0
T44	14411	0	0	0
T56	28081	5	0	0
T60	15751	0	0	0
T71	0	5	0	0
T86	15713	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T93	0	9	0	0
T94	0	2	0	0
T96	0	6	0	0
T102	0	2	0	0
T106	0	4	0	0
T107	0	9	0	0
T108	0	6	0	0
T109	0	3	0	0
T111	434	0	0	0
T112	429	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	17273	0	0
T16	29480	34	0	0
T17	1479	0	0	0
T18	9276	88	0	0
T19	668	0	0	0
T20	10025	44	0	0
T23	0	4	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	6	0	0
T43	0	212	0	0
T45	0	3	0	0
T48	0	4	0	0
T53	0	974	0	0
T55	470	0	0	0
T60	0	146	0	0
T62	736	0	0	0
T63	522	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	350	0	0
T16	29480	7	0	0
T17	1479	0	0	0
T18	9276	1	0	0
T19	668	0	0	0
T20	10025	1	0	0
T23	0	1	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T43	0	5	0	0
T45	0	1	0	0
T48	0	1	0	0
T53	0	10	0	0
T55	470	0	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6746224	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	22289	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6747884	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	22290	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	508	0	0
T16	29480	7	0	0
T17	1479	0	0	0
T18	9276	1	0	0
T19	668	0	0	0
T20	10025	1	0	0
T23	0	1	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	3	0	0
T43	0	5	0	0
T55	470	1	0	0
T56	0	5	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T86	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	422	0	0
T16	29480	7	0	0
T17	1479	0	0	0
T18	9276	1	0	0
T19	668	0	0	0
T20	10025	1	0	0
T23	0	1	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T43	0	5	0	0
T45	0	1	0	0
T53	0	10	0	0
T55	470	0	0	0
T56	0	5	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	350	0	0
T16	29480	7	0	0
T17	1479	0	0	0
T18	9276	1	0	0
T19	668	0	0	0
T20	10025	1	0	0
T23	0	1	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T43	0	5	0	0
T45	0	1	0	0
T48	0	1	0	0
T53	0	10	0	0
T55	470	0	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	350	0	0
T16	29480	7	0	0
T17	1479	0	0	0
T18	9276	1	0	0
T19	668	0	0	0
T20	10025	1	0	0
T23	0	1	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T43	0	5	0	0
T45	0	1	0	0
T48	0	1	0	0
T53	0	10	0	0
T55	470	0	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	16880	0	0
T16	29480	27	0	0
T17	1479	0	0	0
T18	9276	86	0	0
T19	668	0	0	0
T20	10025	42	0	0
T23	0	3	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	4	0	0
T43	0	207	0	0
T45	0	2	0	0
T48	0	3	0	0
T53	0	964	0	0
T55	470	0	0	0
T60	0	144	0	0
T62	736	0	0	0
T63	522	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	301	0	0
T16	29480	7	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T23	0	1	0	0
T33	523	0	0	0
T34	402	0	0	0
T42	0	2	0	0
T43	0	5	0	0
T45	0	1	0	0
T48	0	1	0	0
T53	0	10	0	0
T55	470	0	0	0
T57	0	1	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T72	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T20,T44
1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T18,T20,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T18,T20,T44

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T18,T20,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T44
1	0	Covered	T18,T20,T44
1	1	Covered	T18,T20,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T44
0	1	Covered	T18,T60,T78
1	0	Covered	T18,T20,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T57,T58
0	1	Covered	T44,T57,T58
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T57,T58
1	-	Covered	T44,T57,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T20,T44
0	1	Covered	T18,T20,T44
0	0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T44
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T44
IdleSt	0	-	-	-	-	-	-	Covered	T18,T20,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T73,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T44
DetectSt	-	-	-	-	1	-	-	Covered	T18,T20,T60
DetectSt	-	-	-	-	0	1	-	Covered	T44,T57,T58
DetectSt	-	-	-	-	0	0	-	Covered	T18,T20,T44
StableSt	-	-	-	-	-	-	1	Covered	T44,T57,T58
StableSt	-	-	-	-	-	-	0	Covered	T44,T57,T58
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	3368	0	0
CntIncr_A	7802265	119648	0	0
CntNoWrap_A	7802265	7131536	0	0
DetectStDropOut_A	7802265	435	0	0
DetectedOut_A	7802265	111711	0	0
DetectedPulseOut_A	7802265	1074	0	0
DisabledIdleSt_A	7802265	6624541	0	0
DisabledNoDetection_A	7802265	6626744	0	0
EnterDebounceSt_A	7802265	1690	0	0
EnterDetectSt_A	7802265	1678	0	0
EnterStableSt_A	7802265	1074	0	0
PulseIsPulse_A	7802265	1074	0	0
StayInStableSt	7802265	110488	0	0
gen_high_event_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	924	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	3368	0	0
T18	9276	26	0	0
T19	668	0	0	0
T20	10025	10	0	0
T44	14411	58	0	0
T55	470	0	0	0
T57	0	50	0	0
T58	0	8	0	0
T60	0	46	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	52	0	0
T85	0	14	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	54	0	0
T255	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	119648	0	0
T18	9276	767	0	0
T19	668	0	0	0
T20	10025	384	0	0
T44	14411	2262	0	0
T55	470	0	0	0
T57	0	1950	0	0
T58	0	304	0	0
T60	0	3443	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	1465	0	0
T85	0	1380	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	1863	0	0
T255	0	684	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7131536	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	435	0	0
T18	9276	6	0	0
T19	668	0	0	0
T20	10025	0	0	0
T53	47415	0	0	0
T55	470	0	0	0
T60	15751	12	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	15	0	0
T90	615	0	0	0
T95	0	17	0	0
T97	0	10	0	0
T98	0	9	0	0
T99	0	23	0	0
T100	0	6	0	0
T103	0	28	0	0
T121	505	0	0	0
T237	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	111711	0	0
T44	14411	2084	0	0
T49	482	0	0	0
T53	47415	0	0	0
T57	37129	2492	0	0
T58	18739	297	0	0
T60	15751	0	0	0
T85	0	268	0	0
T91	425	0	0	0
T92	405	0	0	0
T93	9431	0	0	0
T121	505	0	0	0
T164	0	14338	0	0
T196	0	3296	0	0
T255	0	1656	0	0
T256	0	73	0	0
T257	0	129	0	0
T258	0	1063	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1074	0	0
T44	14411	29	0	0
T49	482	0	0	0
T53	47415	0	0	0
T57	37129	25	0	0
T58	18739	4	0	0
T60	15751	0	0	0
T85	0	3	0	0
T91	425	0	0	0
T92	405	0	0	0
T93	9431	0	0	0
T121	505	0	0	0
T164	0	32	0	0
T196	0	27	0	0
T255	0	12	0	0
T256	0	24	0	0
T257	0	7	0	0
T258	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6624541	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6626744	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1690	0	0
T18	9276	13	0	0
T19	668	0	0	0
T20	10025	5	0	0
T44	14411	29	0	0
T55	470	0	0	0
T57	0	25	0	0
T58	0	4	0	0
T60	0	23	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	26	0	0
T85	0	11	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	27	0	0
T255	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1678	0	0
T18	9276	13	0	0
T19	668	0	0	0
T20	10025	5	0	0
T44	14411	29	0	0
T55	470	0	0	0
T57	0	25	0	0
T58	0	4	0	0
T60	0	23	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	26	0	0
T85	0	3	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	27	0	0
T255	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1074	0	0
T44	14411	29	0	0
T49	482	0	0	0
T53	47415	0	0	0
T57	37129	25	0	0
T58	18739	4	0	0
T60	15751	0	0	0
T85	0	3	0	0
T91	425	0	0	0
T92	405	0	0	0
T93	9431	0	0	0
T121	505	0	0	0
T164	0	32	0	0
T196	0	27	0	0
T255	0	12	0	0
T256	0	24	0	0
T257	0	7	0	0
T258	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1074	0	0
T44	14411	29	0	0
T49	482	0	0	0
T53	47415	0	0	0
T57	37129	25	0	0
T58	18739	4	0	0
T60	15751	0	0	0
T85	0	3	0	0
T91	425	0	0	0
T92	405	0	0	0
T93	9431	0	0	0
T121	505	0	0	0
T164	0	32	0	0
T196	0	27	0	0
T255	0	12	0	0
T256	0	24	0	0
T257	0	7	0	0
T258	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	110488	0	0
T44	14411	2053	0	0
T49	482	0	0	0
T53	47415	0	0	0
T57	37129	2460	0	0
T58	18739	291	0	0
T60	15751	0	0	0
T85	0	265	0	0
T91	425	0	0	0
T92	405	0	0	0
T93	9431	0	0	0
T121	505	0	0	0
T164	0	14298	0	0
T196	0	3265	0	0
T255	0	1642	0	0
T256	0	49	0	0
T257	0	122	0	0
T258	0	1052	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	924	0	0
T44	14411	27	0	0
T49	482	0	0	0
T53	47415	0	0	0
T57	37129	18	0	0
T58	18739	2	0	0
T60	15751	0	0	0
T85	0	3	0	0
T91	425	0	0	0
T92	405	0	0	0
T93	9431	0	0	0
T121	505	0	0	0
T164	0	24	0	0
T196	0	23	0	0
T255	0	10	0	0
T256	0	24	0	0
T257	0	7	0	0
T258	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T20
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T16,T56,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T16,T56,T43

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T16,T56,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T56,T43
1	0	Covered	T30,T16,T17
1	1	Covered	T16,T56,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T56,T43
0	1	Covered	T72,T191,T94
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T56,T43
0	1	Covered	T16,T56,T43
1	0	Covered	T73,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T56,T43
1	-	Covered	T16,T56,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T56,T43
0	1	Covered	T16,T56,T43
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T56,T43
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T56,T43
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T56,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T93,T191
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T56,T43
DetectSt	-	-	-	-	1	-	-	Covered	T72,T191,T94
DetectSt	-	-	-	-	0	1	-	Covered	T16,T56,T43
DetectSt	-	-	-	-	0	0	-	Covered	T16,T56,T43
StableSt	-	-	-	-	-	-	1	Covered	T16,T56,T43
StableSt	-	-	-	-	-	-	0	Covered	T16,T56,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	1026	0	0
CntIncr_A	7802265	60871	0	0
CntNoWrap_A	7802265	7133878	0	0
DetectStDropOut_A	7802265	44	0	0
DetectedOut_A	7802265	18043	0	0
DetectedPulseOut_A	7802265	431	0	0
DisabledIdleSt_A	7802265	6719091	0	0
DisabledNoDetection_A	7802265	6720804	0	0
EnterDebounceSt_A	7802265	547	0	0
EnterDetectSt_A	7802265	479	0	0
EnterStableSt_A	7802265	431	0	0
PulseIsPulse_A	7802265	431	0	0
StayInStableSt	7802265	17572	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	389	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1026	0	0
T16	29480	16	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	21	0	0
T44	0	2	0	0
T45	0	2	0	0
T53	0	10	0	0
T55	470	0	0	0
T56	0	2	0	0
T57	0	14	0	0
T62	736	0	0	0
T63	522	0	0	0
T72	0	8	0	0
T93	0	5	0	0
T191	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	60871	0	0
T16	29480	1376	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	1338	0	0
T44	0	99	0	0
T45	0	51	0	0
T53	0	950	0	0
T55	470	0	0	0
T56	0	109	0	0
T57	0	350	0	0
T62	736	0	0	0
T63	522	0	0	0
T72	0	372	0	0
T93	0	163	0	0
T191	0	1264	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7133878	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28186	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	44	0	0
T46	2680	0	0	0
T47	761	0	0	0
T51	3010	0	0	0
T64	1247	0	0	0
T72	15256	4	0	0
T89	739	0	0	0
T94	0	1	0	0
T168	423	0	0	0
T169	490	0	0	0
T183	0	5	0	0
T191	0	9	0	0
T192	0	2	0	0
T254	504	0	0	0
T259	0	3	0	0
T260	0	1	0	0
T261	0	5	0	0
T262	0	3	0	0
T263	0	11	0	0
T264	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	18043	0	0
T16	29480	309	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	54	0	0
T44	0	56	0	0
T45	0	18	0	0
T53	0	58	0	0
T55	470	0	0	0
T56	0	11	0	0
T57	0	284	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	41	0	0
T193	0	276	0	0
T196	0	273	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	431	0	0
T16	29480	8	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	9	0	0
T44	0	1	0	0
T45	0	1	0	0
T53	0	5	0	0
T55	470	0	0	0
T56	0	1	0	0
T57	0	7	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	2	0	0
T193	0	16	0	0
T196	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6719091	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	22289	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6720804	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	22290	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	547	0	0
T16	29480	8	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	12	0	0
T44	0	1	0	0
T45	0	1	0	0
T53	0	5	0	0
T55	470	0	0	0
T56	0	1	0	0
T57	0	7	0	0
T62	736	0	0	0
T63	522	0	0	0
T72	0	4	0	0
T93	0	3	0	0
T191	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	479	0	0
T16	29480	8	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	9	0	0
T44	0	1	0	0
T45	0	1	0	0
T53	0	5	0	0
T55	470	0	0	0
T56	0	1	0	0
T57	0	7	0	0
T62	736	0	0	0
T63	522	0	0	0
T72	0	4	0	0
T93	0	2	0	0
T191	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	431	0	0
T16	29480	8	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	9	0	0
T44	0	1	0	0
T45	0	1	0	0
T53	0	5	0	0
T55	470	0	0	0
T56	0	1	0	0
T57	0	7	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	2	0	0
T193	0	16	0	0
T196	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	431	0	0
T16	29480	8	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	9	0	0
T44	0	1	0	0
T45	0	1	0	0
T53	0	5	0	0
T55	470	0	0	0
T56	0	1	0	0
T57	0	7	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	2	0	0
T193	0	16	0	0
T196	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	17572	0	0
T16	29480	301	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	45	0	0
T44	0	55	0	0
T45	0	17	0	0
T53	0	53	0	0
T55	470	0	0	0
T56	0	10	0	0
T57	0	277	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	39	0	0
T193	0	260	0	0
T196	0	265	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	389	0	0
T16	29480	8	0	0
T17	1479	0	0	0
T18	9276	0	0	0
T19	668	0	0	0
T20	10025	0	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	9	0	0
T44	0	1	0	0
T45	0	1	0	0
T53	0	5	0	0
T55	470	0	0	0
T56	0	1	0	0
T57	0	7	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	2	0	0
T193	0	16	0	0
T265	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T20,T44
1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T18,T20,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T18,T20,T44

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T18,T20,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T44
1	0	Covered	T18,T20,T44
1	1	Covered	T18,T20,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T44
0	1	Covered	T58,T95,T97
1	0	Covered	T58,T95,T256

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T44
0	1	Covered	T18,T20,T44
1	0	Covered	T74,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T20,T44
1	-	Covered	T18,T20,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T20,T44
0	1	Covered	T18,T20,T44
0	0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T44
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T44
IdleSt	0	-	-	-	-	-	-	Covered	T18,T20,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T73,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T44
DetectSt	-	-	-	-	1	-	-	Covered	T58,T95,T256
DetectSt	-	-	-	-	0	1	-	Covered	T18,T20,T44
DetectSt	-	-	-	-	0	0	-	Covered	T18,T20,T44
StableSt	-	-	-	-	-	-	1	Covered	T18,T20,T44
StableSt	-	-	-	-	-	-	0	Covered	T18,T20,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	3196	0	0
CntIncr_A	7802265	107833	0	0
CntNoWrap_A	7802265	7131708	0	0
DetectStDropOut_A	7802265	453	0	0
DetectedOut_A	7802265	87658	0	0
DetectedPulseOut_A	7802265	937	0	0
DisabledIdleSt_A	7802265	6643739	0	0
DisabledNoDetection_A	7802265	6645976	0	0
EnterDebounceSt_A	7802265	1603	0	0
EnterDetectSt_A	7802265	1593	0	0
EnterStableSt_A	7802265	937	0	0
PulseIsPulse_A	7802265	937	0	0
StayInStableSt	7802265	86607	0	0
gen_high_event_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	819	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	3196	0	0
T18	9276	56	0	0
T19	668	0	0	0
T20	10025	26	0	0
T44	14411	28	0	0
T55	470	0	0	0
T57	0	38	0	0
T58	0	24	0	0
T60	0	20	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	6	0	0
T85	0	9	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	28	0	0
T255	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	107833	0	0
T18	9276	1204	0	0
T19	668	0	0	0
T20	10025	676	0	0
T44	14411	1050	0	0
T55	470	0	0	0
T57	0	1140	0	0
T58	0	909	0	0
T60	0	880	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	150	0	0
T85	0	916	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	1274	0	0
T255	0	576	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7131708	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	453	0	0
T49	482	0	0	0
T58	18739	11	0	0
T93	9431	0	0	0
T95	11947	20	0	0
T97	0	4	0	0
T98	0	6	0	0
T99	0	18	0	0
T100	0	15	0	0
T103	0	10	0	0
T256	9610	0	0	0
T266	0	2	0	0
T267	0	20	0	0
T268	0	25	0	0
T269	526	0	0	0
T270	502	0	0	0
T271	502	0	0	0
T272	410	0	0	0
T273	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	87658	0	0
T18	9276	1808	0	0
T19	668	0	0	0
T20	10025	1034	0	0
T44	14411	737	0	0
T55	470	0	0	0
T57	0	1894	0	0
T60	0	1436	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	25	0	0
T85	0	144	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	356	0	0
T255	0	495	0	0
T257	0	1806	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	937	0	0
T18	9276	28	0	0
T19	668	0	0	0
T20	10025	13	0	0
T44	14411	14	0	0
T55	470	0	0	0
T57	0	19	0	0
T60	0	10	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	3	0	0
T85	0	2	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	14	0	0
T255	0	12	0	0
T257	0	31	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6643739	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28202	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6645976	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1603	0	0
T18	9276	28	0	0
T19	668	0	0	0
T20	10025	13	0	0
T44	14411	14	0	0
T55	470	0	0	0
T57	0	19	0	0
T58	0	12	0	0
T60	0	10	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	3	0	0
T85	0	7	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	14	0	0
T255	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	1593	0	0
T18	9276	28	0	0
T19	668	0	0	0
T20	10025	13	0	0
T44	14411	14	0	0
T55	470	0	0	0
T57	0	19	0	0
T58	0	12	0	0
T60	0	10	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	3	0	0
T85	0	2	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	14	0	0
T255	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	937	0	0
T18	9276	28	0	0
T19	668	0	0	0
T20	10025	13	0	0
T44	14411	14	0	0
T55	470	0	0	0
T57	0	19	0	0
T60	0	10	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	3	0	0
T85	0	2	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	14	0	0
T255	0	12	0	0
T257	0	31	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	937	0	0
T18	9276	28	0	0
T19	668	0	0	0
T20	10025	13	0	0
T44	14411	14	0	0
T55	470	0	0	0
T57	0	19	0	0
T60	0	10	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	3	0	0
T85	0	2	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	14	0	0
T255	0	12	0	0
T257	0	31	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	86607	0	0
T18	9276	1779	0	0
T19	668	0	0	0
T20	10025	1021	0	0
T44	14411	722	0	0
T55	470	0	0	0
T57	0	1872	0	0
T60	0	1424	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	22	0	0
T85	0	142	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	342	0	0
T255	0	483	0	0
T257	0	1774	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	819	0	0
T18	9276	27	0	0
T19	668	0	0	0
T20	10025	13	0	0
T44	14411	13	0	0
T55	470	0	0	0
T57	0	16	0	0
T60	0	8	0	0
T62	736	0	0	0
T63	522	0	0	0
T78	0	3	0	0
T85	0	2	0	0
T90	615	0	0	0
T91	425	0	0	0
T92	405	0	0	0
T196	0	14	0	0
T255	0	12	0	0
T257	0	30	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T20
1	Covered	T39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T39,T40,T41
1	1	Covered	T39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T16,T18,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T39,T40,T41	VC_COV_UNR
1	Covered	T16,T18,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T39,T40,T41
1	Covered	T16,T18,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T30,T16,T17
1	1	Covered	T16,T18,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T45,T72,T274
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T16,T18,T20
1	0	Covered	T73,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T20
1	-	Covered	T16,T18,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T20
0	1	Covered	T16,T18,T20
0	0	Excluded	T39,T40,T41	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T20
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T20
IdleSt	0	-	-	-	-	-	-	Covered	T39,T40,T41
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T43,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T20
DetectSt	-	-	-	-	1	-	-	Covered	T45,T72,T274
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T20
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T20
StableSt	-	-	-	-	-	-	1	Covered	T16,T18,T20
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802265	934	0	0
CntIncr_A	7802265	50195	0	0
CntNoWrap_A	7802265	7133970	0	0
DetectStDropOut_A	7802265	74	0	0
DetectedOut_A	7802265	16767	0	0
DetectedPulseOut_A	7802265	363	0	0
DisabledIdleSt_A	7802265	6730505	0	0
DisabledNoDetection_A	7802265	6732225	0	0
EnterDebounceSt_A	7802265	493	0	0
EnterDetectSt_A	7802265	441	0	0
EnterStableSt_A	7802265	363	0	0
PulseIsPulse_A	7802265	363	0	0
StayInStableSt	7802265	16379	0	0
gen_high_level_sva.HighLevelEvent_A	7802265	7137351	0	0
gen_not_sticky_sva.StableStDropOut_A	7802265	334	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	934	0	0
T16	29480	10	0	0
T17	1479	0	0	0
T18	9276	5	0	0
T19	668	0	0	0
T20	10025	4	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	16	0	0
T44	0	2	0	0
T45	0	2	0	0
T53	0	8	0	0
T55	470	0	0	0
T56	0	22	0	0
T57	0	6	0	0
T60	0	5	0	0
T62	736	0	0	0
T63	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	50195	0	0
T16	29480	780	0	0
T17	1479	0	0	0
T18	9276	135	0	0
T19	668	0	0	0
T20	10025	132	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	598	0	0
T44	0	60	0	0
T45	0	69	0	0
T53	0	820	0	0
T55	470	0	0	0
T56	0	1100	0	0
T57	0	120	0	0
T60	0	168	0	0
T62	736	0	0	0
T63	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7133970	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	28192	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	74	0	0
T45	13894	1	0	0
T48	7038	0	0	0
T70	0	13	0	0
T72	0	4	0	0
T106	0	1	0	0
T109	0	2	0	0
T113	422	0	0	0
T114	419	0	0	0
T115	502	0	0	0
T116	432	0	0	0
T117	511	0	0	0
T118	430	0	0	0
T119	524	0	0	0
T159	671	0	0	0
T222	0	8	0	0
T274	0	11	0	0
T275	0	12	0	0
T276	0	2	0	0
T277	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	16767	0	0
T16	29480	270	0	0
T17	1479	0	0	0
T18	9276	167	0	0
T19	668	0	0	0
T20	10025	129	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	464	0	0
T44	0	93	0	0
T53	0	18	0	0
T55	470	0	0	0
T56	0	231	0	0
T57	0	153	0	0
T60	0	137	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	363	0	0
T16	29480	5	0	0
T17	1479	0	0	0
T18	9276	2	0	0
T19	668	0	0	0
T20	10025	2	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T53	0	4	0	0
T55	470	0	0	0
T56	0	11	0	0
T57	0	3	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6730505	0	0
T14	1083	682	0	0
T15	686	285	0	0
T16	29480	22289	0	0
T29	490	89	0	0
T30	2238	635	0	0
T31	670	269	0	0
T32	407	6	0	0
T39	423	22	0	0
T40	522	121	0	0
T41	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	6732225	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	22290	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	493	0	0
T16	29480	5	0	0
T17	1479	0	0	0
T18	9276	3	0	0
T19	668	0	0	0
T20	10025	2	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	9	0	0
T44	0	1	0	0
T45	0	1	0	0
T53	0	4	0	0
T55	470	0	0	0
T56	0	11	0	0
T57	0	3	0	0
T60	0	3	0	0
T62	736	0	0	0
T63	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	441	0	0
T16	29480	5	0	0
T17	1479	0	0	0
T18	9276	2	0	0
T19	668	0	0	0
T20	10025	2	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T45	0	1	0	0
T53	0	4	0	0
T55	470	0	0	0
T56	0	11	0	0
T57	0	3	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	363	0	0
T16	29480	5	0	0
T17	1479	0	0	0
T18	9276	2	0	0
T19	668	0	0	0
T20	10025	2	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T53	0	4	0	0
T55	470	0	0	0
T56	0	11	0	0
T57	0	3	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	363	0	0
T16	29480	5	0	0
T17	1479	0	0	0
T18	9276	2	0	0
T19	668	0	0	0
T20	10025	2	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T53	0	4	0	0
T55	470	0	0	0
T56	0	11	0	0
T57	0	3	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	16379	0	0
T16	29480	265	0	0
T17	1479	0	0	0
T18	9276	165	0	0
T19	668	0	0	0
T20	10025	127	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	457	0	0
T44	0	91	0	0
T53	0	14	0	0
T55	470	0	0	0
T56	0	220	0	0
T57	0	150	0	0
T60	0	135	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	7137351	0	0
T14	1083	683	0	0
T15	686	286	0	0
T16	29480	28214	0	0
T29	490	90	0	0
T30	2238	638	0	0
T31	670	270	0	0
T32	407	7	0	0
T39	423	23	0	0
T40	522	122	0	0
T41	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802265	334	0	0
T16	29480	5	0	0
T17	1479	0	0	0
T18	9276	2	0	0
T19	668	0	0	0
T20	10025	2	0	0
T33	523	0	0	0
T34	402	0	0	0
T43	0	7	0	0
T53	0	4	0	0
T55	470	0	0	0
T56	0	11	0	0
T57	0	3	0	0
T60	0	2	0	0
T62	736	0	0	0
T63	522	0	0	0
T93	0	1	0	0
T191	0	10	0	0