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Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

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Module Instances:
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT18,T20,T44
1CoveredT39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT18,T20,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT18,T20,T44

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT18,T20,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT18,T20,T44
10CoveredT18,T20,T44
11CoveredT18,T20,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT18,T20,T44
01CoveredT58,T97,T98
10CoveredT58,T266,T278

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT18,T20,T44
01CoveredT18,T20,T44
10CoveredT75,T279

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT18,T20,T44
1-CoveredT18,T20,T44

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T6
DetectSt 168 Covered T6
IdleSt 163 Covered T6
StableSt 191 Covered T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T6
DebounceSt->IdleSt 163 Covered T6
DetectSt->IdleSt 186 Covered T6
DetectSt->StableSt 191 Covered T6
IdleSt->DebounceSt 148 Covered T6
StableSt->IdleSt 206 Covered T6



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T18,T20,T44
0 1 Covered T18,T20,T44
0 0 Covered T39,T40,T41


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T18,T20,T44
0 Covered T39,T40,T41


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T39,T40,T41


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T18,T20,T44
IdleSt 0 - - - - - - Covered T18,T20,T44
DebounceSt - 1 - - - - - Covered T73,T74
DebounceSt - 0 1 1 - - - Covered T18,T20,T44
DebounceSt - 0 1 0 - - - Covered T85,T73,T74
DebounceSt - 0 0 - - - - Covered T18,T20,T44
DetectSt - - - - 1 - - Covered T58,T97,T98
DetectSt - - - - 0 1 - Covered T18,T20,T44
DetectSt - - - - 0 0 - Covered T18,T20,T44
StableSt - - - - - - 1 Covered T18,T20,T44
StableSt - - - - - - 0 Covered T18,T20,T44
default - - - - - - - Not Covered


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T39,T40,T41


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7802265 3052 0 0
CntIncr_A 7802265 106809 0 0
CntNoWrap_A 7802265 7131852 0 0
DetectStDropOut_A 7802265 456 0 0
DetectedOut_A 7802265 64611 0 0
DetectedPulseOut_A 7802265 823 0 0
DisabledIdleSt_A 7802265 6654880 0 0
DisabledNoDetection_A 7802265 6657130 0 0
EnterDebounceSt_A 7802265 1533 0 0
EnterDetectSt_A 7802265 1521 0 0
EnterStableSt_A 7802265 823 0 0
PulseIsPulse_A 7802265 823 0 0
StayInStableSt 7802265 63686 0 0
gen_high_event_sva.HighLevelEvent_A 7802265 7137351 0 0
gen_high_level_sva.HighLevelEvent_A 7802265 7137351 0 0
gen_not_sticky_sva.StableStDropOut_A 7802265 710 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 3052 0 0
T18 9276 18 0 0
T19 668 0 0 0
T20 10025 46 0 0
T44 14411 50 0 0
T55 470 0 0 0
T57 0 42 0 0
T58 0 20 0 0
T60 0 2 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 50 0 0
T85 0 14 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T196 0 4 0 0
T255 0 24 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 106809 0 0
T18 9276 486 0 0
T19 668 0 0 0
T20 10025 1426 0 0
T44 14411 2050 0 0
T55 470 0 0 0
T57 0 1386 0 0
T58 0 760 0 0
T60 0 80 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 1350 0 0
T85 0 1374 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T196 0 134 0 0
T255 0 756 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 7131852 0 0
T14 1083 682 0 0
T15 686 285 0 0
T16 29480 28202 0 0
T29 490 89 0 0
T30 2238 635 0 0
T31 670 269 0 0
T32 407 6 0 0
T39 423 22 0 0
T40 522 121 0 0
T41 423 22 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 456 0 0
T49 482 0 0 0
T58 18739 7 0 0
T93 9431 0 0 0
T97 5316 19 0 0
T98 4724 10 0 0
T100 0 9 0 0
T101 0 4 0 0
T103 0 15 0 0
T266 0 8 0 0
T269 526 0 0 0
T270 502 0 0 0
T271 502 0 0 0
T278 0 18 0 0
T280 0 8 0 0
T281 0 13 0 0
T282 502 0 0 0
T283 10480 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 64611 0 0
T18 9276 347 0 0
T19 668 0 0 0
T20 10025 1598 0 0
T44 14411 1998 0 0
T55 470 0 0 0
T57 0 2179 0 0
T60 0 71 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 2879 0 0
T85 0 274 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T95 0 1822 0 0
T196 0 99 0 0
T255 0 309 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 823 0 0
T18 9276 9 0 0
T19 668 0 0 0
T20 10025 23 0 0
T44 14411 25 0 0
T55 470 0 0 0
T57 0 21 0 0
T60 0 1 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 25 0 0
T85 0 3 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T95 0 14 0 0
T196 0 2 0 0
T255 0 12 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 6654880 0 0
T14 1083 682 0 0
T15 686 285 0 0
T16 29480 28202 0 0
T29 490 89 0 0
T30 2238 635 0 0
T31 670 269 0 0
T32 407 6 0 0
T39 423 22 0 0
T40 522 121 0 0
T41 423 22 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 6657130 0 0
T14 1083 683 0 0
T15 686 286 0 0
T16 29480 28214 0 0
T29 490 90 0 0
T30 2238 638 0 0
T31 670 270 0 0
T32 407 7 0 0
T39 423 23 0 0
T40 522 122 0 0
T41 423 23 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 1533 0 0
T18 9276 9 0 0
T19 668 0 0 0
T20 10025 23 0 0
T44 14411 25 0 0
T55 470 0 0 0
T57 0 21 0 0
T58 0 10 0 0
T60 0 1 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 25 0 0
T85 0 11 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T196 0 2 0 0
T255 0 12 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 1521 0 0
T18 9276 9 0 0
T19 668 0 0 0
T20 10025 23 0 0
T44 14411 25 0 0
T55 470 0 0 0
T57 0 21 0 0
T58 0 10 0 0
T60 0 1 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 25 0 0
T85 0 3 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T196 0 2 0 0
T255 0 12 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 823 0 0
T18 9276 9 0 0
T19 668 0 0 0
T20 10025 23 0 0
T44 14411 25 0 0
T55 470 0 0 0
T57 0 21 0 0
T60 0 1 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 25 0 0
T85 0 3 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T95 0 14 0 0
T196 0 2 0 0
T255 0 12 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 823 0 0
T18 9276 9 0 0
T19 668 0 0 0
T20 10025 23 0 0
T44 14411 25 0 0
T55 470 0 0 0
T57 0 21 0 0
T60 0 1 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 25 0 0
T85 0 3 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T95 0 14 0 0
T196 0 2 0 0
T255 0 12 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 63686 0 0
T18 9276 338 0 0
T19 668 0 0 0
T20 10025 1574 0 0
T44 14411 1972 0 0
T55 470 0 0 0
T57 0 2151 0 0
T60 0 70 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 2843 0 0
T85 0 271 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T95 0 1806 0 0
T196 0 97 0 0
T255 0 296 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 7137351 0 0
T14 1083 683 0 0
T15 686 286 0 0
T16 29480 28214 0 0
T29 490 90 0 0
T30 2238 638 0 0
T31 670 270 0 0
T32 407 7 0 0
T39 423 23 0 0
T40 522 122 0 0
T41 423 23 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 7137351 0 0
T14 1083 683 0 0
T15 686 286 0 0
T16 29480 28214 0 0
T29 490 90 0 0
T30 2238 638 0 0
T31 670 270 0 0
T32 407 7 0 0
T39 423 23 0 0
T40 522 122 0 0
T41 423 23 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 710 0 0
T18 9276 9 0 0
T19 668 0 0 0
T20 10025 22 0 0
T44 14411 24 0 0
T55 470 0 0 0
T57 0 14 0 0
T60 0 1 0 0
T62 736 0 0 0
T63 522 0 0 0
T78 0 14 0 0
T85 0 3 0 0
T90 615 0 0 0
T91 425 0 0 0
T92 405 0 0 0
T95 0 12 0 0
T196 0 2 0 0
T255 0 11 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions2121100.00
Logical2121100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT16,T18,T20
1CoveredT39,T40,T41

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T18,T20
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT16,T20,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT39,T40,T41 VC_COV_UNR
1CoveredT16,T20,T43

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT16,T20,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T18,T20
10CoveredT30,T16,T17
11CoveredT16,T20,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T20,T43
01CoveredT93,T284,T73
10CoveredT73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT16,T20,T43
01CoveredT16,T20,T43
10CoveredT20

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT16,T20,T43
1-CoveredT16,T20,T43

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T6
DetectSt 168 Covered T6
IdleSt 163 Covered T6
StableSt 191 Covered T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T6
DebounceSt->IdleSt 163 Covered T6
DetectSt->IdleSt 186 Covered T6
DetectSt->StableSt 191 Covered T6
IdleSt->DebounceSt 148 Covered T6
StableSt->IdleSt 206 Covered T6



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 21 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 11 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T16,T20,T43
0 1 Covered T16,T20,T43
0 0 Excluded T39,T40,T41 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T20,T43
0 Covered T39,T40,T41


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T39,T40,T41


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T16,T20,T43
IdleSt 0 - - - - - - Covered T39,T40,T41
DebounceSt - 1 - - - - - Covered T73,T74
DebounceSt - 0 1 1 - - - Covered T16,T20,T43
DebounceSt - 0 1 0 - - - Covered T16,T93,T191
DebounceSt - 0 0 - - - - Covered T16,T20,T43
DetectSt - - - - 1 - - Covered T93,T284,T73
DetectSt - - - - 0 1 - Covered T16,T20,T43
DetectSt - - - - 0 0 - Covered T16,T20,T43
StableSt - - - - - - 1 Covered T16,T20,T43
StableSt - - - - - - 0 Covered T16,T20,T43
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T39,T40,T41


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T39,T40,T41


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7802265 886 0 0
CntIncr_A 7802265 49975 0 0
CntNoWrap_A 7802265 7134018 0 0
DetectStDropOut_A 7802265 60 0 0
DetectedOut_A 7802265 14338 0 0
DetectedPulseOut_A 7802265 356 0 0
DisabledIdleSt_A 7802265 6763781 0 0
DisabledNoDetection_A 7802265 6765534 0 0
EnterDebounceSt_A 7802265 467 0 0
EnterDetectSt_A 7802265 419 0 0
EnterStableSt_A 7802265 356 0 0
PulseIsPulse_A 7802265 356 0 0
StayInStableSt 7802265 13936 0 0
gen_high_level_sva.HighLevelEvent_A 7802265 7137351 0 0
gen_not_sticky_sva.StableStDropOut_A 7802265 304 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 886 0 0
T16 29480 11 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 10 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 16 0 0
T44 0 4 0 0
T45 0 2 0 0
T53 0 14 0 0
T55 470 0 0 0
T57 0 14 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 8 0 0
T78 0 22 0 0
T93 0 9 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 49975 0 0
T16 29480 651 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 340 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 864 0 0
T44 0 120 0 0
T45 0 47 0 0
T53 0 1370 0 0
T55 470 0 0 0
T57 0 392 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 212 0 0
T78 0 803 0 0
T93 0 397 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 7134018 0 0
T14 1083 682 0 0
T15 686 285 0 0
T16 29480 28191 0 0
T29 490 89 0 0
T30 2238 635 0 0
T31 670 269 0 0
T32 407 6 0 0
T39 423 22 0 0
T40 522 121 0 0
T41 423 22 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 60 0 0
T49 482 0 0 0
T73 0 1 0 0
T93 9431 4 0 0
T106 0 11 0 0
T107 0 1 0 0
T108 0 9 0 0
T176 0 14 0 0
T185 0 1 0 0
T269 526 0 0 0
T270 502 0 0 0
T271 502 0 0 0
T284 8576 5 0 0
T285 0 2 0 0
T286 0 4 0 0
T287 522 0 0 0
T288 424 0 0 0
T289 741 0 0 0
T290 404 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 14338 0 0
T16 29480 487 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 314 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 247 0 0
T44 0 190 0 0
T45 0 22 0 0
T53 0 78 0 0
T55 470 0 0 0
T57 0 241 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 160 0 0
T78 0 613 0 0
T191 0 56 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 356 0 0
T16 29480 5 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 5 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 8 0 0
T44 0 2 0 0
T45 0 1 0 0
T53 0 7 0 0
T55 470 0 0 0
T57 0 7 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 4 0 0
T78 0 11 0 0
T191 0 9 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 6763781 0 0
T14 1083 682 0 0
T15 686 285 0 0
T16 29480 22289 0 0
T29 490 89 0 0
T30 2238 635 0 0
T31 670 269 0 0
T32 407 6 0 0
T39 423 22 0 0
T40 522 121 0 0
T41 423 22 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 6765534 0 0
T14 1083 683 0 0
T15 686 286 0 0
T16 29480 22290 0 0
T29 490 90 0 0
T30 2238 638 0 0
T31 670 270 0 0
T32 407 7 0 0
T39 423 23 0 0
T40 522 122 0 0
T41 423 23 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 467 0 0
T16 29480 6 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 5 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 8 0 0
T44 0 2 0 0
T45 0 1 0 0
T53 0 7 0 0
T55 470 0 0 0
T57 0 7 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 4 0 0
T78 0 11 0 0
T93 0 5 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 419 0 0
T16 29480 5 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 5 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 8 0 0
T44 0 2 0 0
T45 0 1 0 0
T53 0 7 0 0
T55 470 0 0 0
T57 0 7 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 4 0 0
T78 0 11 0 0
T93 0 4 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 356 0 0
T16 29480 5 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 5 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 8 0 0
T44 0 2 0 0
T45 0 1 0 0
T53 0 7 0 0
T55 470 0 0 0
T57 0 7 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 4 0 0
T78 0 11 0 0
T191 0 9 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 356 0 0
T16 29480 5 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 5 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 8 0 0
T44 0 2 0 0
T45 0 1 0 0
T53 0 7 0 0
T55 470 0 0 0
T57 0 7 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 4 0 0
T78 0 11 0 0
T191 0 9 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 13936 0 0
T16 29480 482 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 309 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 239 0 0
T44 0 188 0 0
T45 0 21 0 0
T53 0 71 0 0
T55 470 0 0 0
T57 0 231 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 156 0 0
T78 0 591 0 0
T191 0 47 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 7137351 0 0
T14 1083 683 0 0
T15 686 286 0 0
T16 29480 28214 0 0
T29 490 90 0 0
T30 2238 638 0 0
T31 670 270 0 0
T32 407 7 0 0
T39 423 23 0 0
T40 522 122 0 0
T41 423 23 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802265 304 0 0
T16 29480 5 0 0
T17 1479 0 0 0
T18 9276 0 0 0
T19 668 0 0 0
T20 10025 3 0 0
T33 523 0 0 0
T34 402 0 0 0
T43 0 8 0 0
T44 0 2 0 0
T45 0 1 0 0
T53 0 7 0 0
T55 470 0 0 0
T57 0 4 0 0
T62 736 0 0 0
T63 522 0 0 0
T72 0 4 0 0
T191 0 9 0 0
T192 0 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%