Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1390629705	11680	0	0
auto_block_debounce_ctl_rd_A	1390629705	1670	0	0
auto_block_out_ctl_rd_A	1390629705	2012	0	0
com_det_ctl_0_rd_A	1390629705	3389	0	0
com_det_ctl_1_rd_A	1390629705	3702	0	0
com_det_ctl_2_rd_A	1390629705	3573	0	0
com_det_ctl_3_rd_A	1390629705	3691	0	0
com_out_ctl_0_rd_A	1390629705	4094	0	0
com_out_ctl_1_rd_A	1390629705	4053	0	0
com_out_ctl_2_rd_A	1390629705	3995	0	0
com_out_ctl_3_rd_A	1390629705	3944	0	0
com_pre_det_ctl_0_rd_A	1390629705	1148	0	0
com_pre_det_ctl_1_rd_A	1390629705	1132	0	0
com_pre_det_ctl_2_rd_A	1390629705	1268	0	0
com_pre_det_ctl_3_rd_A	1390629705	1141	0	0
com_pre_sel_ctl_0_rd_A	1390629705	4286	0	0
com_pre_sel_ctl_1_rd_A	1390629705	4219	0	0
com_pre_sel_ctl_2_rd_A	1390629705	4404	0	0
com_pre_sel_ctl_3_rd_A	1390629705	4170	0	0
com_sel_ctl_0_rd_A	1390629705	4079	0	0
com_sel_ctl_1_rd_A	1390629705	4165	0	0
com_sel_ctl_2_rd_A	1390629705	4135	0	0
com_sel_ctl_3_rd_A	1390629705	4153	0	0
ec_rst_ctl_rd_A	1390629705	2289	0	0
intr_enable_rd_A	1390629705	1636	0	0
key_intr_ctl_rd_A	1390629705	3189	0	0
key_intr_debounce_ctl_rd_A	1390629705	1129	0	0
key_invert_ctl_rd_A	1390629705	4456	0	0
pin_allowed_ctl_rd_A	1390629705	5170	0	0
pin_out_ctl_rd_A	1390629705	3537	0	0
pin_out_value_rd_A	1390629705	3810	0	0
regwen_rd_A	1390629705	1221	0	0
ulp_ac_debounce_ctl_rd_A	1390629705	1293	0	0
ulp_ctl_rd_A	1390629705	1218	0	0
ulp_lid_debounce_ctl_rd_A	1390629705	1311	0	0
ulp_pwrb_debounce_ctl_rd_A	1390629705	1326	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	11680	0	0
T9	13113	0	0	0
T10	889619	5	0	0
T11	221866	2	0	0
T12	48396	0	0	0
T13	0	8	0	0
T24	54401	214	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T291	0	848	0	0
T294	0	342	0	0
T295	0	663	0	0
T297	0	4	0	0
T304	14968	1	0	0
T311	0	4	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1670	0	0
T3	146367	8	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	23	0	0
T301	0	31	0	0
T304	0	6	0	0
T312	0	12	0	0
T313	0	13	0	0
T314	0	15	0	0
T315	0	8	0	0
T316	0	6	0	0
T317	0	38	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	2012	0	0
T3	146367	15	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	5	0	0
T300	0	28	0	0
T301	0	5	0	0
T304	0	4	0	0
T312	0	59	0	0
T314	0	13	0	0
T315	0	4	0	0
T316	0	5	0	0
T317	0	28	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	3389	0	0
T3	146367	10	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	15	0	0
T304	0	1	0	0
T312	0	5	0	0
T314	0	8	0	0
T315	0	4	0	0
T317	0	23	0	0
T318	0	252	0	0
T319	0	2	0	0
T320	0	25	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	3702	0	0
T3	146367	8	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	2	0	0
T300	0	5	0	0
T301	0	11	0	0
T312	0	13	0	0
T313	0	22	0	0
T314	0	3	0	0
T315	0	9	0	0
T316	0	4	0	0
T317	0	75	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	3573	0	0
T3	146367	14	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	7	0	0
T300	0	20	0	0
T304	0	3	0	0
T312	0	11	0	0
T313	0	39	0	0
T314	0	6	0	0
T315	0	6	0	0
T317	0	73	0	0
T318	0	212	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	3691	0	0
T3	146367	6	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	9	0	0
T300	0	20	0	0
T301	0	5	0	0
T304	0	4	0	0
T312	0	1	0	0
T313	0	39	0	0
T314	0	2	0	0
T315	0	1	0	0
T316	0	2	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4094	0	0
T3	146367	10	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	2	0	0
T300	0	59	0	0
T312	0	5	0	0
T313	0	45	0	0
T314	0	4	0	0
T316	0	1	0	0
T317	0	59	0	0
T318	0	246	0	0
T319	0	4	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4053	0	0
T3	146367	4	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	2	0	0
T300	0	61	0	0
T301	0	9	0	0
T304	0	1	0	0
T312	0	30	0	0
T313	0	11	0	0
T314	0	7	0	0
T315	0	1	0	0
T317	0	69	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	3995	0	0
T3	146367	12	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	52	0	0
T304	0	6	0	0
T312	0	14	0	0
T313	0	21	0	0
T314	0	16	0	0
T315	0	8	0	0
T316	0	1	0	0
T317	0	42	0	0
T318	0	195	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	3944	0	0
T3	146367	10	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	44	0	0
T301	0	13	0	0
T304	0	5	0	0
T312	0	34	0	0
T313	0	38	0	0
T314	0	6	0	0
T316	0	8	0	0
T317	0	54	0	0
T318	0	216	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1148	0	0
T3	146367	7	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	33	0	0
T301	0	14	0	0
T313	0	22	0	0
T314	0	16	0	0
T317	0	22	0	0
T318	0	229	0	0
T320	0	51	0	0
T321	0	6	0	0
T322	0	9	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1132	0	0
T3	146367	5	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	26	0	0
T301	0	13	0	0
T312	0	14	0	0
T313	0	16	0	0
T315	0	6	0	0
T316	0	6	0	0
T317	0	32	0	0
T318	0	221	0	0
T319	0	2	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1268	0	0
T3	146367	10	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	7	0	0
T300	0	14	0	0
T301	0	6	0	0
T304	0	4	0	0
T312	0	3	0	0
T313	0	10	0	0
T314	0	9	0	0
T315	0	7	0	0
T316	0	1	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1141	0	0
T3	146367	11	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	28	0	0
T301	0	15	0	0
T304	0	2	0	0
T312	0	4	0	0
T313	0	24	0	0
T314	0	12	0	0
T317	0	30	0	0
T318	0	208	0	0
T319	0	4	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4286	0	0
T3	146367	7	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	48	0	0
T301	0	13	0	0
T304	0	6	0	0
T312	0	11	0	0
T313	0	24	0	0
T314	0	14	0	0
T315	0	5	0	0
T316	0	2	0	0
T317	0	20	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4219	0	0
T3	146367	14	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	6	0	0
T300	0	33	0	0
T301	0	20	0	0
T304	0	1	0	0
T312	0	4	0	0
T313	0	31	0	0
T314	0	14	0	0
T315	0	4	0	0
T317	0	27	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4404	0	0
T3	146367	4	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	1	0	0
T300	0	40	0	0
T301	0	6	0	0
T304	0	4	0	0
T312	0	29	0	0
T313	0	25	0	0
T314	0	11	0	0
T315	0	9	0	0
T316	0	7	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4170	0	0
T3	146367	3	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	77	0	0
T301	0	21	0	0
T304	0	3	0	0
T312	0	32	0	0
T313	0	31	0	0
T314	0	1	0	0
T315	0	8	0	0
T316	0	2	0	0
T317	0	55	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4079	0	0
T3	146367	3	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	4	0	0
T300	0	29	0	0
T301	0	3	0	0
T304	0	5	0	0
T312	0	24	0	0
T313	0	15	0	0
T314	0	27	0	0
T315	0	1	0	0
T316	0	2	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4165	0	0
T3	146367	14	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	8	0	0
T300	0	54	0	0
T301	0	32	0	0
T304	0	6	0	0
T312	0	32	0	0
T313	0	20	0	0
T314	0	7	0	0
T315	0	3	0	0
T317	0	25	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4135	0	0
T3	146367	7	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	14	0	0
T300	0	77	0	0
T301	0	10	0	0
T304	0	3	0	0
T312	0	16	0	0
T313	0	24	0	0
T314	0	5	0	0
T315	0	9	0	0
T316	0	7	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4153	0	0
T3	146367	15	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	5	0	0
T300	0	28	0	0
T301	0	5	0	0
T312	0	9	0	0
T313	0	4	0	0
T314	0	17	0	0
T315	0	7	0	0
T316	0	4	0	0
T317	0	23	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	2289	0	0
T3	146367	13	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	21	0	0
T304	0	5	0	0
T312	0	10	0	0
T313	0	36	0	0
T314	0	14	0	0
T315	0	7	0	0
T316	0	3	0	0
T317	0	51	0	0
T318	0	235	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1636	0	0
T1	966072	0	0	0
T2	27699	0	0	0
T3	146367	10	0	0
T4	47188	0	0	0
T6	97121	8	0	0
T7	193647	13	0	0
T8	97125	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T28	0	21	0	0
T312	0	3	0	0
T313	0	76	0	0
T323	0	18	0	0
T324	0	22	0	0
T325	0	6	0	0
T326	0	24	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	3189	0	0
T3	146367	7	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	101	0	0
T301	0	16	0	0
T304	0	2	0	0
T312	0	73	0	0
T313	0	13	0	0
T314	0	17	0	0
T315	0	8	0	0
T316	0	1	0	0
T317	0	39	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1129	0	0
T3	146367	10	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	21	0	0
T301	0	5	0	0
T304	0	5	0	0
T312	0	8	0	0
T313	0	8	0	0
T314	0	7	0	0
T315	0	3	0	0
T317	0	59	0	0
T318	0	195	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	4456	0	0
T3	146367	7	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	176	0	0
T301	0	14	0	0
T304	0	3	0	0
T312	0	10	0	0
T313	0	7	0	0
T314	0	13	0	0
T315	0	8	0	0
T316	0	8	0	0
T317	0	42	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	5170	0	0
T3	146367	3	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	163	0	0
T301	0	7	0	0
T304	0	1	0	0
T312	0	150	0	0
T313	0	25	0	0
T314	0	8	0	0
T315	0	7	0	0
T316	0	4	0	0
T317	0	29	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	3537	0	0
T3	146367	15	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	3	0	0
T300	0	98	0	0
T301	0	14	0	0
T304	0	7	0	0
T312	0	28	0	0
T313	0	18	0	0
T314	0	14	0	0
T315	0	3	0	0
T317	0	23	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	3810	0	0
T3	146367	10	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	103	0	0
T301	0	12	0	0
T304	0	7	0	0
T312	0	38	0	0
T313	0	15	0	0
T314	0	10	0	0
T315	0	6	0	0
T317	0	48	0	0
T318	0	189	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1221	0	0
T3	146367	6	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	8	0	0
T300	0	5	0	0
T301	0	21	0	0
T304	0	2	0	0
T312	0	7	0	0
T313	0	29	0	0
T314	0	7	0	0
T315	0	3	0	0
T316	0	3	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1293	0	0
T3	146367	10	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T299	0	8	0	0
T300	0	18	0	0
T304	0	6	0	0
T312	0	5	0	0
T313	0	8	0	0
T314	0	2	0	0
T315	0	9	0	0
T317	0	44	0	0
T318	0	216	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1218	0	0
T3	146367	13	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	16	0	0
T301	0	9	0	0
T312	0	11	0	0
T314	0	2	0	0
T315	0	6	0	0
T317	0	19	0	0
T318	0	248	0	0
T319	0	2	0	0
T320	0	29	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1311	0	0
T3	146367	8	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	12	0	0
T301	0	5	0	0
T304	0	5	0	0
T312	0	10	0	0
T313	0	44	0	0
T314	0	8	0	0
T315	0	1	0	0
T316	0	6	0	0
T317	0	33	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1326	0	0
T3	146367	5	0	0
T4	47188	0	0	0
T9	13113	0	0	0
T10	889619	0	0	0
T11	221866	0	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T300	0	19	0	0
T304	0	8	0	0
T312	0	8	0	0
T313	0	3	0	0
T314	0	3	0	0
T315	0	9	0	0
T316	0	4	0	0
T317	0	26	0	0
T318	0	204	0	0