Module Definition
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Module : prim_reg_cdc_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.04 100.00 96.51 95.65 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb 83.33 100.00 66.67
tb.dut.u_reg.u_ulp_status_cdc.u_arb 90.16 92.00 86.05 82.61 100.00
tb.dut.u_reg.u_wkup_status_cdc.u_arb 90.16 92.00 86.05 82.61 100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb 97.17 100.00 93.02 95.65 100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_arb 97.17 100.00 93.02 95.65 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
83.33 100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
284 1 1
285 1 1
300 unreachable


Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
90.16 92.00
tb.dut.u_reg.u_ulp_status_cdc.u_arb

SCORELINE
90.16 92.00
tb.dut.u_reg.u_wkup_status_cdc.u_arb

SCORELINE
97.17 100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb

SCORELINE
97.17 100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS12266100.00
CONT_ASSIGN13611100.00
ALWAYS14066100.00
ALWAYS1561010100.00
CONT_ASSIGN18411100.00
ALWAYS1881919100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 1 1
130 1 1
133 1 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
211 1 1
212 1 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
MISSING_ELSE
229 1 1
244 1 1
245 1 1


Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
83.33 66.67
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT6,T7,T8
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.16 86.05
tb.dut.u_reg.u_ulp_status_cdc.u_arb

SCORECOND
90.16 86.05
tb.dut.u_reg.u_wkup_status_cdc.u_arb

SCORECOND
97.17 93.02
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb

SCORECOND
97.17 93.02
tb.dut.u_reg.u_key_intr_status_cdc.u_arb

TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT14,T19,T21
10CoveredT1,T2,T3
11CoveredT14,T15,T16

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT14,T15,T16

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T37
11CoveredT1,T5,T37

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T5,T37

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT1,T2,T3
10CoveredT1,T5,T37

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT14,T15,T16
10CoveredT1,T5,T37
11CoveredT1,T2,T3

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT6,T7,T8
11CoveredT14,T15,T16

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT1,T5,T37
10CoveredT6,T7,T8
11CoveredT1,T2,T3

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T19,T21

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT14,T19,T21
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT14,T15,T16
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT6,T7,T8

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT14,T15,T16
10CoveredT1,T2,T3
11CoveredT14,T15,T16

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT14,T15,T16

Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 112 2 2 100.00
IF 122 4 4 100.00
IF 140 4 4 100.00
IF 156 6 6 100.00
CASE 198 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 112 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 122 if ((!rst_dst_ni)) -2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T1,T5,T37
0 0 1 Covered T1,T5,T37
0 0 0 Covered T6,T7,T8


LineNo. Expression -1-: 140 if ((!rst_dst_ni)) -2-: 142 if (gen_wr_req.dst_lat_d) -3-: 144 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T1,T2,T3
0 0 1 Covered T14,T19,T21
0 0 0 Covered T6,T7,T8


LineNo. Expression -1-: 156 if ((!rst_dst_ni)) -2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 164 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T6,T7,T8
0 1 - - - Covered T1,T2,T4
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T14,T15,T16
0 0 0 0 1 Covered T14,T19,T21
0 0 0 0 0 Covered T6,T7,T8


LineNo. Expression -1-: 198 case (gen_wr_req.state_q) -2-: 201 if (gen_wr_req.dst_req) -3-: 205 if (dst_update) -4-: 208 if ((dst_qs_o != dst_qs_i)) -5-: 218 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T14,T15,T16
StIdle 0 0 1 - Covered T14,T19,T21
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T1,T2,T4
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Module : prim_reg_cdc_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 32214172 1846 0 3684
gen_wr_req.HwIdSelCheck_A 32214172 1967 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32214172 1846 0 3684
T14 2166 5 0 2
T15 2058 1 0 3
T16 117920 20 0 4
T17 5916 1 0 4
T18 18552 2 0 2
T19 668 3 0 1
T20 10025 2 0 1
T21 0 3 0 0
T22 0 1 0 0
T23 0 1 0 0
T29 980 0 0 2
T30 4476 0 0 2
T31 1340 0 0 2
T32 1221 0 0 3
T33 2092 0 0 4
T34 1608 0 0 4
T42 0 5 0 0
T43 0 21 0 0
T44 0 3 0 0
T45 0 4 0 0
T46 0 5 0 0
T47 0 2 0 0
T48 0 5 0 0
T51 0 1 0 0
T53 0 16 0 0
T55 940 0 0 2
T60 0 2 0 0
T61 0 1 0 0
T62 1472 0 0 2
T63 1044 0 0 2

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32214172 1967 0 0
T14 2166 6 0 0
T15 2058 1 0 0
T16 117920 20 0 0
T17 5916 1 0 0
T18 18552 2 0 0
T19 668 5 0 0
T20 10025 2 0 0
T21 0 4 0 0
T22 0 1 0 0
T23 0 1 0 0
T29 980 0 0 0
T30 4476 0 0 0
T31 1340 0 0 0
T32 1221 0 0 0
T33 2092 0 0 0
T34 1608 0 0 0
T42 0 5 0 0
T43 0 21 0 0
T44 0 3 0 0
T45 0 5 0 0
T46 0 8 0 0
T47 0 4 0 0
T48 0 7 0 0
T51 0 1 0 0
T53 0 16 0 0
T55 940 0 0 0
T60 0 2 0 0
T61 0 1 0 0
T62 1472 0 0 0
T63 1044 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%