Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1751

1

T15

8

T17

1

T19

22

auto[1]

606

1

T15

4

T19

3

T21

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1734

1

T15

2

T17

1

T19

20

auto[1]

623

1

T15

10

T19

5

T20

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1773

1

T15

12

T19

14

T20

42

auto[1]

584

1

T17

1

T19

11

T20

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1761

1

T15

4

T17

1

T19

22

auto[1]

596

1

T15

8

T19

3

T51

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2170

1

T15

12

T17

1

T19

25

auto[1]

187

1

T20

18

T65

2

T66

9

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2147

1

T15

12

T17

1

T19

25

auto[1]

210

1

T20

6

T65

2

T66

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2167

1

T15

12

T17

1

T19

25

auto[1]

190

1

T20

12

T66

7

T64

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2167

1

T15

12

T17

1

T19

25

auto[1]

190

1

T20

3

T66

4

T266

8

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2166

1

T15

12

T17

1

T19

25

auto[1]

191

1

T65

10

T66

6

T266

10

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1749

1

T15

6

T17

1

T19

5

auto[1]

608

1

T15

6

T19

20

T20

12

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

838

1

T15

12

T17

1

T19

25

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

65

1

T267

5

T268

8

T336

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T65

8

T64

5

T268

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T115

1

T339

3

-

-

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

80

1

T64

12

T114

1

T345

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T267

3

T344

2

T342

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

17

1

T266

8

T341

3

T346

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T66

4

T329

3

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46

1

T283

2

T281

3

T345

16

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T20

9

T66

5

T267

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T343

5

T347

3

T348

18

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T182

2

T349

1

T329

12

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T20

3

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

2

1

T336

1

T270

1

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T64

7

T268

1

T350

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T20

6

T117

6

T330

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

21

1

T266

2

T270

4

T330

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T65

2

T93

12

T351

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

18

1

T329

12

T352

5

T353

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T354

3

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

21

1

T349

1

T343

4

T348

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T336

2

T116

4

T183

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T66

2

T64

3

T330

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

6

1

T329

5

T355

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

103

1

T66

2

T64

3

T95

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

109

1

T19

11

T20

3

T22

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

47

1

T22

12

T70

3

T241

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

88

1

T65

2

T66

5

T133

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

59

1

T64

7

T83

1

T345

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

55

1

T15

2

T59

5

T268

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T19

3

T51

1

T71

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T17

1

T20

6

T80

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

57

1

T64

12

T95

2

T114

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

56

1

T19

6

T21

4

T24

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T59

1

T70

2

T339

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T70

2

T266

2

T83

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T270

4

T345

10

T349

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T51

3

T71

1

T83

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T175

1

T118

1

T121

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

101

1

T266

8

T327

11

T336

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

54

1

T65

8

T71

7

T83

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

78

1

T20

9

T267

5

T269

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T15

4

T80

1

T113

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T15

6

T71

2

T64

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

52

1

T255

3

T356

4

T326

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T83

2

T167

1

T357

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T83

2

T113

2

T283

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

74

1

T19

5

T69

5

T66

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T21

1

T77

2

T80

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T51

5

T69

2

T71

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T21

1

T358

1

T241

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T83

4

T133

1

T270

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T326

2

T359

1

T184

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T71

1

T328

1

T133

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T359

1

T91

1

T335

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded