Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T34

8

T36

9

T324

11

auto[1]

1036

1

T34

12

T36

11

T324

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

511

1

T34

5

T36

6

T324

4

from_0to1

506

1

T34

4

T36

6

T324

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T34

12

T36

17

T324

11

auto[1]

1069

1

T34

8

T36

3

T324

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T34

10

T36

12

T324

6

auto[1]

1052

1

T34

10

T36

8

T324

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T34

1

T36

4

T324

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T36

1

T108

1

T101

4

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T51

3

T108

1

T59

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T324

1

T51

1

T108

2

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T36

1

T51

2

T101

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T34

1

T324

1

T108

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T34

2

T51

1

T101

2

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T324

3

T101

1

T59

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T34

1

T108

1

T101

2

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T36

1

T324

1

T101

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T51

1

T108

1

T101

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T34

3

T324

1

T51

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T36

2

T324

1

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T34

1

T36

1

T101

3

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T36

1

T51

1

T108

2

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T36

1

T51

1

T101

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T34

7

T36

13

T324

7

auto[1]

1034

1

T34

13

T36

7

T324

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T34

6

T36

6

T324

6

from_0to1

505

1

T34

5

T36

6

T324

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T34

10

T36

13

T324

10

auto[1]

1033

1

T34

10

T36

7

T324

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T34

12

T36

15

T324

9

auto[1]

1036

1

T34

8

T36

5

T324

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

79

1

T34

1

T36

1

T101

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T36

1

T324

2

T51

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T286

1

T70

1

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T34

2

T36

1

T324

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T34

2

T36

2

T324

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T108

1

T70

1

T71

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T34

1

T36

1

T324

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T36

1

T101

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T34

1

T36

2

T324

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T34

1

T324

1

T108

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T36

1

T51

1

T108

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T34

1

T324

1

T51

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T34

1

T36

1

T324

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T324

2

T101

2

T286

2

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T34

1

T36

1

T51

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T101

2

T286

1

T70

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T34

10

T36

8

T324

9

auto[1]

1071

1

T34

10

T36

12

T324

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T34

4

T36

6

T324

4

from_0to1

509

1

T34

5

T36

6

T324

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T34

10

T36

9

T324

7

auto[1]

1076

1

T34

10

T36

11

T324

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T34

8

T36

10

T324

14

auto[1]

1040

1

T34

12

T36

10

T324

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T34

2

T36

2

T286

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T51

1

T101

3

T70

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T36

1

T324

3

T108

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T34

1

T36

1

T108

3

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T34

1

T324

1

T51

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T51

1

T108

2

T101

2

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T34

1

T108

1

T286

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T34

2

T36

2

T101

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T36

1

T51

3

T101

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T51

1

T108

2

T101

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T324

1

T51

1

T108

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T34

1

T36

1

T101

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T34

1

T36

1

T51

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T36

1

T324

1

T51

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T36

1

T324

1

T286

3

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T36

1

T108

1

T101

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1024

1

T34

9

T36

11

T324

12

auto[1]

1073

1

T34

11

T36

9

T324

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T34

3

T36

5

T324

5

from_0to1

527

1

T34

3

T36

6

T324

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1038

1

T34

10

T36

13

T324

15

auto[1]

1059

1

T34

10

T36

7

T324

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T34

6

T36

12

T324

12

auto[1]

1032

1

T34

14

T36

8

T324

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T324

1

T101

2

T286

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T34

2

T36

1

T324

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T36

2

T51

2

T101

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T36

1

T51

1

T286

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T324

2

T108

1

T101

2

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T36

1

T324

1

T51

2

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T34

1

T36

1

T101

3

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T108

1

T101

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T324

1

T101

1

T286

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T36

1

T324

2

T51

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T34

1

T108

2

T101

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T51

1

T108

1

T101

2

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T34

1

T36

2

T324

2

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T51

2

T101

1

T70

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T101

1

T286

1

T59

2

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T34

1

T36

2

T324

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T34

10

T36

5

T324

7

auto[1]

1074

1

T34

10

T36

15

T324

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

492

1

T34

6

T36

6

T324

4

from_0to1

491

1

T34

7

T36

7

T324

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T34

10

T36

15

T324

5

auto[1]

1050

1

T34

10

T36

5

T324

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T34

9

T36

14

T324

11

auto[1]

1020

1

T34

11

T36

6

T324

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T36

1

T51

2

T108

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T34

1

T51

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T34

2

T51

1

T70

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T108

1

T286

1

T59

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T34

1

T36

1

T101

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T34

2

T51

1

T286

2

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T324

1

T51

2

T108

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T51

2

T108

1

T101

2

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T34

1

T36

2

T324

2

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T36

2

T51

1

T108

2

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T36

1

T324

2

T51

2

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T34

2

T101

2

T286

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T34

1

T36

3

T101

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T36

1

T324

1

T51

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T34

2

T36

2

T324

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T34

1

T324

2

T108

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T34

11

T36

8

T324

9

auto[1]

1078

1

T34

9

T36

12

T324

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

491

1

T34

5

T36

4

T324

4

from_0to1

491

1

T34

5

T36

4

T324

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T34

12

T36

13

T324

4

auto[1]

1046

1

T34

8

T36

7

T324

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

987

1

T34

9

T36

7

T324

6

auto[1]

1110

1

T34

11

T36

13

T324

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T34

1

T36

1

T101

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T324

1

T51

1

T101

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T108

2

T101

2

T70

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T34

1

T36

1

T108

2

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T51

1

T101

1

T286

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T34

1

T51

3

T101

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T34

1

T324

1

T101

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T324

2

T108

1

T101

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T34

1

T36

1

T101

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T34

1

T36

1

T51

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T51

1

T101

2

T286

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T34

1

T324

3

T51

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T34

2

T101

1

T59

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T34

1

T36

3

T108

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T36

1

T108

2

T286

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T324

2

T51

1

T108

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T34

11

T36

14

T324

12

auto[1]

1063

1

T34

9

T36

6

T324

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

523

1

T34

4

T36

4

T324

4

from_0to1

525

1

T34

5

T36

5

T324

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1011

1

T34

13

T36

12

T324

11

auto[1]

1086

1

T34

7

T36

8

T324

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T34

9

T36

10

T324

9

auto[1]

1044

1

T34

11

T36

10

T324

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T36

3

T324

1

T51

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T34

1

T286

2

T59

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T51

1

T108

1

T101

5

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T36

1

T324

1

T108

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T34

2

T36

1

T101

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T324

2

T101

3

T286

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T34

1

T36

2

T51

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T51

2

T108

2

T101

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T34

1

T324

1

T51

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T34

1

T51

1

T108

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T51

1

T108

1

T101

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T34

1

T324

1

T51

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T34

1

T51

3

T70

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T36

1

T324

1

T108

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T36

1

T108

1

T101

3

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T34

1

T324

1

T51

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T34

8

T36

10

T324

10

auto[1]

1052

1

T34

12

T36

10

T324

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T34

5

T36

4

T324

4

from_0to1

514

1

T34

6

T36

4

T324

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T34

8

T36

8

T324

9

auto[1]

1060

1

T34

12

T36

12

T324

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1013

1

T34

13

T36

13

T324

6

auto[1]

1084

1

T34

7

T36

7

T324

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T101

1

T286

1

T59

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T324

1

T108

1

T59

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T34

2

T36

2

T51

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T51

1

T108

3

T101

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T51

1

T108

2

T101

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T34

2

T51

1

T286

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T36

2

T324

1

T108

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T34

1

T324

1

T108

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T34

1

T36

1

T324

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T324

1

T101

1

T70

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T34

2

T36

1

T324

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T101

3

T70

2

T369

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T34

2

T51

1

T101

3

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T324

2

T108

1

T101

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T34

1

T324

1

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T36

2

T51

2

T108

2