Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147315	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

112019

1

T6

11

T7

15

T8

88

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	133755	1			T6	16		T7	16		T8	30
values[0x0]	62483	1			T6	5		T7	4		T8	37
values[0x1]	63096	1			T6	6		T7	7		T8	82

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	119577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

139757

1

T6

16

T7

18

T8

130

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	844	1			T29	2		T3	6		T47	4
valid_sources[0x01]	709	1			T8	3		T25	1		T27	1
valid_sources[0x02]	882	1			T1	2		T3	10		T47	1
valid_sources[0x03]	768	1			T3	16		T4	18		T47	1
valid_sources[0x04]	686	1			T29	1		T3	2		T47	5
valid_sources[0x05]	1607	1			T2	1		T3	11		T47	1
valid_sources[0x06]	829	1			T2	1		T3	5		T9	19
valid_sources[0x07]	1842	1			T8	2		T1	1		T2	3
valid_sources[0x08]	1222	1			T8	1		T27	2		T2	1
valid_sources[0x09]	977	1			T2	2		T3	8		T4	16
valid_sources[0x0a]	999	1			T29	3		T2	1		T3	1
valid_sources[0x0b]	740	1			T29	3		T45	1		T47	3
valid_sources[0x0c]	1036	1			T8	1		T27	1		T29	1
valid_sources[0x0d]	769	1			T2	1		T3	24		T47	3
valid_sources[0x0e]	714	1			T2	1		T3	7		T47	3
valid_sources[0x0f]	743	1			T1	2		T3	7		T45	1
valid_sources[0x10]	879	1			T27	1		T3	3		T47	2
valid_sources[0x11]	786	1			T8	2		T1	1		T26	1
valid_sources[0x12]	788	1			T3	19		T47	1		T5	10
valid_sources[0x13]	1064	1			T1	1		T29	2		T2	2
valid_sources[0x14]	1214	1			T25	2		T29	2		T2	1
valid_sources[0x15]	692	1			T1	1		T2	1		T3	23
valid_sources[0x16]	1079	1			T1	1		T3	7		T47	1
valid_sources[0x17]	1228	1			T3	20		T9	26		T47	2
valid_sources[0x18]	1260	1			T1	3		T27	1		T2	1
valid_sources[0x19]	1119	1			T2	1		T3	2		T47	5
valid_sources[0x1a]	1069	1			T6	1		T2	2		T3	5
valid_sources[0x1b]	1125	1			T8	1		T2	1		T3	29
valid_sources[0x1c]	893	1			T7	2		T8	1		T9	23
valid_sources[0x1d]	1378	1			T3	18		T47	6		T5	15
valid_sources[0x1e]	2146	1			T2	2		T3	3		T9	64
valid_sources[0x1f]	912	1			T1	2		T29	3		T2	2
valid_sources[0x20]	1635	1			T6	1		T3	1		T47	4
valid_sources[0x21]	817	1			T26	1		T2	1		T3	12
valid_sources[0x22]	848	1			T26	1		T28	1		T3	6
valid_sources[0x23]	896	1			T6	1		T8	4		T29	1
valid_sources[0x24]	756	1			T27	1		T3	3		T9	5
valid_sources[0x25]	1052	1			T2	3		T3	6		T47	5
valid_sources[0x26]	899	1			T1	1		T27	1		T3	13
valid_sources[0x27]	1010	1			T26	1		T29	2		T2	1
valid_sources[0x28]	1697	1			T8	1		T29	2		T2	1
valid_sources[0x29]	650	1			T1	1		T2	3		T47	1
valid_sources[0x2a]	1061	1			T8	3		T29	1		T2	1
valid_sources[0x2b]	671	1			T8	1		T1	1		T3	3
valid_sources[0x2c]	934	1			T6	1		T8	3		T2	1
valid_sources[0x2d]	779	1			T29	1		T30	5		T2	1
valid_sources[0x2e]	901	1			T3	22		T9	74		T47	3
valid_sources[0x2f]	1431	1			T29	2		T3	15		T9	15
valid_sources[0x30]	981	1			T29	1		T3	2		T47	1
valid_sources[0x31]	1044	1			T2	3		T3	36		T44	1
valid_sources[0x32]	675	1			T3	1		T47	6		T67	15
valid_sources[0x33]	1425	1			T1	1		T47	4		T67	14
valid_sources[0x34]	1115	1			T2	1		T3	23		T4	8
valid_sources[0x35]	831	1			T6	1		T8	5		T25	1
valid_sources[0x36]	1399	1			T29	3		T2	3		T3	23
valid_sources[0x37]	768	1			T3	7		T47	2		T67	23
valid_sources[0x38]	804	1			T28	1		T29	1		T30	7
valid_sources[0x39]	802	1			T8	12		T27	1		T29	1
valid_sources[0x3a]	780	1			T1	1		T29	1		T2	3
valid_sources[0x3b]	720	1			T3	20		T5	8		T67	16
valid_sources[0x3c]	1687	1			T1	1		T28	1		T3	5
valid_sources[0x3d]	879	1			T7	1		T2	4		T47	1
valid_sources[0x3e]	683	1			T3	40		T9	9		T47	1
valid_sources[0x3f]	736	1			T25	1		T27	2		T2	1
valid_sources[0x40]	1867	1			T2	2		T3	2		T67	15
valid_sources[0x41]	1088	1			T3	30		T43	7		T47	4
valid_sources[0x42]	1725	1			T28	1		T2	1		T3	23
valid_sources[0x43]	723	1			T27	1		T29	2		T2	2
valid_sources[0x44]	957	1			T6	1		T1	3		T47	5
valid_sources[0x45]	860	1			T8	6		T30	1		T2	1
valid_sources[0x46]	848	1			T25	1		T2	2		T3	8
valid_sources[0x47]	1387	1			T27	1		T45	1		T47	1
valid_sources[0x48]	810	1			T3	2		T4	14		T47	1
valid_sources[0x49]	1937	1			T1	1		T28	1		T29	10
valid_sources[0x4a]	2107	1			T28	1		T3	8		T47	4
valid_sources[0x4b]	748	1			T1	1		T25	2		T2	1
valid_sources[0x4c]	722	1			T3	8		T67	19		T11	5
valid_sources[0x4d]	959	1			T8	2		T3	3		T9	34
valid_sources[0x4e]	1116	1			T28	2		T29	2		T2	3
valid_sources[0x4f]	760	1			T2	1		T9	6		T47	5
valid_sources[0x50]	731	1			T8	1		T29	2		T2	3
valid_sources[0x51]	811	1			T29	3		T3	11		T9	7
valid_sources[0x52]	1421	1			T2	2		T3	4		T47	3
valid_sources[0x53]	782	1			T26	3		T29	1		T2	1
valid_sources[0x54]	1144	1			T7	1		T2	1		T3	5
valid_sources[0x55]	934	1			T29	3		T2	1		T3	18
valid_sources[0x56]	936	1			T29	6		T2	1		T3	10
valid_sources[0x57]	1117	1			T6	1		T8	1		T3	7
valid_sources[0x58]	1519	1			T2	1		T3	4		T47	1
valid_sources[0x59]	1536	1			T29	3		T2	1		T3	20
valid_sources[0x5a]	1100	1			T8	1		T2	1		T3	3
valid_sources[0x5b]	852	1			T8	1		T29	2		T2	1
valid_sources[0x5c]	866	1			T25	5		T3	5		T9	55
valid_sources[0x5d]	1117	1			T7	1		T8	1		T1	2
valid_sources[0x5e]	1002	1			T29	1		T2	1		T3	31
valid_sources[0x5f]	947	1			T3	1		T4	17		T47	3
valid_sources[0x60]	814	1			T8	3		T1	1		T2	2
valid_sources[0x61]	974	1			T29	4		T2	2		T3	2
valid_sources[0x62]	594	1			T26	1		T29	3		T2	2
valid_sources[0x63]	955	1			T8	7		T3	13		T4	16
valid_sources[0x64]	947	1			T2	1		T3	5		T47	1
valid_sources[0x65]	1726	1			T2	1		T3	22		T9	9
valid_sources[0x66]	822	1			T8	2		T25	1		T3	2
valid_sources[0x67]	1273	1			T1	1		T29	2		T2	1
valid_sources[0x68]	797	1			T2	1		T3	8		T9	75
valid_sources[0x69]	934	1			T2	1		T3	8		T45	2
valid_sources[0x6a]	1141	1			T28	1		T3	19		T9	69
valid_sources[0x6b]	1084	1			T2	1		T47	4		T67	7
valid_sources[0x6c]	775	1			T47	2		T67	17		T68	21
valid_sources[0x6d]	888	1			T8	7		T1	4		T3	15
valid_sources[0x6e]	1024	1			T2	1		T3	6		T43	1
valid_sources[0x6f]	1370	1			T26	1		T2	1		T3	24
valid_sources[0x70]	847	1			T29	3		T2	2		T3	9
valid_sources[0x71]	827	1			T3	42		T4	3		T45	1
valid_sources[0x72]	766	1			T29	1		T3	1		T9	39
valid_sources[0x73]	839	1			T1	2		T25	2		T29	5
valid_sources[0x74]	965	1			T3	1		T45	1		T47	1
valid_sources[0x75]	2043	1			T2	3		T3	1		T4	2
valid_sources[0x76]	861	1			T28	1		T29	6		T2	1
valid_sources[0x77]	860	1			T1	1		T3	22		T4	7
valid_sources[0x78]	813	1			T29	1		T3	29		T9	15
valid_sources[0x79]	819	1			T1	1		T26	1		T29	1
valid_sources[0x7a]	1139	1			T29	5		T2	2		T3	10
valid_sources[0x7b]	925	1			T2	3		T3	16		T47	3
valid_sources[0x7c]	769	1			T3	12		T47	4		T67	14
valid_sources[0x7d]	897	1			T6	1		T2	1		T3	1
valid_sources[0x7e]	1296	1			T25	1		T5	6		T67	16
valid_sources[0x7f]	909	1			T1	2		T29	2		T2	1
valid_sources[0x80]	704	1			T28	1		T44	2		T47	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60866

1

T6

8

T7

10

T8

23

values[0x0]

all_enables

biggest_size

30162

1

T6

2

T7

1

T8

34

values[0x1]

all_enables

biggest_size

20991

1

T6

1

T7

4

T8

31