Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1086127076	9590	0	0
auto_block_debounce_ctl_rd_A	1086127076	2026	0	0
auto_block_out_ctl_rd_A	1086127076	2857	0	0
com_det_ctl_0_rd_A	1086127076	3903	0	0
com_det_ctl_1_rd_A	1086127076	4059	0	0
com_det_ctl_2_rd_A	1086127076	4199	0	0
com_det_ctl_3_rd_A	1086127076	4215	0	0
com_out_ctl_0_rd_A	1086127076	4556	0	0
com_out_ctl_1_rd_A	1086127076	4534	0	0
com_out_ctl_2_rd_A	1086127076	4714	0	0
com_out_ctl_3_rd_A	1086127076	4876	0	0
com_pre_det_ctl_0_rd_A	1086127076	1437	0	0
com_pre_det_ctl_1_rd_A	1086127076	1499	0	0
com_pre_det_ctl_2_rd_A	1086127076	1439	0	0
com_pre_det_ctl_3_rd_A	1086127076	1466	0	0
com_pre_sel_ctl_0_rd_A	1086127076	4677	0	0
com_pre_sel_ctl_1_rd_A	1086127076	5016	0	0
com_pre_sel_ctl_2_rd_A	1086127076	4787	0	0
com_pre_sel_ctl_3_rd_A	1086127076	4865	0	0
com_sel_ctl_0_rd_A	1086127076	4734	0	0
com_sel_ctl_1_rd_A	1086127076	4879	0	0
com_sel_ctl_2_rd_A	1086127076	4984	0	0
com_sel_ctl_3_rd_A	1086127076	5023	0	0
ec_rst_ctl_rd_A	1086127076	2506	0	0
intr_enable_rd_A	1086127076	2029	0	0
key_intr_ctl_rd_A	1086127076	4091	0	0
key_intr_debounce_ctl_rd_A	1086127076	1407	0	0
key_invert_ctl_rd_A	1086127076	6021	0	0
pin_allowed_ctl_rd_A	1086127076	6933	0	0
pin_out_ctl_rd_A	1086127076	5000	0	0
pin_out_value_rd_A	1086127076	5229	0	0
regwen_rd_A	1086127076	1628	0	0
ulp_ac_debounce_ctl_rd_A	1086127076	1476	0	0
ulp_ctl_rd_A	1086127076	1717	0	0
ulp_lid_debounce_ctl_rd_A	1086127076	1527	0	0
ulp_pwrb_debounce_ctl_rd_A	1086127076	1714	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	9590	0	0
T1	386397	0	0	0
T2	103907	0	0	0
T3	107221	8	0	0
T8	202099	276	0	0
T9	0	7	0	0
T10	0	4	0	0
T12	0	2	0	0
T25	194953	0	0	0
T26	179042	0	0	0
T27	51050	0	0	0
T28	48992	0	0	0
T29	203742	322	0	0
T30	199165	0	0	0
T42	0	4	0	0
T47	0	911	0	0
T85	0	4	0	0
T297	0	2	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	2026	0	0
T2	103907	0	0	0
T3	107221	35	0	0
T4	461320	0	0	0
T5	0	30	0	0
T9	275525	0	0	0
T12	0	1	0	0
T29	203742	9	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	60	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	52	0	0
T293	0	17	0	0
T294	0	158	0	0
T304	0	11	0	0
T305	0	90	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	2857	0	0
T2	103907	0	0	0
T3	107221	114	0	0
T4	461320	0	0	0
T5	0	8	0	0
T9	275525	0	0	0
T12	0	5	0	0
T29	203742	7	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	179	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	76	0	0
T68	0	3	0	0
T293	0	14	0	0
T304	0	40	0	0
T305	0	70	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	3903	0	0
T3	107221	70	0	0
T4	461320	0	0	0
T5	124873	19	0	0
T9	275525	0	0	0
T12	0	8	0	0
T31	199018	0	0	0
T42	0	45	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	86	0	0
T68	0	7	0	0
T293	0	6	0	0
T294	0	81	0	0
T304	0	7	0	0
T305	0	70	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4059	0	0
T3	107221	38	0	0
T4	461320	0	0	0
T5	124873	30	0	0
T9	275525	0	0	0
T12	0	11	0	0
T31	199018	0	0	0
T42	0	36	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	91	0	0
T68	0	5	0	0
T293	0	14	0	0
T294	0	87	0	0
T304	0	3	0	0
T305	0	97	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4199	0	0
T2	103907	0	0	0
T3	107221	30	0	0
T4	461320	0	0	0
T5	0	6	0	0
T9	275525	0	0	0
T12	0	9	0	0
T29	203742	6	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	24	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	99	0	0
T293	0	3	0	0
T294	0	91	0	0
T304	0	4	0	0
T305	0	121	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4215	0	0
T2	103907	0	0	0
T3	107221	33	0	0
T4	461320	0	0	0
T5	0	18	0	0
T9	275525	0	0	0
T12	0	2	0	0
T29	203742	9	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	41	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	130	0	0
T68	0	7	0	0
T293	0	15	0	0
T304	0	5	0	0
T305	0	69	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4556	0	0
T2	103907	0	0	0
T3	107221	62	0	0
T4	461320	0	0	0
T5	0	5	0	0
T9	275525	0	0	0
T12	0	7	0	0
T29	203742	1	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	91	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	98	0	0
T68	0	8	0	0
T293	0	22	0	0
T304	0	11	0	0
T305	0	83	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4534	0	0
T2	103907	0	0	0
T3	107221	64	0	0
T4	461320	0	0	0
T5	0	14	0	0
T9	275525	0	0	0
T12	0	8	0	0
T29	203742	8	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	95	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	91	0	0
T293	0	1	0	0
T294	0	103	0	0
T304	0	6	0	0
T305	0	103	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4714	0	0
T3	107221	86	0	0
T4	461320	0	0	0
T5	124873	16	0	0
T9	275525	0	0	0
T12	0	7	0	0
T31	199018	0	0	0
T42	0	200	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	84	0	0
T68	0	7	0	0
T293	0	3	0	0
T294	0	180	0	0
T304	0	3	0	0
T305	0	58	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4876	0	0
T2	103907	0	0	0
T3	107221	89	0	0
T4	461320	0	0	0
T5	0	22	0	0
T9	275525	0	0	0
T12	0	15	0	0
T29	203742	6	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	93	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	52	0	0
T293	0	9	0	0
T294	0	166	0	0
T304	0	3	0	0
T305	0	54	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1437	0	0
T2	103907	0	0	0
T3	107221	30	0	0
T4	461320	0	0	0
T5	0	23	0	0
T9	275525	0	0	0
T12	0	15	0	0
T29	203742	12	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	26	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	90	0	0
T293	0	17	0	0
T294	0	67	0	0
T296	0	14	0	0
T305	0	85	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1499	0	0
T2	103907	0	0	0
T3	107221	41	0	0
T4	461320	0	0	0
T5	0	2	0	0
T9	275525	0	0	0
T12	0	9	0	0
T29	203742	6	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	36	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	77	0	0
T293	0	3	0	0
T294	0	76	0	0
T304	0	2	0	0
T305	0	113	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1439	0	0
T3	107221	29	0	0
T4	461320	0	0	0
T5	124873	7	0	0
T9	275525	0	0	0
T12	0	3	0	0
T31	199018	0	0	0
T42	0	38	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	91	0	0
T293	0	13	0	0
T294	0	60	0	0
T296	0	23	0	0
T304	0	7	0	0
T305	0	87	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1466	0	0
T2	103907	0	0	0
T3	107221	54	0	0
T4	461320	0	0	0
T5	0	15	0	0
T9	275525	0	0	0
T12	0	5	0	0
T29	203742	13	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	34	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	108	0	0
T293	0	5	0	0
T294	0	76	0	0
T304	0	2	0	0
T305	0	132	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4677	0	0
T2	103907	0	0	0
T3	107221	97	0	0
T4	461320	0	0	0
T5	0	10	0	0
T9	275525	0	0	0
T12	0	4	0	0
T29	203742	15	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	102	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	82	0	0
T68	0	2	0	0
T294	0	183	0	0
T304	0	25	0	0
T305	0	85	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	5016	0	0
T2	103907	0	0	0
T3	107221	135	0	0
T4	461320	0	0	0
T5	0	12	0	0
T9	275525	0	0	0
T12	0	6	0	0
T29	203742	4	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	199	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	84	0	0
T68	0	6	0	0
T293	0	11	0	0
T304	0	19	0	0
T305	0	83	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4787	0	0
T2	103907	0	0	0
T3	107221	75	0	0
T4	461320	0	0	0
T5	0	27	0	0
T9	275525	0	0	0
T12	0	13	0	0
T29	203742	23	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	91	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	94	0	0
T68	0	7	0	0
T294	0	153	0	0
T304	0	2	0	0
T305	0	102	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4865	0	0
T3	107221	113	0	0
T4	461320	0	0	0
T5	124873	21	0	0
T9	275525	0	0	0
T12	0	7	0	0
T31	199018	0	0	0
T42	0	119	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	92	0	0
T293	0	8	0	0
T294	0	251	0	0
T298	0	188	0	0
T305	0	87	0	0
T306	0	5	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4734	0	0
T3	107221	86	0	0
T4	461320	0	0	0
T5	124873	19	0	0
T9	275525	0	0	0
T12	0	6	0	0
T31	199018	0	0	0
T42	0	138	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	89	0	0
T68	0	3	0	0
T293	0	9	0	0
T294	0	263	0	0
T304	0	23	0	0
T305	0	58	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4879	0	0
T2	103907	0	0	0
T3	107221	66	0	0
T4	461320	0	0	0
T5	0	23	0	0
T9	275525	0	0	0
T12	0	8	0	0
T29	203742	4	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	177	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	80	0	0
T68	0	4	0	0
T293	0	3	0	0
T304	0	8	0	0
T305	0	115	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4984	0	0
T2	103907	0	0	0
T3	107221	92	0	0
T4	461320	0	0	0
T5	0	33	0	0
T9	275525	0	0	0
T12	0	5	0	0
T29	203742	9	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	156	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	72	0	0
T293	0	16	0	0
T294	0	252	0	0
T304	0	7	0	0
T305	0	67	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	5023	0	0
T3	107221	99	0	0
T4	461320	0	0	0
T5	124873	22	0	0
T9	275525	0	0	0
T12	0	9	0	0
T31	199018	0	0	0
T42	0	112	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	76	0	0
T68	0	2	0	0
T293	0	2	0	0
T294	0	236	0	0
T304	0	3	0	0
T305	0	78	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	2506	0	0
T2	103907	0	0	0
T3	107221	27	0	0
T4	461320	0	0	0
T5	0	35	0	0
T9	275525	0	0	0
T12	0	5	0	0
T29	203742	17	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	45	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	87	0	0
T68	0	8	0	0
T293	0	9	0	0
T304	0	3	0	0
T305	0	113	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	2029	0	0
T1	386397	0	0	0
T3	0	45	0	0
T5	0	45	0	0
T6	193214	7	0	0
T7	187189	0	0	0
T8	202099	0	0	0
T12	0	6	0	0
T25	194953	0	0	0
T26	179042	0	0	0
T27	51050	0	0	0
T28	48992	0	0	0
T29	203742	7	0	0
T30	199165	0	0	0
T42	0	40	0	0
T67	0	150	0	0
T68	0	1	0	0
T304	0	2	0	0
T307	0	22	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	4091	0	0
T2	103907	0	0	0
T3	107221	349	0	0
T4	461320	0	0	0
T5	0	11	0	0
T9	275525	0	0	0
T12	0	3	0	0
T29	203742	12	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	125	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	87	0	0
T293	0	13	0	0
T294	0	772	0	0
T304	0	57	0	0
T305	0	131	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1407	0	0
T3	107221	52	0	0
T4	461320	0	0	0
T5	124873	3	0	0
T9	275525	0	0	0
T12	0	6	0	0
T31	199018	0	0	0
T42	0	45	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	72	0	0
T68	0	3	0	0
T293	0	11	0	0
T294	0	50	0	0
T304	0	2	0	0
T305	0	85	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	6021	0	0
T2	103907	0	0	0
T3	107221	278	0	0
T4	461320	0	0	0
T5	0	47	0	0
T9	275525	0	0	0
T12	0	14	0	0
T29	203742	5	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	214	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	95	0	0
T293	0	11	0	0
T294	0	522	0	0
T304	0	3	0	0
T305	0	99	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	6933	0	0
T2	103907	0	0	0
T3	107221	216	0	0
T4	461320	0	0	0
T5	0	32	0	0
T9	275525	0	0	0
T12	0	9	0	0
T29	203742	11	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	297	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	88	0	0
T68	0	1	0	0
T293	0	7	0	0
T304	0	69	0	0
T305	0	82	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	5000	0	0
T3	107221	232	0	0
T4	461320	0	0	0
T5	124873	46	0	0
T9	275525	0	0	0
T12	0	2	0	0
T31	199018	0	0	0
T42	0	220	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	101	0	0
T68	0	3	0	0
T293	0	17	0	0
T294	0	313	0	0
T304	0	24	0	0
T305	0	98	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	5229	0	0
T2	103907	0	0	0
T3	107221	197	0	0
T4	461320	0	0	0
T5	0	33	0	0
T9	275525	0	0	0
T12	0	2	0	0
T29	203742	9	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	102	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	109	0	0
T293	0	13	0	0
T294	0	389	0	0
T304	0	38	0	0
T305	0	65	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1628	0	0
T3	107221	23	0	0
T4	461320	0	0	0
T5	124873	12	0	0
T9	275525	0	0	0
T12	0	3	0	0
T31	199018	0	0	0
T42	0	28	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	153	0	0
T294	0	91	0	0
T296	0	4	0	0
T298	0	84	0	0
T304	0	10	0	0
T305	0	74	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1476	0	0
T2	103907	0	0	0
T3	107221	28	0	0
T4	461320	0	0	0
T5	0	22	0	0
T9	275525	0	0	0
T12	0	1	0	0
T29	203742	9	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	19	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	108	0	0
T68	0	8	0	0
T293	0	12	0	0
T304	0	8	0	0
T305	0	80	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1717	0	0
T2	103907	0	0	0
T3	107221	45	0	0
T4	461320	0	0	0
T5	0	17	0	0
T9	275525	0	0	0
T12	0	6	0	0
T29	203742	9	0	0
T30	199165	0	0	0
T31	199018	0	0	0
T42	0	81	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T67	0	103	0	0
T68	0	9	0	0
T294	0	94	0	0
T304	0	6	0	0
T305	0	73	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1527	0	0
T3	107221	61	0	0
T4	461320	0	0	0
T5	124873	19	0	0
T9	275525	0	0	0
T12	0	6	0	0
T31	199018	0	0	0
T42	0	42	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	110	0	0
T68	0	4	0	0
T294	0	80	0	0
T296	0	4	0	0
T298	0	69	0	0
T305	0	77	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086127076	1714	0	0
T3	107221	38	0	0
T4	461320	0	0	0
T5	124873	18	0	0
T9	275525	0	0	0
T12	0	13	0	0
T31	199018	0	0	0
T42	0	49	0	0
T43	22952	0	0	0
T44	195203	0	0	0
T45	48952	0	0	0
T46	40974	0	0	0
T47	52471	0	0	0
T67	0	76	0	0
T293	0	12	0	0
T294	0	72	0	0
T298	0	86	0	0
T304	0	4	0	0
T305	0	123	0	0