SYSRST_CTRL Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.490s	2.109ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.480s	2.447ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	4.460s	2.162ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.980s	2.506ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	11.390s	4.025ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.290s	2.039ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.725m	28.018ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	10.420s	2.754ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.640s	2.110ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.290s	2.039ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	10.420s	2.754ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	7.757m	174.896ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	10.327m	241.979ms	91	100	91.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	22.051m	511.894ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	52.170s	214.671ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.760s	2.513ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.700s	2.242ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	13.390s	4.939ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	8.120s	2.612ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	4.436m	1.111s	46	50	92.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	43.500s	35.061ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	12.550m	265.948ms	50	50	100.00
V2	alert_test	sysrst_ctrl_alert_test	6.250s	2.013ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.260s	2.009ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.590s	2.120ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.590s	2.120ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	11.390s	4.025ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.290s	2.039ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	10.420s	2.754ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	39.360s	10.201ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	11.390s	4.025ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.290s	2.039ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	10.420s	2.754ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	39.360s	10.201ms	20	20	100.00
V2		TOTAL			679	692	98.12
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.735m	42.021ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.309m	42.390ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.309m	42.390ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	4.128m	995.970ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			915	932	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	98.99	96.40	100.00	98.08	98.36	99.91	93.77

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 6 failures:

Test sysrst_ctrl_ultra_low_pwr has 4 failures.

1.sysrst_ctrl_ultra_low_pwr.112661567250663126516482591875599163321602382280832735520398439564027814597726
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2800916414 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 4043416414 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4043416414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.sysrst_ctrl_ultra_low_pwr.42116121181684747631994608839553503388006722749128352202875671192820883233623
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 5482103206 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 7009603206 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 7009603206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

8.sysrst_ctrl_stress_all_with_rand_reset.49160179311088795139891305466987573608615515719215062909068715551547582471484
Line 571, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8631106625 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 9083606625 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 9083606625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.sysrst_ctrl_stress_all_with_rand_reset.6166326265073547654330273783098262466684708198532140538091226781200692877867
Line 687, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 37738717650 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 37836217650 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 38931338791 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 38931453378 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 38946047595 ps: (cip_base_vseq.sv:706) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 4 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 4 failures.

47.sysrst_ctrl_combo_detect_with_pre_cond.46548966405148990164402854950915719712012357672684749809343539282929317240677
Line 642, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 87091380164 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 87091380164 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 87091380164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

54.sysrst_ctrl_combo_detect_with_pre_cond.33218027597752768997698492721402635135150879613172706737962251149168714433139
Line 609, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 51673040374 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 51673040374 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 51673040374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(10) vs exp(5) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

11.sysrst_ctrl_combo_detect_with_pre_cond.56373552133832595672915017906908512602849589165412252393662378607983696991898
Line 573, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 15883728811 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(10) vs exp(5) +/-4
  UVM_INFO @ 15888728811 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
  UVM_INFO @ 16048728811 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 16068728811 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 26174586701 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x24

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

19.sysrst_ctrl_stress_all_with_rand_reset.54373357090607390495595435972650031499740145900932537959573084656987487085387
Line 656, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28543693758 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 28748451129 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_override_vseq
  UVM_INFO @ 30743671356 ps: (sysrst_ctrl_pin_override_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Starting the body from pin_override_vseq
  UVM_INFO @ 31255307208 ps: (cip_base_vseq.sv:706) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Finished run 8/10 w/o reset

UVM_FATAL (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:247) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] time out waiting for bat_disable == * has 1 failures:
- Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.
  - 36.sysrst_ctrl_combo_detect_with_pre_cond.102783218156951997780371362051521796955102353659641913356949321523499779693986
    Line 626, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
```
  UVM_FATAL @ 91136816353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:247) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] time out waiting for bat_disable == 1
  UVM_INFO @ 91136816353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 45.sysrst_ctrl_stress_all_with_rand_reset.111117901757407856461841769789334037550030367731423274808634706496756829682365
    Line 642, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 86670289379 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 86670289379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

58.sysrst_ctrl_combo_detect_with_pre_cond.37094839471673279330078229789169207902740281378778200874314735948070787026288
Line 683, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 152472771468 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 152472771468 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 152472771468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

74.sysrst_ctrl_combo_detect_with_pre_cond.37496075344392156185871932647715925893762875041301303309407446564329652333857
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13243581888 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 13463668603 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
  UVM_INFO @ 13463668603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

95.sysrst_ctrl_combo_detect_with_pre_cond.102371251817483080906552765365472447456082997051426850888580866051857421502024
Line 605, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 52463483355 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4
  UVM_ERROR @ 52463483355 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 52463483355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---