Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T26,T47,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T26,T47,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T26,T47,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T47,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T26,T47,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T47,T8
0	1	Covered	T111,T114
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T47,T14
0	1	Covered	T26,T47,T8
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T26,T47,T14
1	-	Covered	T26,T47,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T47,T8
DetectSt	168	Covered	T26,T47,T8
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T26,T47,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T47,T8
DebounceSt->IdleSt	163	Covered	T47,T8,T19
DetectSt->IdleSt	186	Covered	T111,T114
DetectSt->StableSt	191	Covered	T26,T47,T8
IdleSt->DebounceSt	148	Covered	T26,T47,T8
StableSt->IdleSt	206	Covered	T26,T47,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T47,T8
0	1	Covered	T26,T47,T8
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T47,T8
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T47,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T47,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T8,T19
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T47,T8
DetectSt	-	-	-	-	1	-	-	Covered	T111,T114
DetectSt	-	-	-	-	0	1	-	Covered	T26,T47,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T26,T47,T8
StableSt	-	-	-	-	-	-	0	Covered	T26,T47,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	257	0	0
CntIncr_A	6011137	230124	0	0
CntNoWrap_A	6011137	5357634	0	0
DetectStDropOut_A	6011137	2	0	0
DetectedOut_A	6011137	769	0	0
DetectedPulseOut_A	6011137	113	0	0
DisabledIdleSt_A	6011137	5121586	0	0
DisabledNoDetection_A	6011137	5123861	0	0
EnterDebounceSt_A	6011137	142	0	0
EnterDetectSt_A	6011137	115	0	0
EnterStableSt_A	6011137	113	0	0
PulseIsPulse_A	6011137	113	0	0
StayInStableSt	6011137	656	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6011137	6899	0	0
gen_low_level_sva.LowLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	112	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	257	0	0
T6	36286	0	0	0
T8	0	3	0	0
T14	0	2	0	0
T18	0	2	0	0
T19	0	1	0	0
T26	777	2	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	3	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	4	0	0
T60	755	0	0	0
T95	0	3	0	0
T96	0	2	0	0
T97	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	230124	0	0
T6	36286	0	0	0
T8	0	34	0	0
T14	0	29	0	0
T18	0	74	0	0
T19	0	54	0	0
T26	777	100	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	118	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	57819	0	0
T60	755	0	0	0
T95	0	131	0	0
T96	0	17	0	0
T97	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357634	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	374	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2	0	0
T111	127942	1	0	0
T114	0	1	0	0
T122	521	0	0	0
T123	1184	0	0	0
T124	28465	0	0	0
T125	526	0	0	0
T126	17782	0	0	0
T127	17827	0	0	0
T128	19291	0	0	0
T129	492	0	0	0
T130	656	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	769	0	0
T6	36286	0	0	0
T8	0	1	0	0
T14	0	11	0	0
T18	0	5	0	0
T26	777	3	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	6	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	17	0	0
T60	755	0	0	0
T95	0	11	0	0
T96	0	8	0	0
T97	0	20	0	0
T131	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	113	0	0
T6	36286	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T26	777	1	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	1	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	2	0	0
T60	755	0	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	2	0	0
T131	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5121586	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	241	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5123861	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	241	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	142	0	0
T6	36286	0	0	0
T8	0	2	0	0
T14	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T26	777	1	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	2	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	2	0	0
T60	755	0	0	0
T95	0	2	0	0
T96	0	1	0	0
T97	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	115	0	0
T6	36286	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T26	777	1	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	1	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	2	0	0
T60	755	0	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	2	0	0
T131	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	113	0	0
T6	36286	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T26	777	1	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	1	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	2	0	0
T60	755	0	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	2	0	0
T131	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	113	0	0
T6	36286	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T26	777	1	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	1	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	2	0	0
T60	755	0	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	2	0	0
T131	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	656	0	0
T6	36286	0	0	0
T14	0	10	0	0
T18	0	4	0	0
T26	777	2	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	5	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	15	0	0
T60	755	0	0	0
T95	0	10	0	0
T96	0	7	0	0
T97	0	18	0	0
T131	0	9	0	0
T132	0	9	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	6899	0	0
T1	6250	30	0	0
T2	751	1	0	0
T3	18039	12	0	0
T4	10366	12	0	0
T5	15041	12	0	0
T23	408	0	0	0
T24	493	8	0	0
T25	1305	4	0	0
T26	777	3	0	0
T27	10053	30	0	0
T28	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	112	0	0
T6	36286	0	0	0
T8	0	1	0	0
T18	0	1	0	0
T26	777	1	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	1	0	0
T48	30444	0	0	0
T56	10964	0	0	0
T57	0	2	0	0
T60	755	0	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	2	0	0
T131	0	1	0	0
T132	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T7,T14,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T7,T14,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T18,T19,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T18
1	0	Covered	T5,T1,T2
1	1	Covered	T7,T14,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T22
0	1	Covered	T93,T94,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T22
0	1	Unreachable
1	0	Covered	T18,T19,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T14,T18
DetectSt	168	Covered	T18,T19,T22
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T18,T19,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T19,T22
DebounceSt->IdleSt	163	Covered	T7,T14,T18
DetectSt->IdleSt	186	Covered	T93,T94,T92
DetectSt->StableSt	191	Covered	T18,T19,T22
IdleSt->DebounceSt	148	Covered	T7,T14,T18
StableSt->IdleSt	206	Covered	T18,T19,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T14,T18
0	1	Covered	T7,T14,T18
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T22
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T14,T18
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T19,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T18,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T14,T18
DetectSt	-	-	-	-	1	-	-	Covered	T93,T94,T92
DetectSt	-	-	-	-	0	1	-	Covered	T18,T19,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T19,T22
StableSt	-	-	-	-	-	-	0	Covered	T18,T19,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	183	0	0
CntIncr_A	6011137	153234	0	0
CntNoWrap_A	6011137	5357708	0	0
DetectStDropOut_A	6011137	9	0	0
DetectedOut_A	6011137	84013	0	0
DetectedPulseOut_A	6011137	64	0	0
DisabledIdleSt_A	6011137	4162662	0	0
DisabledNoDetection_A	6011137	4164984	0	0
EnterDebounceSt_A	6011137	111	0	0
EnterDetectSt_A	6011137	73	0	0
EnterStableSt_A	6011137	64	0	0
PulseIsPulse_A	6011137	64	0	0
StayInStableSt	6011137	83949	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6011137	6899	0	0
gen_low_level_sva.LowLevelEvent_A	6011137	5360213	0	0
gen_sticky_sva.StableStDropOut_A	6011137	837790	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	183	0	0
T7	116381	2	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T14	0	2	0	0
T18	0	5	0	0
T19	0	2	0	0
T22	0	4	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	5	0	0
T37	0	6	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	153234	0	0
T7	116381	24	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T14	0	78	0	0
T18	0	15643	0	0
T19	0	70	0	0
T22	0	116	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	80	0	0
T37	0	261	0	0
T38	0	59	0	0
T39	0	150	0	0
T40	0	194	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357708	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	9	0	0
T92	0	2	0	0
T93	10707	1	0	0
T94	0	2	0	0
T107	26326	0	0	0
T110	0	2	0	0
T141	0	2	0	0
T142	425	0	0	0
T143	521	0	0	0
T144	426	0	0	0
T145	647	0	0	0
T146	503	0	0	0
T147	426	0	0	0
T148	1476	0	0	0
T149	16390	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	84013	0	0
T18	103663	72706	0	0
T19	9205	281	0	0
T22	0	321	0	0
T37	0	1056	0	0
T38	0	47	0	0
T39	0	180	0	0
T40	0	659	0	0
T41	0	82	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T134	0	366	0	0
T135	0	259	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	64	0	0
T18	103663	2	0	0
T19	9205	1	0	0
T22	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4162662	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4164984	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	111	0	0
T7	116381	2	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T14	0	2	0	0
T18	0	3	0	0
T19	0	1	0	0
T22	0	2	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	5	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	73	0	0
T18	103663	2	0	0
T19	9205	1	0	0
T22	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	64	0	0
T18	103663	2	0	0
T19	9205	1	0	0
T22	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	64	0	0
T18	103663	2	0	0
T19	9205	1	0	0
T22	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	83949	0	0
T18	103663	72704	0	0
T19	9205	280	0	0
T22	0	319	0	0
T37	0	1053	0	0
T38	0	46	0	0
T39	0	178	0	0
T40	0	657	0	0
T41	0	81	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T134	0	365	0	0
T135	0	258	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	6899	0	0
T1	6250	30	0	0
T2	751	1	0	0
T3	18039	12	0	0
T4	10366	12	0	0
T5	15041	12	0	0
T23	408	0	0	0
T24	493	8	0	0
T25	1305	4	0	0
T26	777	3	0	0
T27	10053	30	0	0
T28	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	837790	0	0
T18	103663	256	0	0
T19	9205	87	0	0
T22	0	458	0	0
T37	0	387	0	0
T38	0	81	0	0
T39	0	117420	0	0
T40	0	148	0	0
T41	0	247	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T134	0	97	0	0
T135	0	767	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T1,T2,T24

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T24
1	1	Covered	T1,T2,T24

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T7,T14,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T7,T14,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T18,T19,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T18
1	0	Covered	T1,T2,T24
1	1	Covered	T7,T14,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T36
0	1	Covered	T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T36
0	1	Unreachable
1	0	Covered	T18,T19,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T14,T18
DetectSt	168	Covered	T18,T19,T36
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T18,T19,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T19,T36
DebounceSt->IdleSt	163	Covered	T7,T14,T18
DetectSt->IdleSt	186	Covered	T91,T92
DetectSt->StableSt	191	Covered	T18,T19,T36
IdleSt->DebounceSt	148	Covered	T7,T14,T18
StableSt->IdleSt	206	Covered	T18,T19,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T14,T18
0	1	Covered	T7,T14,T18
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T36
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T14,T18
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T19,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T18,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T14,T18
DetectSt	-	-	-	-	1	-	-	Covered	T91,T92
DetectSt	-	-	-	-	0	1	-	Covered	T18,T19,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T19,T36
StableSt	-	-	-	-	-	-	0	Covered	T18,T19,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	188	0	0
CntIncr_A	6011137	118336	0	0
CntNoWrap_A	6011137	5357703	0	0
DetectStDropOut_A	6011137	6	0	0
DetectedOut_A	6011137	615390	0	0
DetectedPulseOut_A	6011137	50	0	0
DisabledIdleSt_A	6011137	4162662	0	0
DisabledNoDetection_A	6011137	4164984	0	0
EnterDebounceSt_A	6011137	133	0	0
EnterDetectSt_A	6011137	56	0	0
EnterStableSt_A	6011137	50	0	0
PulseIsPulse_A	6011137	50	0	0
StayInStableSt	6011137	615340	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_sticky_sva.StableStDropOut_A	6011137	206828	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	188	0	0
T7	116381	2	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T14	0	2	0	0
T18	0	7	0	0
T19	0	2	0	0
T22	0	6	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	2	0	0
T37	0	6	0	0
T38	0	1	0	0
T39	0	4	0	0
T40	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	118336	0	0
T7	116381	168	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T14	0	78	0	0
T18	0	171	0	0
T19	0	34	0	0
T22	0	456	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	88	0	0
T37	0	240	0	0
T38	0	74	0	0
T39	0	31474	0	0
T40	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357703	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	6	0	0
T87	862	0	0	0
T88	153696	0	0	0
T91	155615	2	0	0
T92	0	4	0	0
T135	5617	0	0	0
T150	494	0	0	0
T151	492	0	0	0
T152	495	0	0	0
T153	22340	0	0	0
T154	526	0	0	0
T155	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	615390	0	0
T18	103663	30	0	0
T19	9205	132	0	0
T36	0	784	0	0
T37	0	757	0	0
T39	0	86202	0	0
T40	0	332	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T89	0	58	0	0
T91	0	36	0	0
T134	0	184	0	0
T135	0	541	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	50	0	0
T18	103663	2	0	0
T19	9205	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	2	0	0
T40	0	2	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T89	0	1	0	0
T91	0	2	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4162662	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4164984	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	133	0	0
T7	116381	2	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T14	0	2	0	0
T18	0	5	0	0
T19	0	1	0	0
T22	0	6	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	56	0	0
T18	103663	2	0	0
T19	9205	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	2	0	0
T40	0	2	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T89	0	1	0	0
T91	0	4	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	50	0	0
T18	103663	2	0	0
T19	9205	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	2	0	0
T40	0	2	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T89	0	1	0	0
T91	0	2	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	50	0	0
T18	103663	2	0	0
T19	9205	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	2	0	0
T40	0	2	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T89	0	1	0	0
T91	0	2	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	615340	0	0
T18	103663	28	0	0
T19	9205	131	0	0
T36	0	783	0	0
T37	0	754	0	0
T39	0	86200	0	0
T40	0	330	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T89	0	57	0	0
T91	0	34	0	0
T134	0	183	0	0
T135	0	540	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	206828	0	0
T18	103663	190	0	0
T19	9205	273	0	0
T36	0	114	0	0
T37	0	692	0	0
T39	0	85	0	0
T40	0	600	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T89	0	218	0	0
T91	0	88574	0	0
T134	0	307	0	0
T135	0	467	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T7,T14,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T7,T14,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T7,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T14,T18
1	0	Covered	T5,T1,T2
1	1	Covered	T7,T14,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T18,T22
0	1	Covered	T19,T41,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T18,T22
0	1	Unreachable
1	0	Covered	T7,T18,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T14,T18
DetectSt	168	Covered	T7,T18,T19
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T7,T18,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T18,T19
DebounceSt->IdleSt	163	Covered	T14,T19,T41
DetectSt->IdleSt	186	Covered	T19,T41,T90
DetectSt->StableSt	191	Covered	T7,T18,T22
IdleSt->DebounceSt	148	Covered	T7,T14,T18
StableSt->IdleSt	206	Covered	T7,T18,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T14,T18
0	1	Covered	T7,T14,T18
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T18,T19
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T14,T18
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T41,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T14,T18
DetectSt	-	-	-	-	1	-	-	Covered	T19,T41,T90
DetectSt	-	-	-	-	0	1	-	Covered	T7,T18,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T18,T22
StableSt	-	-	-	-	-	-	0	Covered	T7,T18,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	198	0	0
CntIncr_A	6011137	158012	0	0
CntNoWrap_A	6011137	5357693	0	0
DetectStDropOut_A	6011137	13	0	0
DetectedOut_A	6011137	84953	0	0
DetectedPulseOut_A	6011137	66	0	0
DisabledIdleSt_A	6011137	4162662	0	0
DisabledNoDetection_A	6011137	4164984	0	0
EnterDebounceSt_A	6011137	120	0	0
EnterDetectSt_A	6011137	79	0	0
EnterStableSt_A	6011137	66	0	0
PulseIsPulse_A	6011137	66	0	0
StayInStableSt	6011137	84887	0	0
gen_high_event_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_sticky_sva.StableStDropOut_A	6011137	816083	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	198	0	0
T7	116381	2	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T14	0	2	0	0
T18	0	6	0	0
T19	0	5	0	0
T22	0	4	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	2	0	0
T37	0	6	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	158012	0	0
T7	116381	41924	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T14	0	79	0	0
T18	0	263	0	0
T19	0	117	0	0
T22	0	190	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	95	0	0
T37	0	270	0	0
T38	0	85	0	0
T39	0	178	0	0
T40	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357693	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	13	0	0
T19	9205	2	0	0
T20	518	0	0	0
T41	0	3	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T90	0	2	0	0
T111	0	4	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0
T156	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	84953	0	0
T7	116381	72639	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T18	0	384	0	0
T22	0	475	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	785	0	0
T37	0	1315	0	0
T38	0	82	0	0
T39	0	244	0	0
T40	0	148	0	0
T90	0	61	0	0
T134	0	144	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	66	0	0
T7	116381	1	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T18	0	3	0	0
T22	0	2	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T90	0	1	0	0
T134	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4162662	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4164984	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	120	0	0
T7	116381	1	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T14	0	2	0	0
T18	0	3	0	0
T19	0	3	0	0
T22	0	2	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	79	0	0
T7	116381	1	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T18	0	3	0	0
T19	0	2	0	0
T22	0	2	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	66	0	0
T7	116381	1	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T18	0	3	0	0
T22	0	2	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T90	0	1	0	0
T134	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	66	0	0
T7	116381	1	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T18	0	3	0	0
T22	0	2	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T90	0	1	0	0
T134	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	84887	0	0
T7	116381	72638	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T18	0	381	0	0
T22	0	473	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	784	0	0
T37	0	1312	0	0
T38	0	81	0	0
T39	0	242	0	0
T40	0	146	0	0
T90	0	60	0	0
T134	0	143	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	816083	0	0
T7	116381	144	0	0
T8	10018	0	0	0
T9	508	0	0	0
T10	834	0	0	0
T18	0	88109	0	0
T22	0	240	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T36	0	116	0	0
T37	0	145	0	0
T38	0	29	0	0
T39	0	117346	0	0
T40	0	813	0	0
T90	0	175	0	0
T134	0	360	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T10,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T10,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T10,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T5,T1,T2
1	1	Covered	T2,T10,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T14
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T14
0	1	Covered	T2,T19,T51
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T10,T14
1	-	Covered	T2,T19,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T14
DetectSt	168	Covered	T2,T10,T14
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T10,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T14
DebounceSt->IdleSt	163	Covered	T2,T83
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T10,T14
IdleSt->DebounceSt	148	Covered	T2,T10,T14
StableSt->IdleSt	206	Covered	T2,T14,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T14
0	1	Covered	T2,T10,T14
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T14
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T2
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T14
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T14,T19
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	82	0	0
CntIncr_A	6011137	2494	0	0
CntNoWrap_A	6011137	5357809	0	0
DetectStDropOut_A	6011137	0	0	0
DetectedOut_A	6011137	4283	0	0
DetectedPulseOut_A	6011137	40	0	0
DisabledIdleSt_A	6011137	5337586	0	0
DisabledNoDetection_A	6011137	5339851	0	0
EnterDebounceSt_A	6011137	42	0	0
EnterDetectSt_A	6011137	40	0	0
EnterStableSt_A	6011137	40	0	0
PulseIsPulse_A	6011137	40	0	0
StayInStableSt	6011137	4219	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	82	0	0
T2	751	3	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T18	0	2	0	0
T19	0	4	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	2	0	0
T54	0	2	0	0
T132	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2494	0	0
T2	751	78	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	74	0	0
T14	0	35	0	0
T15	0	38	0	0
T18	0	40	0	0
T19	0	196	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	74	0	0
T54	0	97	0	0
T132	0	22	0	0
T157	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357809	0	0
T1	6250	2449	0	0
T2	751	347	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4283	0	0
T2	751	110	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	178	0	0
T14	0	12	0	0
T15	0	39	0	0
T18	0	116	0	0
T19	0	211	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	28	0	0
T54	0	203	0	0
T132	0	82	0	0
T157	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	40	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T132	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5337586	0	0
T1	6250	2449	0	0
T2	751	3	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5339851	0	0
T1	6250	2458	0	0
T2	751	3	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	42	0	0
T2	751	2	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T132	0	1	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	40	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T132	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	40	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T132	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	40	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T132	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4219	0	0
T2	751	109	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	176	0	0
T14	0	11	0	0
T15	0	37	0	0
T18	0	114	0	0
T19	0	208	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	27	0	0
T54	0	202	0	0
T132	0	80	0	0
T157	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	15	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T19	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T14,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T8,T14,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T14,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T14
1	0	Covered	T5,T1,T2
1	1	Covered	T8,T14,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T14,T51
0	1	Covered	T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T14,T51
0	1	Covered	T51,T53,T54
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T14,T51
1	-	Covered	T51,T53,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T14,T51
DetectSt	168	Covered	T8,T14,T51
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T8,T14,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T14,T51
DebounceSt->IdleSt	163	Covered	T164,T165,T166
DetectSt->IdleSt	186	Covered	T88
DetectSt->StableSt	191	Covered	T8,T14,T51
IdleSt->DebounceSt	148	Covered	T8,T14,T51
StableSt->IdleSt	206	Covered	T8,T14,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T14,T51
0	1	Covered	T8,T14,T51
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T14,T51
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T14,T51
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T14,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T164,T165,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T14,T51
DetectSt	-	-	-	-	1	-	-	Covered	T88
DetectSt	-	-	-	-	0	1	-	Covered	T8,T14,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T51,T53
StableSt	-	-	-	-	-	-	0	Covered	T8,T14,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	108	0	0
CntIncr_A	6011137	78311	0	0
CntNoWrap_A	6011137	5357783	0	0
DetectStDropOut_A	6011137	1	0	0
DetectedOut_A	6011137	23260	0	0
DetectedPulseOut_A	6011137	50	0	0
DisabledIdleSt_A	6011137	5049681	0	0
DisabledNoDetection_A	6011137	5051950	0	0
EnterDebounceSt_A	6011137	57	0	0
EnterDetectSt_A	6011137	51	0	0
EnterStableSt_A	6011137	50	0	0
PulseIsPulse_A	6011137	50	0	0
StayInStableSt	6011137	23191	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6011137	2675	0	0
gen_low_level_sva.LowLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	108	0	0
T8	10018	2	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	2	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	4	0	0
T53	0	2	0	0
T54	0	4	0	0
T87	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	78311	0	0
T8	10018	75	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	35	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	148	0	0
T53	0	47	0	0
T54	0	194	0	0
T87	0	83	0	0
T164	0	61	0	0
T165	0	54	0	0
T167	0	97	0	0
T168	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357783	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1	0	0
T88	153696	1	0	0
T169	426	0	0	0
T170	13127	0	0	0
T171	651	0	0	0
T172	805	0	0	0
T173	423	0	0	0
T174	523	0	0	0
T175	21072	0	0	0
T176	32735	0	0	0
T177	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	23260	0	0
T8	10018	40	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	12	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	81	0	0
T53	0	267	0	0
T54	0	102	0	0
T80	0	139	0	0
T87	0	41	0	0
T88	0	43	0	0
T167	0	42	0	0
T168	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	50	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T80	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5049681	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5051950	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	57	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T87	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	51	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T80	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	50	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T80	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	50	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T80	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	23191	0	0
T8	10018	38	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	11	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	78	0	0
T53	0	266	0	0
T54	0	99	0	0
T80	0	138	0	0
T87	0	40	0	0
T88	0	42	0	0
T167	0	40	0	0
T168	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2675	0	0
T1	6250	23	0	0
T2	751	3	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	60	0	0
T23	408	0	0	0
T24	493	3	0	0
T25	1305	6	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	1	0	0
T29	0	3	0	0
T30	0	5	0	0
T46	0	4	0	0
T61	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	30	0	0
T51	817	1	0	0
T52	584	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T70	6129	0	0	0
T80	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T96	650	0	0	0
T133	522	0	0	0
T158	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	522	0	0	0
T181	500	0	0	0
T182	6536	0	0	0
T183	690	0	0	0
T184	865	0	0	0