Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_ec_rst_ctl_cdc

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	88.73			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1907274	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	2108	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1907274	0	0
T1	750006	950	0	0
T2	127048	0	0	0
T3	216477	2736	0	0
T4	466496	4605	0	0
T5	383560	4216	0	0
T6	0	5061	0	0
T7	0	998	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	695	0	0
T48	0	2562	0	0
T56	0	377	0	0
T60	0	1015	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2108	0	0
T1	750006	2	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T7	0	1	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T48	0	12	0	0
T56	0	2	0	0
T60	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T7,T8,T45

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T7,T8,T45
1	1	Covered	T7,T8,T45

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T7,T8,T45

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T45
1	1	Covered	T7,T8,T45

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T8,T45
0	0	1	Covered	T7,T8,T45
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T8,T45
0	0	1	Covered	T7,T8,T45
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1124189	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1165	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1124189	0	0
T7	423435	998	0	0
T8	456742	1934	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T14	0	495	0	0
T18	0	4123	0	0
T19	0	5477	0	0
T22	0	232	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	2276	0	0
T37	0	4716	0	0
T38	0	3989	0	0
T45	0	238	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1165	0	0
T7	423435	1	0	0
T8	456742	1	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T14	0	1	0	0
T18	0	5	0	0
T19	0	3	0	0
T22	0	2	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	2	0	0
T45	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T7,T8,T45

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T7,T8,T45
1	1	Covered	T7,T8,T45

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T7,T8,T45

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T45
1	1	Covered	T7,T8,T45

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T8,T45
0	0	1	Covered	T7,T8,T45
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T8,T45
0	0	1	Covered	T7,T8,T45
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1151245	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1166	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1151245	0	0
T7	423435	996	0	0
T8	456742	1927	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T14	0	486	0	0
T18	0	4113	0	0
T19	0	5453	0	0
T22	0	228	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	2272	0	0
T37	0	4692	0	0
T38	0	3970	0	0
T45	0	229	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1166	0	0
T7	423435	1	0	0
T8	456742	1	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T14	0	1	0	0
T18	0	5	0	0
T19	0	3	0	0
T22	0	2	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	2	0	0
T45	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T7,T8,T45

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T7,T8,T45
1	1	Covered	T7,T8,T45

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T7,T8,T45

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T45
1	1	Covered	T7,T8,T45

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T8,T45
0	0	1	Covered	T7,T8,T45
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T8,T45
0	0	1	Covered	T7,T8,T45
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1136525	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1175	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1136525	0	0
T7	423435	994	0	0
T8	456742	1915	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T14	0	482	0	0
T18	0	4103	0	0
T19	0	5432	0	0
T22	0	224	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	2268	0	0
T37	0	4669	0	0
T38	0	3953	0	0
T45	0	223	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1175	0	0
T7	423435	1	0	0
T8	456742	1	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T14	0	1	0	0
T18	0	5	0	0
T19	0	3	0	0
T22	0	2	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	2	0	0
T45	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T7,T14,T18

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T7,T14,T18
1	1	Covered	T7,T14,T18

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T7,T14,T18
1	-	Covered	T7,T14,T18

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T7,T14,T18

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T14,T18
1	1	Covered	T7,T14,T18

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T14,T18
0	0	1	Covered	T7,T14,T18
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T14,T18
0	0	1	Covered	T7,T14,T18
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1168318	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1184	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1168318	0	0
T7	423435	1999	0	0
T8	456742	0	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T14	0	1575	0	0
T18	0	4818	0	0
T19	0	3478	0	0
T22	0	513	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	2280	0	0
T37	0	9452	0	0
T38	0	3996	0	0
T39	0	1686	0	0
T40	0	3523	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1184	0	0
T7	423435	2	0	0
T8	456742	0	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T14	0	4	0	0
T18	0	6	0	0
T19	0	2	0	0
T22	0	4	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	2	0	0
T37	0	6	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T7,T18,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T7,T18,T19
1	1	Covered	T7,T18,T19

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T42,T43,T44
1	-	Covered	T7,T18,T19

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T18,T19
1	0	Covered	T7,T18,T19

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T18,T19
1	1	Covered	T7,T18,T19

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Not Covered
1	1	Covered	T7,T18,T19

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T18,T19
0	0	1	Covered	T7,T18,T19
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T7,T18,T19
0	0	1	Covered	T7,T18,T19
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	630371	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	632	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	630371	0	0
T7	423435	995	0	0
T8	456742	0	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T18	0	2513	0	0
T19	0	1464	0	0
T22	0	229	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	1135	0	0
T37	0	4683	0	0
T38	0	1966	0	0
T39	0	801	0	0
T40	0	1870	0	0
T41	0	706	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	632	0	0
T7	423435	1	0	0
T8	456742	0	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T18	0	3	0	0
T19	0	1	0	0
T22	0	2	0	0
T30	495039	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T11
1	-	Covered	T3,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1219749	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1256	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1219749	0	0
T1	750006	474	0	0
T2	127048	0	0	0
T3	216477	1713	0	0
T4	466496	4881	0	0
T6	0	1911	0	0
T7	0	997	0	0
T8	0	1431	0	0
T11	0	338	0	0
T12	0	1497	0	0
T13	0	2483	0	0
T14	0	467	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1256	0	0
T1	750006	1	0	0
T2	127048	0	0	0
T3	216477	4	0	0
T4	466496	3	0	0
T6	0	4	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	6	0	0
T14	0	1	0	0
T16	0	1	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T24,T46

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T24,T46
1	1	Covered	T1,T24,T46

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T24,T46

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T24,T46
1	1	Covered	T1,T24,T46

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T24,T46
0	0	1	Covered	T1,T24,T46
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T24,T46
0	0	1	Covered	T1,T24,T46
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	2757618	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	3306	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2757618	0	0
T1	750006	26422	0	0
T2	127048	0	0	0
T3	216477	0	0	0
T4	466496	0	0	0
T16	0	9758	0	0
T18	0	95928	0	0
T19	0	70775	0	0
T23	51093	0	0	0
T24	246720	35506	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T32	0	1606	0	0
T46	0	20082	0	0
T61	0	19528	0	0
T62	0	35902	0	0
T63	0	8778	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	3306	0	0
T1	750006	60	0	0
T2	127048	0	0	0
T3	216477	0	0	0
T4	466496	0	0	0
T16	0	20	0	0
T18	0	120	0	0
T19	0	40	0	0
T23	51093	0	0	0
T24	246720	20	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T32	0	20	0	0
T46	0	20	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T24,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T24,T25
1	1	Covered	T1,T24,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T24,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T24,T25
1	1	Covered	T1,T24,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T24,T25
0	0	1	Covered	T1,T24,T25
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T24,T25
0	0	1	Covered	T1,T24,T25
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	5582440	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	6655	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5582440	0	0
T1	750006	10241	0	0
T2	127048	0	0	0
T3	216477	0	0	0
T4	466496	0	0	0
T8	0	233509	0	0
T23	51093	0	0	0
T24	246720	1497	0	0
T25	626300	34023	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T30	0	16248	0	0
T32	0	86	0	0
T34	0	8464	0	0
T46	0	822	0	0
T61	0	819	0	0
T62	0	1976	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	6655	0	0
T1	750006	23	0	0
T2	127048	0	0	0
T3	216477	0	0	0
T4	466496	0	0	0
T8	0	138	0	0
T23	51093	0	0	0
T24	246720	1	0	0
T25	626300	20	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T30	0	20	0	0
T32	0	1	0	0
T34	0	20	0	0
T46	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	6616568	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	7759	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	6616568	0	0
T1	750006	11646	0	0
T2	127048	0	0	0
T3	216477	3138	0	0
T4	466496	4861	0	0
T5	383560	4312	0	0
T6	0	5643	0	0
T23	51093	0	0	0
T24	246720	1499	0	0
T25	626300	34450	0	0
T26	373544	0	0	0
T27	246292	734	0	0
T48	0	2961	0	0
T60	0	1031	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7759	0	0
T1	750006	26	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T23	51093	0	0	0
T24	246720	1	0	0
T25	626300	20	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T48	0	12	0	0
T60	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T25,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T25,T30
1	1	Covered	T1,T25,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T25,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T25,T30
1	1	Covered	T1,T25,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T25,T30
0	0	1	Covered	T1,T25,T30
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T25,T30
0	0	1	Covered	T1,T25,T30
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	5503172	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	6513	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5503172	0	0
T1	750006	8608	0	0
T2	127048	0	0	0
T3	216477	0	0	0
T4	466496	0	0	0
T8	0	234738	0	0
T18	0	79415	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	34259	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T30	0	16288	0	0
T34	0	8627	0	0
T64	0	31834	0	0
T65	0	8123	0	0
T66	0	8246	0	0
T67	0	9372	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	6513	0	0
T1	750006	20	0	0
T2	127048	0	0	0
T3	216477	0	0	0
T4	466496	0	0	0
T8	0	138	0	0
T18	0	100	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	20	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T30	0	20	0	0
T34	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T2,T8,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T8,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T2,T8,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T8,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T2,T8,T9
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T2,T8,T9
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1116260	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1177	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1116260	0	0
T2	127048	749	0	0
T3	216477	0	0	0
T4	466496	0	0	0
T8	0	1929	0	0
T9	0	379	0	0
T10	0	706	0	0
T14	0	12080	0	0
T15	0	1918	0	0
T18	0	920	0	0
T19	0	1480	0	0
T20	0	1983	0	0
T21	0	1477	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1177	0	0
T2	127048	1	0	0
T3	216477	0	0	0
T4	466496	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	28	0	0
T15	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1952294	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	2136	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1952294	0	0
T1	750006	470	0	0
T2	127048	747	0	0
T3	216477	2674	0	0
T4	466496	4569	0	0
T5	383560	4206	0	0
T6	0	4929	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	693	0	0
T30	0	709	0	0
T48	0	2538	0	0
T56	0	363	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2136	0	0
T1	750006	1	0	0
T2	127048	1	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T30	0	1	0	0
T48	0	12	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T26,T47,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T26,T47,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T26,T47,T8
0	0	1	Covered	T26,T47,T8
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T26,T47,T8
0	0	1	Covered	T26,T47,T8
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1357657	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1438	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1357657	0	0
T6	453578	0	0	0
T8	0	6744	0	0
T14	0	997	0	0
T18	0	4133	0	0
T19	0	9480	0	0
T26	373544	6222	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T35	0	438	0	0
T46	136607	0	0	0
T47	353533	5814	0	0
T48	243556	0	0	0
T56	712751	0	0	0
T57	0	7975	0	0
T58	0	4922	0	0
T59	0	4985	0	0
T60	200217	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1438	0	0
T6	453578	0	0	0
T8	0	4	0	0
T14	0	2	0	0
T18	0	5	0	0
T19	0	5	0	0
T26	373544	4	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T35	0	3	0	0
T46	136607	0	0	0
T47	353533	4	0	0
T48	243556	0	0	0
T56	712751	0	0	0
T57	0	5	0	0
T58	0	3	0	0
T59	0	3	0	0
T60	200217	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T26,T47,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T26,T47,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T26,T47,T8
0	0	1	Covered	T26,T47,T8
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T26,T47,T8
0	0	1	Covered	T26,T47,T8
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1273233	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1318	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1273233	0	0
T6	453578	0	0	0
T8	0	5269	0	0
T14	0	491	0	0
T18	0	2520	0	0
T19	0	5458	0	0
T26	373544	4762	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T35	0	432	0	0
T46	136607	0	0	0
T47	353533	4353	0	0
T48	243556	0	0	0
T56	712751	0	0	0
T57	0	4948	0	0
T58	0	4893	0	0
T59	0	4959	0	0
T60	200217	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1318	0	0
T6	453578	0	0	0
T8	0	3	0	0
T14	0	1	0	0
T18	0	3	0	0
T19	0	3	0	0
T26	373544	3	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T35	0	3	0	0
T46	136607	0	0	0
T47	353533	3	0	0
T48	243556	0	0	0
T56	712751	0	0	0
T57	0	3	0	0
T58	0	3	0	0
T59	0	3	0	0
T60	200217	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	7164787	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	7325	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7164787	0	0
T6	453578	37616	0	0
T11	0	355	0	0
T13	0	37980	0	0
T14	0	5011	0	0
T17	0	126399	0	0
T27	246292	67168	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	23272	0	0
T56	712751	13619	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	37191	0	0
T69	0	86246	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7325	0	0
T6	453578	90	0	0
T11	0	1	0	0
T13	0	89	0	0
T14	0	11	0	0
T17	0	81	0	0
T27	246292	79	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	86	0	0
T56	712751	66	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	88	0	0
T69	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	7098324	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	7298	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7098324	0	0
T6	453578	32128	0	0
T13	0	32183	0	0
T14	0	4976	0	0
T17	0	100838	0	0
T27	246292	59568	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	24006	0	0
T56	712751	15906	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	30416	0	0
T69	0	85321	0	0
T70	0	37516	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7298	0	0
T6	453578	82	0	0
T13	0	80	0	0
T14	0	11	0	0
T17	0	66	0	0
T27	246292	70	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	90	0	0
T56	712751	80	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	73	0	0
T69	0	51	0	0
T70	0	58	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	6876477	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	7114	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	6876477	0	0
T6	453578	25678	0	0
T13	0	30121	0	0
T14	0	5019	0	0
T17	0	109397	0	0
T27	246292	51846	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	19180	0	0
T56	712751	11074	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	26260	0	0
T69	0	84387	0	0
T70	0	49173	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7114	0	0
T6	453578	68	0	0
T13	0	78	0	0
T14	0	11	0	0
T17	0	72	0	0
T27	246292	62	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	73	0	0
T56	712751	60	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	63	0	0
T69	0	51	0	0
T70	0	77	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	6864284	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	7198	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	6864284	0	0
T6	453578	38320	0	0
T13	0	24142	0	0
T14	0	5006	0	0
T17	0	84540	0	0
T27	246292	63276	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	20975	0	0
T56	712751	13436	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	30546	0	0
T69	0	83461	0	0
T70	0	47461	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7198	0	0
T6	453578	99	0	0
T13	0	64	0	0
T14	0	11	0	0
T17	0	56	0	0
T27	246292	75	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	81	0	0
T56	712751	74	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	75	0	0
T69	0	51	0	0
T70	0	77	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1380332	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1419	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1380332	0	0
T6	453578	5804	0	0
T11	0	352	0	0
T13	0	3025	0	0
T14	0	3958	0	0
T17	0	9169	0	0
T27	246292	733	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	3018	0	0
T56	712751	374	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	2753	0	0
T69	0	1907	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1419	0	0
T6	453578	13	0	0
T11	0	1	0	0
T13	0	7	0	0
T14	0	9	0	0
T17	0	6	0	0
T27	246292	1	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	12	0	0
T56	712751	2	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	6	0	0
T69	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1378789	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1416	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1378789	0	0
T6	453578	5182	0	0
T13	0	2689	0	0
T14	0	3937	0	0
T17	0	8955	0	0
T27	246292	723	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	2898	0	0
T56	712751	309	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	2693	0	0
T69	0	1862	0	0
T70	0	722	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1416	0	0
T6	453578	13	0	0
T13	0	7	0	0
T14	0	9	0	0
T17	0	6	0	0
T27	246292	1	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	12	0	0
T56	712751	2	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	6	0	0
T69	0	1	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1348551	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1392	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1348551	0	0
T6	453578	4694	0	0
T13	0	2696	0	0
T14	0	3959	0	0
T17	0	8773	0	0
T27	246292	713	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	2778	0	0
T56	712751	366	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	2633	0	0
T69	0	1822	0	0
T70	0	670	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1392	0	0
T6	453578	13	0	0
T13	0	7	0	0
T14	0	9	0	0
T17	0	6	0	0
T27	246292	1	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	12	0	0
T56	712751	2	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	6	0	0
T69	0	1	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T27,T48,T6
0	0	1	Covered	T27,T48,T6
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1377421	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1423	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1377421	0	0
T6	453578	5508	0	0
T13	0	2829	0	0
T14	0	3948	0	0
T17	0	8583	0	0
T27	246292	703	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	2658	0	0
T56	712751	301	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	2573	0	0
T69	0	1764	0	0
T70	0	616	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1423	0	0
T6	453578	13	0	0
T13	0	7	0	0
T14	0	9	0	0
T17	0	6	0	0
T27	246292	1	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T47	353533	0	0	0
T48	243556	12	0	0
T56	712751	2	0	0
T60	200217	0	0	0
T61	135832	0	0	0
T68	0	6	0	0
T69	0	1	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	7713673	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	7974	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7713673	0	0
T1	750006	478	0	0
T2	127048	0	0	0
T3	216477	3210	0	0
T4	466496	4943	0	0
T5	383560	4336	0	0
T6	0	38155	0	0
T8	0	3850	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	67320	0	0
T30	0	717	0	0
T48	0	23372	0	0
T56	0	13939	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7974	0	0
T1	750006	1	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	90	0	0
T8	0	2	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	79	0	0
T30	0	1	0	0
T48	0	86	0	0
T56	0	66	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	7601364	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	7852	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7601364	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	3166	0	0
T4	466496	4922	0	0
T5	383560	4326	0	0
T6	0	32486	0	0
T12	0	14985	0	0
T13	0	32818	0	0
T14	0	4869	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	59702	0	0
T48	0	24114	0	0
T56	0	16421	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7852	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	82	0	0
T12	0	9	0	0
T13	0	80	0	0
T14	0	11	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	70	0	0
T48	0	90	0	0
T56	0	80	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	7389295	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	7715	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7389295	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	3128	0	0
T4	466496	4885	0	0
T5	383560	4316	0	0
T6	0	26040	0	0
T12	0	14967	0	0
T13	0	31084	0	0
T14	0	4890	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	51964	0	0
T48	0	19254	0	0
T56	0	11427	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7715	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	68	0	0
T12	0	9	0	0
T13	0	78	0	0
T14	0	11	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	62	0	0
T48	0	73	0	0
T56	0	60	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	7380570	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	7796	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7380570	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	3072	0	0
T4	466496	4849	0	0
T5	383560	4306	0	0
T6	0	38903	0	0
T12	0	14949	0	0
T13	0	24648	0	0
T14	0	4883	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	63420	0	0
T48	0	21065	0	0
T56	0	13665	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7796	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	99	0	0
T12	0	9	0	0
T13	0	64	0	0
T14	0	11	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	75	0	0
T48	0	81	0	0
T56	0	74	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1878637	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	2032	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1878637	0	0
T1	750006	476	0	0
T2	127048	0	0	0
T3	216477	3026	0	0
T4	466496	4823	0	0
T5	383560	4296	0	0
T6	0	5556	0	0
T8	0	3837	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	729	0	0
T30	0	715	0	0
T48	0	2970	0	0
T56	0	346	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2032	0	0
T1	750006	1	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T8	0	2	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T30	0	1	0	0
T48	0	12	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1829483	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1981	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1829483	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	2964	0	0
T4	466496	4790	0	0
T5	383560	4286	0	0
T6	0	4939	0	0
T12	0	14913	0	0
T13	0	2557	0	0
T14	0	3807	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	719	0	0
T48	0	2850	0	0
T56	0	279	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1981	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T12	0	9	0	0
T13	0	7	0	0
T14	0	9	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T48	0	12	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1797872	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1954	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1797872	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	2910	0	0
T4	466496	4756	0	0
T5	383560	4276	0	0
T6	0	5580	0	0
T12	0	14895	0	0
T13	0	2658	0	0
T14	0	3841	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	709	0	0
T48	0	2730	0	0
T56	0	349	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1954	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T12	0	9	0	0
T13	0	7	0	0
T14	0	9	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T48	0	12	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1800766	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1970	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1800766	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	2862	0	0
T4	466496	4740	0	0
T5	383560	4266	0	0
T6	0	5206	0	0
T12	0	14877	0	0
T13	0	2705	0	0
T14	0	3844	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	699	0	0
T48	0	2610	0	0
T56	0	271	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1970	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T12	0	9	0	0
T13	0	7	0	0
T14	0	9	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T48	0	12	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T1,T3
0	0	1	Covered	T5,T1,T3
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1834907	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	2000	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1834907	0	0
T1	750006	474	0	0
T2	127048	0	0	0
T3	216477	2824	0	0
T4	466496	4712	0	0
T5	383560	4256	0	0
T6	0	5456	0	0
T8	0	3821	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	727	0	0
T30	0	713	0	0
T48	0	2946	0	0
T56	0	338	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2000	0	0
T1	750006	1	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T8	0	2	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T30	0	1	0	0
T48	0	12	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1820436	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1965	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1820436	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	2779	0	0
T4	466496	4684	0	0
T5	383560	4246	0	0
T6	0	4833	0	0
T12	0	14841	0	0
T13	0	2502	0	0
T14	0	3744	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	717	0	0
T48	0	2826	0	0
T56	0	337	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1965	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T12	0	9	0	0
T13	0	7	0	0
T14	0	9	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T48	0	12	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1787710	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1966	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1787710	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	2718	0	0
T4	466496	4664	0	0
T5	383560	4236	0	0
T6	0	5796	0	0
T12	0	14823	0	0
T13	0	2961	0	0
T14	0	3763	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	707	0	0
T48	0	2706	0	0
T56	0	330	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1966	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T12	0	9	0	0
T13	0	7	0	0
T14	0	9	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T48	0	12	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T3,T4
1	1	Covered	T5,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T5,T3,T4
0	0	1	Covered	T5,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1745238	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1944	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1745238	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	2663	0	0
T4	466496	4640	0	0
T5	383560	4226	0	0
T6	0	5088	0	0
T12	0	14805	0	0
T13	0	2623	0	0
T14	0	3777	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	697	0	0
T48	0	2586	0	0
T56	0	325	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1944	0	0
T1	750006	0	0	0
T2	127048	0	0	0
T3	216477	7	0	0
T4	466496	3	0	0
T5	383560	5	0	0
T6	0	13	0	0
T12	0	9	0	0
T13	0	7	0	0
T14	0	9	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	1	0	0
T48	0	12	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Unreachable
1	0	Covered	T1,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T1,T2
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1180808185	1110322	0	0
DstReqKnown_A	6294349	5440436	0	0
SrcAckBusyChk_A	1180808185	1156	0	0
SrcBusyKnown_A	1180808185	1179106424	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1110322	0	0
T1	750006	478	0	0
T2	127048	0	0	0
T3	216477	1709	0	0
T4	466496	4853	0	0
T6	0	1845	0	0
T8	0	3855	0	0
T11	0	355	0	0
T12	0	1495	0	0
T13	0	2396	0	0
T16	0	529	0	0
T17	0	6057	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6294349	5440436	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1156	0	0
T1	750006	1	0	0
T2	127048	0	0	0
T3	216477	4	0	0
T4	466496	3	0	0
T6	0	4	0	0
T8	0	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	6	0	0
T16	0	1	0	0
T17	0	4	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1179106424	0	0
T1	750006	747349	0	0
T2	127048	126955	0	0
T3	216477	215979	0	0
T4	466496	465995	0	0
T5	383560	382940	0	0
T23	51093	51030	0	0
T24	246720	246633	0	0
T25	626300	626075	0	0
T26	373544	373493	0	0
T27	246292	246285	0	0