Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1855

1

T1

24

T8

24

T9

2

auto[1]

668

1

T2

2

T8

13

T10

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1822

1

T1

18

T2

2

T8

37

auto[1]

701

1

T1

6

T13

5

T20

13

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1899

1

T1

12

T2

2

T8

37

auto[1]

624

1

T1

12

T12

6

T13

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1859

1

T1

15

T2

2

T8

13

auto[1]

664

1

T1

9

T8

24

T9

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2360

1

T1

24

T2

2

T8

37

auto[1]

163

1

T14

2

T46

1

T69

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2337

1

T1

24

T2

2

T8

37

auto[1]

186

1

T16

4

T69

4

T44

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2298

1

T1

24

T2

2

T8

37

auto[1]

225

1

T16

2

T46

1

T69

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2371

1

T1

24

T2

2

T8

37

auto[1]

152

1

T16

2

T45

3

T226

8

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2347

1

T1

24

T2

2

T8

37

auto[1]

176

1

T14

2

T16

4

T46

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1881

1

T1

9

T8

37

T9

2

auto[1]

642

1

T1

15

T2

2

T10

9

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	1031	1			T1	24		T2	2		T8	25
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	59	1			T14	2		T69	4		T229	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	60	1			T14	2		T44	5		T243	16
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	23	1			T79	4		T239	4		T333	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	53	1			T224	2		T201	1		T337	9
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	16	1			T45	3		T226	2		T230	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	23	1			T226	4		T227	1		T243	11
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	71	1			T228	2		T201	2		T338	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	10	1			T44	2		T339	2		T340	6
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	19	1			T46	1		T69	2		T224	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T243	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	23	1			T178	3		T80	8		T341	12
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T342	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	8	1			T337	8		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	64	1			T229	8		T89	12		T338	18
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	18	1			T45	5		T227	1		T343	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	22	1			T16	2		T44	3		T178	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	4	1			T226	2		T344	2		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T79	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	31	1			T69	4		T336	5		T345	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	8	1			T239	6		T346	2		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T347	4		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	7	1			T224	1		T228	1		T321	1
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T16	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

108

1

T8

13

T16

2

T73

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

119

1

T69

4

T44

2

T45

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

53

1

T2

2

T178

3

T338

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

93

1

T8

12

T9

2

T73

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

60

1

T10

4

T231

4

T44

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

98

1

T1

6

T10

6

T13

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T10

3

T88

3

T325

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

117

1

T1

9

T14

2

T22

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

76

1

T12

6

T229

8

T177

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

10

1

T226

2

T329

6

T348

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T319

1

T200

7

T244

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

65

1

T232

5

T244

2

T78

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T16

2

T78

4

T318

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

44

1

T1

3

T14

2

T323

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T237

1

T319

1

T99

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

113

1

T13

3

T20

10

T46

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

86

1

T226

4

T224

2

T201

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T1

6

T20

3

T349

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T73

1

T319

1

T318

10

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T185

5

T69

2

T319

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T323

3

T320

1

T345

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

38

1

T231

4

T339

2

T331

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T237

2

T228

2

T350

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T72

6

T323

3

T316

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

64

1

T44

5

T200

6

T243

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T72

3

T45

3

T323

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T72

2

T201

1

T163

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T239

4

T319

2

T78

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T72

2

T240

4

T88

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T232

2

T316

1

T325

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T78

2

T351

6

T352

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded