Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T2

12

T29

10

T63

12

auto[1]

1066

1

T2

8

T29

10

T63

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T2

4

T29

4

T63

6

from_0to1

503

1

T2

3

T29

4

T63

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T2

11

T29

9

T63

9

auto[1]

1074

1

T2

9

T29

11

T63

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T2

8

T29

10

T63

6

auto[1]

1062

1

T2

12

T29

10

T63

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T2

1

T29

1

T64

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T2

1

T63

1

T64

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T63

1

T53

1

T67

2

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T63

1

T53

1

T15

6

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T29

1

T63

1

T64

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T64

1

T15

5

T284

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T2

2

T29

1

T63

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T29

1

T63

2

T15

3

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T2

1

T29

1

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T2

1

T29

1

T63

2

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T29

1

T64

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T63

1

T53

1

T15

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T29

1

T15

4

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T67

1

T15

3

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T63

1

T64

1

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T2

1

T64

1

T53

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T2

9

T29

12

T63

14

auto[1]

1078

1

T2

11

T29

8

T63

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T2

5

T29

5

T63

5

from_0to1

520

1

T2

4

T29

5

T63

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T2

9

T29

12

T63

11

auto[1]

1071

1

T2

11

T29

8

T63

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T2

8

T29

10

T63

12

auto[1]

1098

1

T2

12

T29

10

T63

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T29

1

T63

1

T53

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T2

1

T29

1

T64

2

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T63

1

T15

3

T284

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T29

1

T64

1

T53

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T29

1

T63

1

T64

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T64

3

T67

1

T15

6

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T29

1

T63

1

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T2

3

T29

1

T63

2

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T2

2

T63

2

T15

2

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T2

1

T63

1

T64

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T29

1

T64

1

T15

4

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T2

1

T29

1

T15

7

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T29

1

T63

1

T53

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T29

1

T63

1

T15

4

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T2

1

T15

3

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T64

2

T15

4

T284

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T2

7

T29

10

T63

10

auto[1]

1126

1

T2

13

T29

10

T63

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T2

5

T29

4

T63

2

from_0to1

520

1

T2

5

T29

4

T63

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T2

9

T29

12

T63

11

auto[1]

1113

1

T2

11

T29

8

T63

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T2

11

T29

7

T63

12

auto[1]

1077

1

T2

9

T29

13

T63

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T29

1

T63

1

T53

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T29

1

T64

1

T15

5

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T2

2

T63

1

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T53

2

T67

1

T15

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T29

1

T63

1

T64

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T29

1

T63

1

T15

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T53

1

T15

4

T284

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T2

1

T29

1

T64

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T2

1

T64

1

T53

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T15

5

T73

2

T363

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T2

1

T64

1

T15

4

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T2

1

T29

2

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

82

1

T2

1

T64

1

T53

3

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T2

2

T63

1

T67

2

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T53

1

T67

1

T15

2

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T2

1

T29

1

T64

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T2

10

T29

11

T63

11

auto[1]

1098

1

T2

10

T29

9

T63

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T2

4

T29

7

T63

4

from_0to1

539

1

T2

4

T29

6

T63

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T2

9

T29

11

T63

12

auto[1]

1088

1

T2

11

T29

9

T63

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T2

9

T29

13

T63

10

auto[1]

1073

1

T2

11

T29

7

T63

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T2

1

T29

1

T63

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T2

1

T63

1

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T2

1

T53

1

T15

5

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T2

1

T29

2

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T29

2

T53

3

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T63

1

T64

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T29

1

T63

1

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T2

1

T64

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T63

1

T53

1

T15

5

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T29

1

T67

2

T15

5

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T29

2

T64

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T29

1

T64

2

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T29

2

T64

3

T15

7

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T63

1

T53

2

T15

3

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T2

2

T53

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

90

1

T2

1

T29

1

T53

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T2

10

T29

11

T63

9

auto[1]

1078

1

T2

10

T29

9

T63

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

528

1

T2

6

T29

3

T63

4

from_0to1

522

1

T2

5

T29

4

T63

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T2

12

T29

14

T63

11

auto[1]

1022

1

T2

8

T29

6

T63

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T2

10

T29

7

T63

11

auto[1]

1104

1

T2

10

T29

13

T63

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T2

1

T64

1

T53

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T2

1

T29

1

T53

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T2

2

T67

1

T15

3

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T67

1

T15

5

T284

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T2

2

T64

3

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T29

1

T64

1

T15

3

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T2

1

T53

1

T67

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T29

1

T15

3

T284

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T2

2

T63

1

T53

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T63

1

T64

2

T53

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T63

1

T64

1

T15

3

auto[1]

from_1to0

auto[1]

auto[1]

82

1

T29

2

T63

1

T64

1

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T29

1

T63

2

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T2

1

T29

1

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T53

1

T67

1

T15

6

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T2

1

T63

1

T64

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T2

11

T29

9

T63

8

auto[1]

1063

1

T2

9

T29

11

T63

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T2

3

T29

5

T63

5

from_0to1

515

1

T2

4

T29

5

T63

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1039

1

T2

8

T29

11

T63

8

auto[1]

1121

1

T2

12

T29

9

T63

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T2

10

T29

7

T63

13

auto[1]

1098

1

T2

10

T29

13

T63

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T29

1

T67

1

T15

2

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T2

1

T29

1

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T63

1

T67

2

T15

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T2

1

T29

1

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T63

1

T53

1

T15

6

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T29

1

T64

1

T284

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T2

1

T67

1

T15

5

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T2

1

T53

1

T67

2

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T29

1

T53

1

T67

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T64

1

T15

2

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T63

3

T53

1

T15

3

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T2

1

T29

1

T64

1

auto[1]

from_0to1

auto[0]

auto[0]

84

1

T2

2

T29

1

T64

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T29

2

T63

1

T15

4

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T29

1

T63

1

T15

4

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T63

1

T53

2

T15

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T2

13

T29

8

T63

9

auto[1]

1059

1

T2

7

T29

12

T63

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T2

4

T29

6

T63

5

from_0to1

510

1

T2

4

T29

6

T63

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1085

1

T2

8

T29

13

T63

10

auto[1]

1075

1

T2

12

T29

7

T63

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T2

8

T29

11

T63

12

auto[1]

1047

1

T2

12

T29

9

T63

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T64

2

T53

1

T15

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T29

1

T63

1

T64

3

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T53

2

T15

5

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T2

1

T63

2

T53

2

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T2

1

T29

3

T63

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T2

1

T63

1

T15

5

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T2

1

T53

2

T67

2

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T2

1

T64

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T2

1

T29

2

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T29

2

T67

2

T15

2

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T67

2

T15

6

T22

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T2

2

T29

1

T63

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T29

1

T64

2

T53

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T63

2

T53

1

T15

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T63

2

T64

1

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T29

2

T53

1

T67

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T2

9

T29

9

T63

9

auto[1]

1103

1

T2

11

T29

11

T63

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

527

1

T2

3

T29

6

T63

4

from_0to1

520

1

T2

4

T29

5

T63

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T2

13

T29

12

T63

6

auto[1]

1080

1

T2

7

T29

8

T63

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T2

11

T29

9

T63

12

auto[1]

1068

1

T2

9

T29

11

T63

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T2

1

T29

1

T15

3

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T64

2

T15

3

T73

4

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T63

1

T64

1

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T29

1

T64

1

T53

3

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T2

1

T63

1

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T29

1

T64

2

T53

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T63

1

T64

3

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T64

1

T67

1

T15

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T29

2

T15

7

T22

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T2

1

T53

1

T67

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T2

1

T29

2

T63

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T63

1

T64

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T2

2

T63

1

T64

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T29

3

T53

1

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T2

1

T63

2

T64

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T29

1

T15

4

T73

2