Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152078	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116761

1

T1

343

T4

2

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	140966	1			T1	421		T4	2		T5	2
values[0x0]	63718	1			T1	127		T5	1		T2	229
values[0x1]	64155	1			T1	134		T2	251		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	123146	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145693

1

T1

411

T4

2

T5

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	969	1			T1	2		T8	5		T40	3
valid_sources[0x01]	1164	1			T1	3		T63	4		T40	1
valid_sources[0x02]	1186	1			T2	11		T6	4		T28	18
valid_sources[0x03]	1446	1			T1	2		T40	3		T9	5
valid_sources[0x04]	1468	1			T56	1		T8	2		T40	2
valid_sources[0x05]	1080	1			T1	4		T3	5		T25	2
valid_sources[0x06]	840	1			T1	7		T2	17		T7	1
valid_sources[0x07]	988	1			T1	2		T8	8		T40	3
valid_sources[0x08]	1512	1			T1	6		T2	12		T8	5
valid_sources[0x09]	1135	1			T1	1		T3	2		T40	5
valid_sources[0x0a]	786	1			T1	1		T3	1		T26	1
valid_sources[0x0b]	1051	1			T1	2		T2	13		T3	1
valid_sources[0x0c]	1076	1			T1	2		T8	1		T63	2
valid_sources[0x0d]	960	1			T1	3		T8	4		T63	2
valid_sources[0x0e]	786	1			T8	5		T63	1		T40	6
valid_sources[0x0f]	1774	1			T1	2		T27	4		T40	4
valid_sources[0x10]	1033	1			T1	2		T2	20		T3	3
valid_sources[0x11]	1610	1			T1	3		T63	1		T40	3
valid_sources[0x12]	872	1			T1	1		T8	11		T40	3
valid_sources[0x13]	1459	1			T1	3		T27	1		T8	4
valid_sources[0x14]	926	1			T1	1		T8	2		T10	2
valid_sources[0x15]	823	1			T1	2		T2	14		T8	1
valid_sources[0x16]	2133	1			T1	3		T8	3		T40	4
valid_sources[0x17]	999	1			T1	2		T8	1		T40	1
valid_sources[0x18]	1099	1			T25	1		T40	3		T9	3
valid_sources[0x19]	1081	1			T1	4		T2	19		T40	3
valid_sources[0x1a]	820	1			T1	3		T56	1		T40	3
valid_sources[0x1b]	824	1			T1	6		T2	12		T8	7
valid_sources[0x1c]	844	1			T1	1		T4	1		T2	43
valid_sources[0x1d]	829	1			T1	2		T40	4		T9	8
valid_sources[0x1e]	735	1			T1	8		T7	1		T8	4
valid_sources[0x1f]	1211	1			T1	6		T8	1		T40	3
valid_sources[0x20]	779	1			T1	2		T8	2		T40	3
valid_sources[0x21]	932	1			T1	3		T2	3		T27	4
valid_sources[0x22]	1163	1			T1	3		T8	7		T40	4
valid_sources[0x23]	1069	1			T1	5		T30	1		T236	8
valid_sources[0x24]	992	1			T1	3		T8	1		T63	1
valid_sources[0x25]	1596	1			T1	3		T56	3		T8	10
valid_sources[0x26]	958	1			T1	1		T40	5		T9	5
valid_sources[0x27]	699	1			T1	2		T25	2		T7	1
valid_sources[0x28]	889	1			T1	1		T2	6		T7	1
valid_sources[0x29]	2419	1			T2	19		T7	1		T40	4
valid_sources[0x2a]	909	1			T1	2		T2	4		T3	2
valid_sources[0x2b]	816	1			T1	4		T2	6		T40	1
valid_sources[0x2c]	854	1			T1	4		T8	10		T40	4
valid_sources[0x2d]	806	1			T1	2		T7	2		T8	2
valid_sources[0x2e]	719	1			T1	2		T24	3		T40	6
valid_sources[0x2f]	843	1			T40	2		T10	3		T41	5
valid_sources[0x30]	985	1			T1	1		T25	1		T40	5
valid_sources[0x31]	1285	1			T1	3		T8	9		T63	1
valid_sources[0x32]	832	1			T1	5		T2	16		T8	9
valid_sources[0x33]	790	1			T1	2		T40	5		T10	3
valid_sources[0x34]	745	1			T1	2		T2	15		T8	6
valid_sources[0x35]	668	1			T1	2		T40	4		T9	1
valid_sources[0x36]	997	1			T1	6		T236	2		T40	2
valid_sources[0x37]	941	1			T1	1		T40	3		T9	1
valid_sources[0x38]	780	1			T1	1		T7	1		T8	1
valid_sources[0x39]	783	1			T1	2		T2	17		T8	4
valid_sources[0x3a]	999	1			T2	44		T7	1		T40	6
valid_sources[0x3b]	1483	1			T1	3		T25	3		T63	1
valid_sources[0x3c]	965	1			T1	6		T2	12		T27	1
valid_sources[0x3d]	1074	1			T1	3		T8	4		T63	1
valid_sources[0x3e]	1489	1			T1	3		T6	150		T7	1
valid_sources[0x3f]	1027	1			T8	10		T63	4		T40	4
valid_sources[0x40]	1242	1			T1	6		T8	3		T40	6
valid_sources[0x41]	996	1			T1	5		T8	3		T40	3
valid_sources[0x42]	1185	1			T1	5		T25	1		T40	5
valid_sources[0x43]	1050	1			T1	5		T56	1		T63	2
valid_sources[0x44]	1219	1			T1	6		T2	20		T8	9
valid_sources[0x45]	1063	1			T1	4		T8	1		T40	4
valid_sources[0x46]	844	1			T1	2		T27	2		T8	2
valid_sources[0x47]	907	1			T1	4		T63	1		T40	1
valid_sources[0x48]	1245	1			T5	2		T6	5		T7	1
valid_sources[0x49]	912	1			T8	7		T9	4		T53	1
valid_sources[0x4a]	911	1			T1	5		T3	2		T8	2
valid_sources[0x4b]	824	1			T1	1		T2	7		T25	1
valid_sources[0x4c]	1072	1			T1	3		T6	25		T8	8
valid_sources[0x4d]	1026	1			T1	3		T8	6		T9	4
valid_sources[0x4e]	1022	1			T2	46		T28	26		T8	8
valid_sources[0x4f]	763	1			T1	2		T8	6		T236	4
valid_sources[0x50]	1335	1			T1	3		T8	6		T63	1
valid_sources[0x51]	1365	1			T8	1		T63	4		T40	2
valid_sources[0x52]	730	1			T1	4		T3	1		T8	6
valid_sources[0x53]	1020	1			T1	3		T63	3		T40	3
valid_sources[0x54]	1197	1			T1	2		T27	1		T63	1
valid_sources[0x55]	855	1			T1	1		T2	2		T8	2
valid_sources[0x56]	1141	1			T1	6		T8	1		T63	1
valid_sources[0x57]	877	1			T1	1		T2	4		T25	1
valid_sources[0x58]	990	1			T1	2		T40	5		T9	2
valid_sources[0x59]	1012	1			T1	1		T40	4		T10	3
valid_sources[0x5a]	1018	1			T1	1		T8	2		T63	1
valid_sources[0x5b]	758	1			T1	2		T2	8		T40	2
valid_sources[0x5c]	986	1			T1	7		T27	1		T8	5
valid_sources[0x5d]	1042	1			T1	2		T7	1		T236	1
valid_sources[0x5e]	1217	1			T1	1		T2	27		T27	3
valid_sources[0x5f]	834	1			T1	5		T2	1		T8	7
valid_sources[0x60]	789	1			T2	20		T8	2		T10	2
valid_sources[0x61]	833	1			T1	5		T8	1		T40	3
valid_sources[0x62]	989	1			T1	2		T27	2		T8	1
valid_sources[0x63]	830	1			T1	9		T6	66		T40	3
valid_sources[0x64]	1302	1			T1	5		T25	2		T8	1
valid_sources[0x65]	922	1			T1	1		T8	2		T40	3
valid_sources[0x66]	902	1			T1	2		T2	27		T3	1
valid_sources[0x67]	856	1			T1	6		T2	9		T8	9
valid_sources[0x68]	892	1			T1	1		T3	4		T25	2
valid_sources[0x69]	982	1			T1	3		T25	3		T40	7
valid_sources[0x6a]	952	1			T1	4		T63	2		T40	5
valid_sources[0x6b]	847	1			T2	5		T8	2		T63	2
valid_sources[0x6c]	1137	1			T1	3		T25	1		T8	8
valid_sources[0x6d]	1058	1			T1	4		T63	2		T40	1
valid_sources[0x6e]	758	1			T1	2		T40	2		T9	2
valid_sources[0x6f]	929	1			T1	3		T2	6		T8	2
valid_sources[0x70]	1013	1			T1	2		T8	3		T40	1
valid_sources[0x71]	957	1			T1	2		T2	28		T3	3
valid_sources[0x72]	740	1			T1	3		T25	1		T8	5
valid_sources[0x73]	871	1			T1	4		T63	3		T40	4
valid_sources[0x74]	795	1			T2	16		T8	2		T40	2
valid_sources[0x75]	847	1			T1	3		T2	31		T8	2
valid_sources[0x76]	993	1			T1	4		T8	4		T63	1
valid_sources[0x77]	994	1			T8	3		T40	1		T10	2
valid_sources[0x78]	1004	1			T25	2		T8	1		T40	6
valid_sources[0x79]	748	1			T1	3		T8	7		T40	4
valid_sources[0x7a]	978	1			T1	1		T8	3		T63	1
valid_sources[0x7b]	1834	1			T1	1		T2	9		T40	2
valid_sources[0x7c]	880	1			T1	3		T8	12		T40	2
valid_sources[0x7d]	985	1			T1	2		T2	2		T40	2
valid_sources[0x7e]	837	1			T1	2		T7	1		T40	3
valid_sources[0x7f]	1363	1			T30	1		T8	7		T40	1
valid_sources[0x80]	1184	1			T1	4		T2	2		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63808

1

T1

206

T4

2

T5

2

values[0x0]

all_enables

biggest_size

31067

1

T1

75

T5

1

T2

92

values[0x1]

all_enables

biggest_size

21886

1

T1

62

T2

57

T3

2