Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T24,T26,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T24,T26,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T24,T26,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T24,T26
1	0	Covered	T1,T4,T5
1	1	Covered	T24,T26,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T26,T47
0	1	Covered	T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T26,T47
0	1	Covered	T24,T26,T47
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T26,T47
1	-	Covered	T24,T26,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T26,T47
DetectSt	168	Covered	T24,T26,T47
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T24,T26,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T26,T47
DebounceSt->IdleSt	163	Covered	T48,T75,T110
DetectSt->IdleSt	186	Covered	T78
DetectSt->StableSt	191	Covered	T24,T26,T47
IdleSt->DebounceSt	148	Covered	T24,T26,T47
StableSt->IdleSt	206	Covered	T24,T26,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T26,T47
0	1	Covered	T24,T26,T47
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T26,T47
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T26,T47
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T26,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T110,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T26,T47
DetectSt	-	-	-	-	1	-	-	Covered	T78
DetectSt	-	-	-	-	0	1	-	Covered	T24,T26,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T26,T47
StableSt	-	-	-	-	-	-	0	Covered	T24,T26,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	232	0	0
CntIncr_A	7034196	206063	0	0
CntNoWrap_A	7034196	6347855	0	0
DetectStDropOut_A	7034196	1	0	0
DetectedOut_A	7034196	703	0	0
DetectedPulseOut_A	7034196	106	0	0
DisabledIdleSt_A	7034196	6136071	0	0
DisabledNoDetection_A	7034196	6138479	0	0
EnterDebounceSt_A	7034196	128	0	0
EnterDetectSt_A	7034196	107	0	0
EnterStableSt_A	7034196	106	0	0
PulseIsPulse_A	7034196	106	0	0
StayInStableSt	7034196	597	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7034196	7089	0	0
gen_low_level_sva.LowLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	105	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	232	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	4	0	0
T22	0	4	0	0
T24	716	2	0	0
T25	496	0	0	0
T26	759	4	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	2	0	0
T48	0	3	0	0
T50	0	4	0	0
T51	0	4	0	0
T56	2009	0	0	0
T86	0	2	0	0
T87	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	206063	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	130	0	0
T22	0	157	0	0
T24	716	81	0	0
T25	496	0	0	0
T26	759	184	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	84	0	0
T48	0	93	0	0
T50	0	122	0	0
T51	0	53701	0	0
T56	2009	0	0	0
T86	0	86	0	0
T87	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347855	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	313	0	0
T25	496	95	0	0
T26	759	354	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1	0	0
T78	21125	1	0	0
T107	906	0	0	0
T108	522	0	0	0
T109	502	0	0	0
T110	707	0	0	0
T111	501	0	0	0
T112	424	0	0	0
T113	38552	0	0	0
T114	522	0	0	0
T115	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	703	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	12	0	0
T22	0	12	0	0
T24	716	9	0	0
T25	496	0	0	0
T26	759	20	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	3	0	0
T48	0	1	0	0
T50	0	14	0	0
T51	0	20	0	0
T56	2009	0	0	0
T86	0	6	0	0
T87	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	106	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	2	0	0
T22	0	2	0	0
T24	716	1	0	0
T25	496	0	0	0
T26	759	2	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T56	2009	0	0	0
T86	0	1	0	0
T87	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6136071	0	0
T1	35063	34567	0	0
T2	13507	6261	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	187	0	0
T25	496	95	0	0
T26	759	76	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6138479	0	0
T1	35063	34582	0	0
T2	13507	6280	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	188	0	0
T25	496	96	0	0
T26	759	77	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	128	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	2	0	0
T22	0	2	0	0
T24	716	1	0	0
T25	496	0	0	0
T26	759	2	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T56	2009	0	0	0
T86	0	1	0	0
T87	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	107	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	2	0	0
T22	0	2	0	0
T24	716	1	0	0
T25	496	0	0	0
T26	759	2	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T56	2009	0	0	0
T86	0	1	0	0
T87	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	106	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	2	0	0
T22	0	2	0	0
T24	716	1	0	0
T25	496	0	0	0
T26	759	2	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T56	2009	0	0	0
T86	0	1	0	0
T87	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	106	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	2	0	0
T22	0	2	0	0
T24	716	1	0	0
T25	496	0	0	0
T26	759	2	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T56	2009	0	0	0
T86	0	1	0	0
T87	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	597	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	10	0	0
T22	0	10	0	0
T24	716	8	0	0
T25	496	0	0	0
T26	759	18	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	2	0	0
T50	0	12	0	0
T51	0	18	0	0
T56	2009	0	0	0
T84	0	4	0	0
T86	0	5	0	0
T87	0	11	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	7089	0	0
T1	35063	12	0	0
T2	13507	39	0	0
T3	1601	8	0	0
T4	425	3	0	0
T5	427	3	0	0
T6	41075	14	0	0
T24	716	3	0	0
T25	496	6	0	0
T26	759	3	0	0
T27	493	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	105	0	0
T7	525	0	0	0
T8	41344	0	0	0
T17	0	2	0	0
T22	0	2	0	0
T24	716	1	0	0
T25	496	0	0	0
T26	759	2	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T56	2009	0	0	0
T86	0	1	0	0
T87	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T6,T13,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Unreachable
1	0	Covered	T3,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T7
DetectSt	168	Covered	T3,T6,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T7
DebounceSt->IdleSt	163	Covered	T6,T13,T32
DetectSt->IdleSt	186	Covered	T6,T13,T84
DetectSt->StableSt	191	Covered	T3,T6,T7
IdleSt->DebounceSt	148	Covered	T3,T6,T7
StableSt->IdleSt	206	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T13,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T6,T13,T84
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	190	0	0
CntIncr_A	7034196	6007	0	0
CntNoWrap_A	7034196	6347897	0	0
DetectStDropOut_A	7034196	19	0	0
DetectedOut_A	7034196	8654	0	0
DetectedPulseOut_A	7034196	54	0	0
DisabledIdleSt_A	7034196	5525951	0	0
DisabledNoDetection_A	7034196	5528403	0	0
EnterDebounceSt_A	7034196	118	0	0
EnterDetectSt_A	7034196	73	0	0
EnterStableSt_A	7034196	54	0	0
PulseIsPulse_A	7034196	54	0	0
StayInStableSt	7034196	8600	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7034196	7089	0	0
gen_low_level_sva.LowLevelEvent_A	7034196	6350539	0	0
gen_sticky_sva.StableStDropOut_A	7034196	345534	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	190	0	0
T3	1601	2	0	0
T6	41075	7	0	0
T7	525	2	0	0
T13	0	3	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T33	0	6	0	0
T34	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6007	0	0
T3	1601	23	0	0
T6	41075	88	0	0
T7	525	26	0	0
T13	0	188	0	0
T22	0	84	0	0
T23	0	11	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	41	0	0
T32	0	94	0	0
T33	0	126	0	0
T34	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347897	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1198	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36947	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	19	0	0
T6	41075	1	0	0
T7	525	0	0	0
T13	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T56	2009	0	0	0
T84	0	1	0	0
T113	0	2	0	0
T117	0	4	0	0
T120	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	8654	0	0
T3	1601	3	0	0
T6	41075	53	0	0
T7	525	10	0	0
T22	0	139	0	0
T23	0	4	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	5	0	0
T32	0	1	0	0
T33	0	400	0	0
T81	0	114	0	0
T116	0	603	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T3	1601	1	0	0
T6	41075	1	0	0
T7	525	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T81	0	2	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5525951	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1030	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36164	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5528403	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1031	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36175	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	118	0	0
T3	1601	1	0	0
T6	41075	5	0	0
T7	525	1	0	0
T13	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T34	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	73	0	0
T3	1601	1	0	0
T6	41075	2	0	0
T7	525	1	0	0
T13	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T81	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T3	1601	1	0	0
T6	41075	1	0	0
T7	525	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T81	0	2	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T3	1601	1	0	0
T6	41075	1	0	0
T7	525	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T81	0	2	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	8600	0	0
T3	1601	2	0	0
T6	41075	52	0	0
T7	525	9	0	0
T22	0	138	0	0
T23	0	3	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	4	0	0
T33	0	397	0	0
T81	0	112	0	0
T84	0	420	0	0
T116	0	602	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	7089	0	0
T1	35063	12	0	0
T2	13507	39	0	0
T3	1601	8	0	0
T4	425	3	0	0
T5	427	3	0	0
T6	41075	14	0	0
T24	716	3	0	0
T25	496	6	0	0
T26	759	3	0	0
T27	493	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	345534	0	0
T3	1601	119	0	0
T6	41075	232	0	0
T7	525	54	0	0
T22	0	43	0	0
T23	0	124	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	124	0	0
T32	0	137	0	0
T33	0	269	0	0
T81	0	43575	0	0
T116	0	191	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T4,T5,T2
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T22
0	1	Covered	T33,T34,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T22
0	1	Unreachable
1	0	Covered	T3,T6,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T7
DetectSt	168	Covered	T3,T6,T22
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T6,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T22
DebounceSt->IdleSt	163	Covered	T7,T13,T23
DetectSt->IdleSt	186	Covered	T33,T34,T81
DetectSt->StableSt	191	Covered	T3,T6,T22
IdleSt->DebounceSt	148	Covered	T3,T6,T7
StableSt->IdleSt	206	Covered	T3,T6,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T22
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T13,T23
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T33,T34,T81
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T22
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	184	0	0
CntIncr_A	7034196	241874	0	0
CntNoWrap_A	7034196	6347903	0	0
DetectStDropOut_A	7034196	19	0	0
DetectedOut_A	7034196	290265	0	0
DetectedPulseOut_A	7034196	50	0	0
DisabledIdleSt_A	7034196	5525951	0	0
DisabledNoDetection_A	7034196	5528403	0	0
EnterDebounceSt_A	7034196	116	0	0
EnterDetectSt_A	7034196	69	0	0
EnterStableSt_A	7034196	50	0	0
PulseIsPulse_A	7034196	50	0	0
StayInStableSt	7034196	290215	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_sticky_sva.StableStDropOut_A	7034196	267072	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	184	0	0
T3	1601	2	0	0
T6	41075	4	0	0
T7	525	1	0	0
T13	0	2	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	8	0	0
T34	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	241874	0	0
T3	1601	84	0	0
T6	41075	118	0	0
T7	525	33	0	0
T13	0	84	0	0
T22	0	43	0	0
T23	0	68	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	85	0	0
T32	0	95	0	0
T33	0	184	0	0
T34	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347903	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1198	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36950	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	19	0	0
T33	1334	1	0	0
T34	1397	1	0	0
T72	16883	0	0	0
T81	0	2	0	0
T83	545	0	0	0
T124	0	4	0	0
T125	0	1	0	0
T126	0	2	0	0
T127	0	6	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	619	0	0	0
T131	440	0	0	0
T132	697	0	0	0
T133	524	0	0	0
T134	1192	0	0	0
T135	681	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	290265	0	0
T3	1601	27	0	0
T6	41075	318	0	0
T7	525	0	0	0
T22	0	60	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	62	0	0
T32	0	202	0	0
T33	0	236	0	0
T81	0	1913	0	0
T84	0	59	0	0
T117	0	548	0	0
T118	0	944	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	50	0	0
T3	1601	1	0	0
T6	41075	2	0	0
T7	525	0	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T81	0	1	0	0
T84	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5525951	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1030	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36164	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5528403	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1031	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36175	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	116	0	0
T3	1601	1	0	0
T6	41075	2	0	0
T7	525	1	0	0
T13	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	4	0	0
T34	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	69	0	0
T3	1601	1	0	0
T6	41075	2	0	0
T7	525	0	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	4	0	0
T34	0	1	0	0
T81	0	3	0	0
T84	0	1	0	0
T117	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	50	0	0
T3	1601	1	0	0
T6	41075	2	0	0
T7	525	0	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T81	0	1	0	0
T84	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	50	0	0
T3	1601	1	0	0
T6	41075	2	0	0
T7	525	0	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T81	0	1	0	0
T84	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	290215	0	0
T3	1601	26	0	0
T6	41075	316	0	0
T7	525	0	0	0
T22	0	59	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	61	0	0
T32	0	201	0	0
T33	0	233	0	0
T81	0	1912	0	0
T84	0	58	0	0
T117	0	547	0	0
T118	0	942	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	267072	0	0
T3	1601	42	0	0
T6	41075	314	0	0
T7	525	0	0	0
T22	0	153	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	29	0	0
T32	0	83	0	0
T33	0	333	0	0
T81	0	25	0	0
T84	0	125	0	0
T117	0	258094	0	0
T118	0	154	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T13
0	1	Covered	T22,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T13
0	1	Unreachable
1	0	Covered	T3,T6,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T7
DetectSt	168	Covered	T3,T6,T13
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T6,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T13
DebounceSt->IdleSt	163	Covered	T6,T7,T32
DetectSt->IdleSt	186	Covered	T22,T81,T82
DetectSt->StableSt	191	Covered	T3,T6,T13
IdleSt->DebounceSt	148	Covered	T3,T6,T7
StableSt->IdleSt	206	Covered	T3,T6,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T13
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T7,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T22,T81,T82
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T13
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	173	0	0
CntIncr_A	7034196	45868	0	0
CntNoWrap_A	7034196	6347914	0	0
DetectStDropOut_A	7034196	9	0	0
DetectedOut_A	7034196	245513	0	0
DetectedPulseOut_A	7034196	53	0	0
DisabledIdleSt_A	7034196	5525951	0	0
DisabledNoDetection_A	7034196	5528403	0	0
EnterDebounceSt_A	7034196	112	0	0
EnterDetectSt_A	7034196	62	0	0
EnterStableSt_A	7034196	53	0	0
PulseIsPulse_A	7034196	53	0	0
StayInStableSt	7034196	245460	0	0
gen_high_event_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_sticky_sva.StableStDropOut_A	7034196	336793	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	173	0	0
T3	1601	2	0	0
T6	41075	6	0	0
T7	525	1	0	0
T13	0	2	0	0
T22	0	4	0	0
T23	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	9	0	0
T34	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	45868	0	0
T3	1601	77	0	0
T6	41075	291	0	0
T7	525	20	0	0
T13	0	68	0	0
T22	0	92	0	0
T23	0	65	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	19	0	0
T32	0	166	0	0
T33	0	135	0	0
T34	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347914	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1198	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36948	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	9	0	0
T22	15707	2	0	0
T23	1101	0	0	0
T70	4521	0	0	0
T73	30117	0	0	0
T81	0	1	0	0
T82	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	2	0	0
T139	404	0	0	0
T140	402	0	0	0
T141	424	0	0	0
T142	521	0	0	0
T143	410	0	0	0
T144	8401	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	245513	0	0
T3	1601	56	0	0
T6	41075	66	0	0
T7	525	0	0	0
T13	0	153	0	0
T23	0	13	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	3	0	0
T34	0	64	0	0
T81	0	8	0	0
T84	0	280	0	0
T113	0	9884	0	0
T116	0	453	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	53	0	0
T3	1601	1	0	0
T6	41075	1	0	0
T7	525	0	0	0
T13	0	1	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T81	0	2	0	0
T84	0	2	0	0
T113	0	1	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5525951	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1030	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36164	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5528403	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1031	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36175	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	112	0	0
T3	1601	1	0	0
T6	41075	5	0	0
T7	525	1	0	0
T13	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	9	0	0
T34	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	62	0	0
T3	1601	1	0	0
T6	41075	1	0	0
T7	525	0	0	0
T13	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T81	0	3	0	0
T84	0	2	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	53	0	0
T3	1601	1	0	0
T6	41075	1	0	0
T7	525	0	0	0
T13	0	1	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T81	0	2	0	0
T84	0	2	0	0
T113	0	1	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	53	0	0
T3	1601	1	0	0
T6	41075	1	0	0
T7	525	0	0	0
T13	0	1	0	0
T23	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T81	0	2	0	0
T84	0	2	0	0
T113	0	1	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	245460	0	0
T3	1601	55	0	0
T6	41075	65	0	0
T7	525	0	0	0
T13	0	152	0	0
T23	0	12	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	2	0	0
T34	0	63	0	0
T81	0	6	0	0
T84	0	278	0	0
T113	0	9883	0	0
T116	0	452	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	336793	0	0
T3	1601	31	0	0
T6	41075	193	0	0
T7	525	0	0	0
T13	0	66	0	0
T23	0	70	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T30	422	0	0	0
T31	0	155	0	0
T34	0	40	0	0
T81	0	43596	0	0
T84	0	693	0	0
T113	0	70	0	0
T116	0	384	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T15,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T9,T15,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T15,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T9,T15,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T15,T19
0	1	Covered	T145
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T15,T19
0	1	Covered	T9,T19,T43
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T15,T19
1	-	Covered	T9,T19,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T15,T19
DetectSt	168	Covered	T9,T15,T19
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T15,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T15,T19
DebounceSt->IdleSt	163	Covered	T75,T146,T147
DetectSt->IdleSt	186	Covered	T145
DetectSt->StableSt	191	Covered	T9,T15,T19
IdleSt->DebounceSt	148	Covered	T9,T15,T19
StableSt->IdleSt	206	Covered	T9,T15,T19

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T15,T19
0	1	Covered	T9,T15,T19
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T15,T19
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T15,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T15,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T147
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T15,T19
DetectSt	-	-	-	-	1	-	-	Covered	T145
DetectSt	-	-	-	-	0	1	-	Covered	T9,T15,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T19,T43
StableSt	-	-	-	-	-	-	0	Covered	T9,T15,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	86	0	0
CntIncr_A	7034196	48891	0	0
CntNoWrap_A	7034196	6348001	0	0
DetectStDropOut_A	7034196	1	0	0
DetectedOut_A	7034196	113160	0	0
DetectedPulseOut_A	7034196	41	0	0
DisabledIdleSt_A	7034196	6125644	0	0
DisabledNoDetection_A	7034196	6128040	0	0
EnterDebounceSt_A	7034196	45	0	0
EnterDetectSt_A	7034196	42	0	0
EnterStableSt_A	7034196	41	0	0
PulseIsPulse_A	7034196	41	0	0
StayInStableSt	7034196	113091	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	86	0	0
T9	11689	2	0	0
T10	14540	0	0	0
T15	0	2	0	0
T19	0	2	0	0
T21	0	2	0	0
T41	4865	0	0	0
T43	0	2	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	4	0	0
T130	0	2	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	1671	0	0	0
T152	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	48891	0	0
T9	11689	24	0	0
T10	14540	0	0	0
T15	0	30	0	0
T19	0	99	0	0
T21	0	46716	0	0
T41	4865	0	0	0
T43	0	18	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	132	0	0
T130	0	60	0	0
T148	0	86	0	0
T149	0	20	0	0
T150	0	99	0	0
T151	1671	0	0	0
T152	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6348001	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1	0	0
T145	3044	1	0	0
T146	23166	0	0	0
T153	494	0	0	0
T154	5455	0	0	0
T155	402	0	0	0
T156	11571	0	0	0
T157	926	0	0	0
T158	6209	0	0	0
T159	569	0	0	0
T160	33736	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	113160	0	0
T9	11689	2	0	0
T10	14540	0	0	0
T15	0	38	0	0
T19	0	41	0	0
T21	0	110503	0	0
T41	4865	0	0	0
T43	0	39	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	239	0	0
T130	0	42	0	0
T148	0	61	0	0
T149	0	38	0	0
T150	0	40	0	0
T151	1671	0	0	0
T152	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	41	0	0
T9	11689	1	0	0
T10	14540	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T41	4865	0	0	0
T43	0	1	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	2	0	0
T130	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	1671	0	0	0
T152	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6125644	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36263	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6128040	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36273	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	45	0	0
T9	11689	1	0	0
T10	14540	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T41	4865	0	0	0
T43	0	1	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	2	0	0
T130	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	1671	0	0	0
T152	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	42	0	0
T9	11689	1	0	0
T10	14540	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T41	4865	0	0	0
T43	0	1	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	2	0	0
T130	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	1671	0	0	0
T152	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	41	0	0
T9	11689	1	0	0
T10	14540	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T41	4865	0	0	0
T43	0	1	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	2	0	0
T130	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	1671	0	0	0
T152	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	41	0	0
T9	11689	1	0	0
T10	14540	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T41	4865	0	0	0
T43	0	1	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	2	0	0
T130	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	1671	0	0	0
T152	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	113091	0	0
T9	11689	1	0	0
T10	14540	0	0	0
T15	0	36	0	0
T19	0	40	0	0
T21	0	110501	0	0
T41	4865	0	0	0
T43	0	38	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	236	0	0
T130	0	40	0	0
T148	0	59	0	0
T149	0	36	0	0
T150	0	38	0	0
T151	1671	0	0	0
T152	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	12	0	0
T9	11689	1	0	0
T10	14540	0	0	0
T19	0	1	0	0
T41	4865	0	0	0
T43	0	1	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T85	0	1	0	0
T97	0	1	0	0
T151	1671	0	0	0
T152	422	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T11,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T17
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T17,T19
0	1	Covered	T77,T159
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T17,T19
0	1	Covered	T19,T149,T150
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T17,T19
1	-	Covered	T19,T149,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T17,T19
DetectSt	168	Covered	T11,T17,T19
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T17,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T17,T19
DebounceSt->IdleSt	163	Covered	T85,T75,T166
DetectSt->IdleSt	186	Covered	T77,T159
DetectSt->StableSt	191	Covered	T11,T17,T19
IdleSt->DebounceSt	148	Covered	T11,T17,T19
StableSt->IdleSt	206	Covered	T17,T19,T149

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T17,T19
0	1	Covered	T11,T17,T19
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T17,T19
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T17,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T17,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T166,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T17,T19
DetectSt	-	-	-	-	1	-	-	Covered	T77,T159
DetectSt	-	-	-	-	0	1	-	Covered	T11,T17,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T149,T150
StableSt	-	-	-	-	-	-	0	Covered	T11,T17,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	127	0	0
CntIncr_A	7034196	54683	0	0
CntNoWrap_A	7034196	6347960	0	0
DetectStDropOut_A	7034196	2	0	0
DetectedOut_A	7034196	5330	0	0
DetectedPulseOut_A	7034196	58	0	0
DisabledIdleSt_A	7034196	6227835	0	0
DisabledNoDetection_A	7034196	6230234	0	0
EnterDebounceSt_A	7034196	67	0	0
EnterDetectSt_A	7034196	60	0	0
EnterStableSt_A	7034196	58	0	0
PulseIsPulse_A	7034196	58	0	0
StayInStableSt	7034196	5248	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7034196	2742	0	0
gen_low_level_sva.LowLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	127	0	0
T11	841	2	0	0
T12	7398	0	0	0
T17	0	4	0	0
T19	0	4	0	0
T59	813	0	0	0
T62	494	0	0	0
T66	2127	0	0	0
T67	502	0	0	0
T81	0	2	0	0
T85	0	3	0	0
T87	0	4	0	0
T149	0	2	0	0
T150	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	427	0	0	0
T170	437	0	0	0
T171	422	0	0	0
T172	421	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54683	0	0
T11	841	68	0	0
T12	7398	0	0	0
T17	0	99	0	0
T19	0	198	0	0
T59	813	0	0	0
T62	494	0	0	0
T66	2127	0	0	0
T67	502	0	0	0
T81	0	20	0	0
T85	0	132	0	0
T87	0	116	0	0
T149	0	20	0	0
T150	0	99	0	0
T167	0	92	0	0
T168	0	67	0	0
T169	427	0	0	0
T170	437	0	0	0
T171	422	0	0	0
T172	421	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347960	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	2	0	0
T77	498	1	0	0
T89	44388	0	0	0
T90	5435	0	0	0
T116	9183	0	0	0
T159	0	1	0	0
T173	489	0	0	0
T174	404	0	0	0
T175	410	0	0	0
T176	522	0	0	0
T177	29208	0	0	0
T178	10466	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5330	0	0
T11	841	363	0	0
T12	7398	0	0	0
T17	0	176	0	0
T19	0	166	0	0
T59	813	0	0	0
T62	494	0	0	0
T66	2127	0	0	0
T67	502	0	0	0
T81	0	1	0	0
T85	0	43	0	0
T87	0	299	0	0
T149	0	12	0	0
T150	0	9	0	0
T167	0	219	0	0
T168	0	144	0	0
T169	427	0	0	0
T170	437	0	0	0
T171	422	0	0	0
T172	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	58	0	0
T11	841	1	0	0
T12	7398	0	0	0
T17	0	2	0	0
T19	0	2	0	0
T59	813	0	0	0
T62	494	0	0	0
T66	2127	0	0	0
T67	502	0	0	0
T81	0	1	0	0
T85	0	1	0	0
T87	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	427	0	0	0
T170	437	0	0	0
T171	422	0	0	0
T172	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6227835	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6230234	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	67	0	0
T11	841	1	0	0
T12	7398	0	0	0
T17	0	2	0	0
T19	0	2	0	0
T59	813	0	0	0
T62	494	0	0	0
T66	2127	0	0	0
T67	502	0	0	0
T81	0	1	0	0
T85	0	2	0	0
T87	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	427	0	0	0
T170	437	0	0	0
T171	422	0	0	0
T172	421	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	60	0	0
T11	841	1	0	0
T12	7398	0	0	0
T17	0	2	0	0
T19	0	2	0	0
T59	813	0	0	0
T62	494	0	0	0
T66	2127	0	0	0
T67	502	0	0	0
T81	0	1	0	0
T85	0	1	0	0
T87	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	427	0	0	0
T170	437	0	0	0
T171	422	0	0	0
T172	421	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	58	0	0
T11	841	1	0	0
T12	7398	0	0	0
T17	0	2	0	0
T19	0	2	0	0
T59	813	0	0	0
T62	494	0	0	0
T66	2127	0	0	0
T67	502	0	0	0
T81	0	1	0	0
T85	0	1	0	0
T87	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	427	0	0	0
T170	437	0	0	0
T171	422	0	0	0
T172	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	58	0	0
T11	841	1	0	0
T12	7398	0	0	0
T17	0	2	0	0
T19	0	2	0	0
T59	813	0	0	0
T62	494	0	0	0
T66	2127	0	0	0
T67	502	0	0	0
T81	0	1	0	0
T85	0	1	0	0
T87	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	427	0	0	0
T170	437	0	0	0
T171	422	0	0	0
T172	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5248	0	0
T11	841	361	0	0
T12	7398	0	0	0
T17	0	172	0	0
T19	0	163	0	0
T59	813	0	0	0
T62	494	0	0	0
T66	2127	0	0	0
T67	502	0	0	0
T85	0	42	0	0
T87	0	296	0	0
T149	0	11	0	0
T150	0	8	0	0
T167	0	217	0	0
T168	0	142	0	0
T169	427	0	0	0
T170	437	0	0	0
T171	422	0	0	0
T172	421	0	0	0
T179	0	87	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	2742	0	0
T2	13507	33	0	0
T3	1601	0	0	0
T4	425	2	0	0
T5	427	3	0	0
T6	41075	6	0	0
T7	525	0	0	0
T24	716	0	0	0
T25	496	6	0	0
T26	759	0	0	0
T27	493	5	0	0
T28	0	4	0	0
T29	0	7	0	0
T30	0	3	0	0
T63	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	33	0	0
T19	2836	1	0	0
T20	26947	0	0	0
T21	204346	0	0	0
T49	5617	0	0	0
T81	0	1	0	0
T85	0	1	0	0
T87	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	492	0	0	0
T184	654	0	0	0
T185	6049	0	0	0
T186	524	0	0	0
T187	412	0	0	0
T188	402	0	0	0