Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T13,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T13,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T13,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T15
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T13,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T19
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T19
0	1	Covered	T2,T13,T21
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T19
1	-	Covered	T2,T13,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T19
DetectSt	168	Covered	T2,T13,T19
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T13,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T19
DebounceSt->IdleSt	163	Covered	T75,T164,T189
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T13,T19
IdleSt->DebounceSt	148	Covered	T2,T13,T19
StableSt->IdleSt	206	Covered	T2,T13,T19

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T13,T19
0	1	Covered	T2,T13,T19
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T19
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T164,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T19
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T13,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T13,T21
StableSt	-	-	-	-	-	-	0	Covered	T2,T13,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	87	0	0
CntIncr_A	7034196	49071	0	0
CntNoWrap_A	7034196	6348000	0	0
DetectStDropOut_A	7034196	0	0	0
DetectedOut_A	7034196	20384	0	0
DetectedPulseOut_A	7034196	42	0	0
DisabledIdleSt_A	7034196	6127517	0	0
DisabledNoDetection_A	7034196	6129916	0	0
EnterDebounceSt_A	7034196	45	0	0
EnterDetectSt_A	7034196	42	0	0
EnterStableSt_A	7034196	42	0	0
PulseIsPulse_A	7034196	42	0	0
StayInStableSt	7034196	20321	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	87	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	2	0	0
T19	0	2	0	0
T21	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	2	0	0
T75	0	1	0	0
T117	0	2	0	0
T161	0	2	0	0
T182	0	2	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	49071	0	0
T2	13507	58	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	20	0	0
T19	0	99	0	0
T21	0	46716	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	18	0	0
T75	0	16	0	0
T117	0	81	0	0
T161	0	46	0	0
T182	0	46	0	0
T190	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6348000	0	0
T1	35063	34567	0	0
T2	13507	6260	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	20384	0	0
T2	13507	13	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	40	0	0
T19	0	162	0	0
T21	0	16986	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	59	0	0
T117	0	41	0	0
T161	0	188	0	0
T182	0	40	0	0
T190	0	44	0	0
T191	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	42	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	1	0	0
T117	0	1	0	0
T161	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6127517	0	0
T1	35063	34567	0	0
T2	13507	5696	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6129916	0	0
T1	35063	34582	0	0
T2	13507	5715	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	45	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	1	0	0
T75	0	1	0	0
T117	0	1	0	0
T161	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	42	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	1	0	0
T117	0	1	0	0
T161	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	42	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	1	0	0
T117	0	1	0	0
T161	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	42	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	1	0	0
T117	0	1	0	0
T161	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	20321	0	0
T2	13507	12	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	39	0	0
T19	0	160	0	0
T21	0	16985	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	58	0	0
T117	0	39	0	0
T161	0	186	0	0
T182	0	38	0	0
T190	0	42	0	0
T191	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	20	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	1	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	1	0	0
T97	0	1	0	0
T121	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T9
1	-	Covered	T2,T6,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T9
DetectSt	168	Covered	T2,T6,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T6,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T9
DebounceSt->IdleSt	163	Covered	T75,T166,T192
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T6,T9
IdleSt->DebounceSt	148	Covered	T2,T6,T9
StableSt->IdleSt	206	Covered	T2,T6,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T166
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	110	0	0
CntIncr_A	7034196	98024	0	0
CntNoWrap_A	7034196	6347977	0	0
DetectStDropOut_A	7034196	0	0	0
DetectedOut_A	7034196	4707	0	0
DetectedPulseOut_A	7034196	54	0	0
DisabledIdleSt_A	7034196	6127879	0	0
DisabledNoDetection_A	7034196	6130289	0	0
EnterDebounceSt_A	7034196	57	0	0
EnterDetectSt_A	7034196	54	0	0
EnterStableSt_A	7034196	54	0	0
PulseIsPulse_A	7034196	54	0	0
StayInStableSt	7034196	4629	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7034196	3184	0	0
gen_low_level_sva.LowLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	110	0	0
T2	13507	4	0	0
T3	1601	0	0	0
T6	41075	4	0	0
T7	525	0	0	0
T9	0	2	0	0
T11	0	4	0	0
T21	0	4	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	4	0	0
T87	0	2	0	0
T130	0	2	0	0
T149	0	2	0	0
T193	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	98024	0	0
T2	13507	116	0	0
T3	1601	0	0	0
T6	41075	152	0	0
T7	525	0	0	0
T9	0	24	0	0
T11	0	136	0	0
T21	0	93432	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	132	0	0
T87	0	58	0	0
T130	0	60	0	0
T149	0	20	0	0
T193	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347977	0	0
T1	35063	34567	0	0
T2	13507	6258	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36950	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	4707	0	0
T2	13507	371	0	0
T3	1601	0	0	0
T6	41075	283	0	0
T7	525	0	0	0
T9	0	67	0	0
T11	0	82	0	0
T21	0	83	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	190	0	0
T87	0	146	0	0
T130	0	149	0	0
T149	0	39	0	0
T193	0	96	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T21	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	2	0	0
T87	0	1	0	0
T130	0	1	0	0
T149	0	1	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6127879	0	0
T1	35063	34567	0	0
T2	13507	5696	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36263	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6130289	0	0
T1	35063	34582	0	0
T2	13507	5715	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36273	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	57	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T21	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	2	0	0
T87	0	1	0	0
T130	0	1	0	0
T149	0	1	0	0
T193	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T21	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	2	0	0
T87	0	1	0	0
T130	0	1	0	0
T149	0	1	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T21	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	2	0	0
T87	0	1	0	0
T130	0	1	0	0
T149	0	1	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T21	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	2	0	0
T87	0	1	0	0
T130	0	1	0	0
T149	0	1	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	4629	0	0
T2	13507	368	0	0
T3	1601	0	0	0
T6	41075	280	0	0
T7	525	0	0	0
T9	0	66	0	0
T11	0	79	0	0
T21	0	80	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	187	0	0
T87	0	145	0	0
T130	0	147	0	0
T149	0	37	0	0
T193	0	94	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	3184	0	0
T2	13507	33	0	0
T3	1601	0	0	0
T4	425	3	0	0
T5	427	1	0	0
T6	41075	15	0	0
T7	525	0	0	0
T24	716	0	0	0
T25	496	8	0	0
T26	759	0	0	0
T27	493	4	0	0
T28	0	3	0	0
T29	0	5	0	0
T61	0	4	0	0
T63	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	29	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	1	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T13,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T13,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T13,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T1,T4,T5
1	1	Covered	T13,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T15,T19,T150
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T15,T17
1	-	Covered	T15,T19,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T15,T17
DetectSt	168	Covered	T13,T15,T17
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T13,T15,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T15,T17
DebounceSt->IdleSt	163	Covered	T134,T84,T75
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T13,T15,T17
IdleSt->DebounceSt	148	Covered	T13,T15,T17
StableSt->IdleSt	206	Covered	T13,T15,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T17
0	1	Covered	T13,T15,T17
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T17
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T134,T84,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T19,T150
StableSt	-	-	-	-	-	-	0	Covered	T13,T15,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	143	0	0
CntIncr_A	7034196	29446	0	0
CntNoWrap_A	7034196	6347944	0	0
DetectStDropOut_A	7034196	1	0	0
DetectedOut_A	7034196	30845	0	0
DetectedPulseOut_A	7034196	66	0	0
DisabledIdleSt_A	7034196	6227802	0	0
DisabledNoDetection_A	7034196	6230197	0	0
EnterDebounceSt_A	7034196	76	0	0
EnterDetectSt_A	7034196	67	0	0
EnterStableSt_A	7034196	66	0	0
PulseIsPulse_A	7034196	66	0	0
StayInStableSt	7034196	30750	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	143	0	0
T13	20329	2	0	0
T14	12831	0	0	0
T15	13134	4	0	0
T16	6502	0	0	0
T17	8254	2	0	0
T18	613	0	0	0
T19	2836	2	0	0
T85	0	4	0	0
T130	0	2	0	0
T134	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T196	0	4	0	0
T197	423	0	0	0
T198	402	0	0	0
T199	486	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	29446	0	0
T13	20329	10	0	0
T14	12831	0	0	0
T15	13134	75	0	0
T16	6502	0	0	0
T17	8254	47	0	0
T18	613	0	0	0
T19	2836	99	0	0
T85	0	132	0	0
T130	0	60	0	0
T134	0	198	0	0
T149	0	20	0	0
T150	0	99	0	0
T196	0	104	0	0
T197	423	0	0	0
T198	402	0	0	0
T199	486	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347944	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1	0	0
T75	5807	0	0	0
T84	12739	1	0	0
T200	22733	0	0	0
T201	14837	0	0	0
T202	558	0	0	0
T203	691	0	0	0
T204	502	0	0	0
T205	503	0	0	0
T206	402	0	0	0
T207	528	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	30845	0	0
T13	20329	38	0	0
T14	12831	0	0	0
T15	13134	132	0	0
T16	6502	0	0	0
T17	8254	41	0	0
T18	613	0	0	0
T19	2836	39	0	0
T85	0	377	0	0
T130	0	42	0	0
T134	0	60	0	0
T149	0	39	0	0
T150	0	8	0	0
T196	0	79	0	0
T197	423	0	0	0
T198	402	0	0	0
T199	486	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	66	0	0
T13	20329	1	0	0
T14	12831	0	0	0
T15	13134	2	0	0
T16	6502	0	0	0
T17	8254	1	0	0
T18	613	0	0	0
T19	2836	1	0	0
T85	0	2	0	0
T130	0	1	0	0
T134	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T196	0	2	0	0
T197	423	0	0	0
T198	402	0	0	0
T199	486	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6227802	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6230197	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	76	0	0
T13	20329	1	0	0
T14	12831	0	0	0
T15	13134	2	0	0
T16	6502	0	0	0
T17	8254	1	0	0
T18	613	0	0	0
T19	2836	1	0	0
T85	0	2	0	0
T130	0	1	0	0
T134	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T196	0	2	0	0
T197	423	0	0	0
T198	402	0	0	0
T199	486	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	67	0	0
T13	20329	1	0	0
T14	12831	0	0	0
T15	13134	2	0	0
T16	6502	0	0	0
T17	8254	1	0	0
T18	613	0	0	0
T19	2836	1	0	0
T85	0	2	0	0
T130	0	1	0	0
T134	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T196	0	2	0	0
T197	423	0	0	0
T198	402	0	0	0
T199	486	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	66	0	0
T13	20329	1	0	0
T14	12831	0	0	0
T15	13134	2	0	0
T16	6502	0	0	0
T17	8254	1	0	0
T18	613	0	0	0
T19	2836	1	0	0
T85	0	2	0	0
T130	0	1	0	0
T134	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T196	0	2	0	0
T197	423	0	0	0
T198	402	0	0	0
T199	486	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	66	0	0
T13	20329	1	0	0
T14	12831	0	0	0
T15	13134	2	0	0
T16	6502	0	0	0
T17	8254	1	0	0
T18	613	0	0	0
T19	2836	1	0	0
T85	0	2	0	0
T130	0	1	0	0
T134	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T196	0	2	0	0
T197	423	0	0	0
T198	402	0	0	0
T199	486	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	30750	0	0
T13	20329	36	0	0
T14	12831	0	0	0
T15	13134	130	0	0
T16	6502	0	0	0
T17	8254	39	0	0
T18	613	0	0	0
T19	2836	38	0	0
T85	0	374	0	0
T130	0	40	0	0
T134	0	59	0	0
T149	0	37	0	0
T150	0	7	0	0
T196	0	76	0	0
T197	423	0	0	0
T198	402	0	0	0
T199	486	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	36	0	0
T15	13134	2	0	0
T16	6502	0	0	0
T17	8254	0	0	0
T18	613	0	0	0
T19	2836	1	0	0
T20	26947	0	0	0
T21	204346	0	0	0
T81	0	2	0	0
T85	0	1	0	0
T87	0	1	0	0
T134	0	1	0	0
T150	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	492	0	0	0
T196	0	1	0	0
T198	402	0	0	0
T199	486	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T43,T208
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T2,T13,T209
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T11
1	-	Covered	T2,T13,T209

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T11
DetectSt	168	Covered	T2,T9,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T11
DebounceSt->IdleSt	163	Covered	T43,T85,T75
DetectSt->IdleSt	186	Covered	T43,T208
DetectSt->StableSt	191	Covered	T2,T9,T11
IdleSt->DebounceSt	148	Covered	T2,T9,T11
StableSt->IdleSt	206	Covered	T2,T9,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T11
0	1	Covered	T2,T9,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T85,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T43,T208
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T13,T209
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	88	0	0
CntIncr_A	7034196	27951	0	0
CntNoWrap_A	7034196	6347999	0	0
DetectStDropOut_A	7034196	2	0	0
DetectedOut_A	7034196	28865	0	0
DetectedPulseOut_A	7034196	40	0	0
DisabledIdleSt_A	7034196	6228839	0	0
DisabledNoDetection_A	7034196	6231240	0	0
EnterDebounceSt_A	7034196	46	0	0
EnterDetectSt_A	7034196	42	0	0
EnterStableSt_A	7034196	40	0	0
PulseIsPulse_A	7034196	40	0	0
StayInStableSt	7034196	28801	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7034196	6755	0	0
gen_low_level_sva.LowLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	88	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T13	0	2	0	0
T15	0	4	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	3	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	27951	0	0
T2	13507	58	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	24	0	0
T11	0	68	0	0
T13	0	20	0	0
T15	0	75	0	0
T17	0	52	0	0
T18	0	64	0	0
T19	0	99	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	36	0	0
T150	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347999	0	0
T1	35063	34567	0	0
T2	13507	6260	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	2	0	0
T22	15707	0	0	0
T23	1101	0	0	0
T43	641	1	0	0
T60	562	0	0	0
T73	30117	0	0	0
T139	404	0	0	0
T208	0	1	0	0
T210	522	0	0	0
T211	404	0	0	0
T212	526	0	0	0
T213	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	28865	0	0
T2	13507	43	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	41	0	0
T11	0	277	0	0
T13	0	40	0	0
T15	0	45	0	0
T17	0	41	0	0
T18	0	50	0	0
T19	0	163	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T150	0	41	0	0
T209	0	286	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	40	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T150	0	1	0	0
T209	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6228839	0	0
T1	35063	34567	0	0
T2	13507	5696	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6231240	0	0
T1	35063	34582	0	0
T2	13507	5715	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	46	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	2	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	42	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	1	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	40	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T150	0	1	0	0
T209	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	40	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T150	0	1	0	0
T209	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	28801	0	0
T2	13507	42	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	39	0	0
T11	0	275	0	0
T13	0	39	0	0
T15	0	41	0	0
T17	0	39	0	0
T18	0	48	0	0
T19	0	161	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T150	0	39	0	0
T209	0	283	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6755	0	0
T1	35063	11	0	0
T2	13507	37	0	0
T3	1601	8	0	0
T4	425	3	0	0
T5	427	2	0	0
T6	41075	17	0	0
T7	0	1	0	0
T24	716	0	0	0
T25	496	5	0	0
T26	759	0	0	0
T27	493	8	0	0
T28	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	15	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T13	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T87	0	1	0	0
T121	0	1	0	0
T162	0	1	0	0
T166	0	1	0	0
T209	0	1	0	0
T214	0	2	0	0
T215	0	1	0	0
T216	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T21,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T9
1	-	Covered	T2,T6,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T9
DetectSt	168	Covered	T2,T6,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T6,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T9
DebounceSt->IdleSt	163	Covered	T15,T17,T209
DetectSt->IdleSt	186	Covered	T21,T196
DetectSt->StableSt	191	Covered	T2,T6,T9
IdleSt->DebounceSt	148	Covered	T2,T6,T9
StableSt->IdleSt	206	Covered	T2,T6,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T209,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T21,T196
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	143	0	0
CntIncr_A	7034196	52158	0	0
CntNoWrap_A	7034196	6347944	0	0
DetectStDropOut_A	7034196	2	0	0
DetectedOut_A	7034196	6253	0	0
DetectedPulseOut_A	7034196	67	0	0
DisabledIdleSt_A	7034196	6124606	0	0
DisabledNoDetection_A	7034196	6127005	0	0
EnterDebounceSt_A	7034196	76	0	0
EnterDetectSt_A	7034196	69	0	0
EnterStableSt_A	7034196	67	0	0
PulseIsPulse_A	7034196	67	0	0
StayInStableSt	7034196	6157	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	143	0	0
T2	13507	6	0	0
T3	1601	0	0	0
T6	41075	4	0	0
T7	525	0	0	0
T9	0	4	0	0
T11	0	4	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	0	2	0	0
T21	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T130	0	2	0	0
T148	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	52158	0	0
T2	13507	174	0	0
T3	1601	0	0	0
T6	41075	152	0	0
T7	525	0	0	0
T9	0	48	0	0
T11	0	136	0	0
T15	0	7	0	0
T17	0	99	0	0
T18	0	64	0	0
T19	0	99	0	0
T21	0	46716	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T148	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347944	0	0
T1	35063	34567	0	0
T2	13507	6256	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36950	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	2	0	0
T21	204346	1	0	0
T49	5617	0	0	0
T68	5269	0	0	0
T148	963	0	0	0
T167	721	0	0	0
T184	654	0	0	0
T185	6049	0	0	0
T186	524	0	0	0
T187	412	0	0	0
T188	402	0	0	0
T196	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6253	0	0
T2	13507	211	0	0
T3	1601	0	0	0
T6	41075	166	0	0
T7	525	0	0	0
T9	0	123	0	0
T11	0	73	0	0
T17	0	41	0	0
T18	0	50	0	0
T19	0	407	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T130	0	47	0	0
T148	0	190	0	0
T196	0	205	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	67	0	0
T2	13507	3	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T130	0	1	0	0
T148	0	1	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6124606	0	0
T1	35063	34567	0	0
T2	13507	5696	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36263	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6127005	0	0
T1	35063	34582	0	0
T2	13507	5715	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36273	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	76	0	0
T2	13507	3	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T148	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	69	0	0
T2	13507	3	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T130	0	1	0	0
T148	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	67	0	0
T2	13507	3	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T130	0	1	0	0
T148	0	1	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	67	0	0
T2	13507	3	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T130	0	1	0	0
T148	0	1	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6157	0	0
T2	13507	207	0	0
T3	1601	0	0	0
T6	41075	164	0	0
T7	525	0	0	0
T9	0	120	0	0
T11	0	71	0	0
T17	0	39	0	0
T18	0	48	0	0
T19	0	405	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T130	0	46	0	0
T148	0	189	0	0
T196	0	204	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	37	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	2	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T74	0	1	0	0
T87	0	1	0	0
T130	0	1	0	0
T148	0	1	0	0
T196	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T43
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T11
0	1	Covered	T2,T9,T11
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T11
1	-	Covered	T2,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T11
DetectSt	168	Covered	T2,T9,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T11
DebounceSt->IdleSt	163	Covered	T43,T85,T75
DetectSt->IdleSt	186	Covered	T43
DetectSt->StableSt	191	Covered	T2,T9,T11
IdleSt->DebounceSt	148	Covered	T2,T9,T11
StableSt->IdleSt	206	Covered	T2,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T11
0	1	Covered	T2,T9,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T85,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T43
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	114	0	0
CntIncr_A	7034196	49586	0	0
CntNoWrap_A	7034196	6347973	0	0
DetectStDropOut_A	7034196	1	0	0
DetectedOut_A	7034196	113436	0	0
DetectedPulseOut_A	7034196	54	0	0
DisabledIdleSt_A	7034196	6020218	0	0
DisabledNoDetection_A	7034196	6022606	0	0
EnterDebounceSt_A	7034196	59	0	0
EnterDetectSt_A	7034196	55	0	0
EnterStableSt_A	7034196	54	0	0
PulseIsPulse_A	7034196	54	0	0
StayInStableSt	7034196	113358	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7034196	6453	0	0
gen_low_level_sva.LowLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	114	0	0
T2	13507	4	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	2	0	0
T11	0	4	0	0
T13	0	4	0	0
T21	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	3	0	0
T73	0	2	0	0
T148	0	2	0	0
T150	0	2	0	0
T193	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	49586	0	0
T2	13507	116	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	24	0	0
T11	0	136	0	0
T13	0	30	0	0
T21	0	46716	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	36	0	0
T73	0	55	0	0
T148	0	86	0	0
T150	0	99	0	0
T193	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347973	0	0
T1	35063	34567	0	0
T2	13507	6258	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1	0	0
T22	15707	0	0	0
T23	1101	0	0	0
T43	641	1	0	0
T60	562	0	0	0
T73	30117	0	0	0
T139	404	0	0	0
T210	522	0	0	0
T211	404	0	0	0
T212	526	0	0	0
T213	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	113436	0	0
T2	13507	55	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	3	0	0
T11	0	83	0	0
T13	0	160	0	0
T21	0	110504	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T73	0	1	0	0
T85	0	159	0	0
T148	0	61	0	0
T150	0	41	0	0
T193	0	93	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	0	2	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T73	0	1	0	0
T85	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T193	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6020218	0	0
T1	35063	34567	0	0
T2	13507	5696	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6022606	0	0
T1	35063	34582	0	0
T2	13507	5715	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	59	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	0	2	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	2	0	0
T73	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T193	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	55	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	0	2	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T43	0	1	0	0
T73	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T193	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	0	2	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T73	0	1	0	0
T85	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T193	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	0	2	0	0
T21	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T73	0	1	0	0
T85	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T193	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	113358	0	0
T2	13507	53	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	2	0	0
T11	0	80	0	0
T13	0	156	0	0
T21	0	110502	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T85	0	158	0	0
T148	0	59	0	0
T150	0	39	0	0
T193	0	90	0	0
T209	0	79	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6453	0	0
T1	35063	15	0	0
T2	13507	39	0	0
T3	1601	0	0	0
T4	425	2	0	0
T5	427	1	0	0
T6	41075	7	0	0
T24	716	0	0	0
T25	496	8	0	0
T26	759	0	0	0
T27	493	4	0	0
T28	0	9	0	0
T29	0	3	0	0
T30	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	29	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T6	41075	0	0	0
T7	525	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T28	488	0	0	0
T29	507	0	0	0
T73	0	1	0	0
T81	0	2	0	0
T85	0	1	0	0
T87	0	1	0	0
T193	0	1	0	0
T203	0	1	0	0
T209	0	1	0	0