Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T42
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T40,T14,T46
1	1	Covered	T40,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T42,T14
0	1	Covered	T41,T42,T49
1	0	Covered	T79,T224,T89

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T14,T16
0	1	Covered	T40,T14,T16
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T14,T16
1	-	Covered	T40,T14,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T41,T42
DetectSt	168	Covered	T40,T41,T42
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T40,T14,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T41,T42
DebounceSt->IdleSt	163	Covered	T41,T75,T225
DetectSt->IdleSt	186	Covered	T41,T42,T49
DetectSt->StableSt	191	Covered	T40,T14,T16
IdleSt->DebounceSt	148	Covered	T40,T41,T42
StableSt->IdleSt	206	Covered	T40,T14,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T41,T42
0	1	Covered	T40,T41,T42
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T42
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T40,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T42
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T75,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T41,T42,T49
DetectSt	-	-	-	-	0	1	-	Covered	T40,T14,T16
DetectSt	-	-	-	-	0	0	-	Covered	T40,T42,T14
StableSt	-	-	-	-	-	-	1	Covered	T40,T14,T16
StableSt	-	-	-	-	-	-	0	Covered	T40,T14,T16
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	2902	0	0
CntIncr_A	7034196	97795	0	0
CntNoWrap_A	7034196	6345185	0	0
DetectStDropOut_A	7034196	468	0	0
DetectedOut_A	7034196	69205	0	0
DetectedPulseOut_A	7034196	744	0	0
DisabledIdleSt_A	7034196	5925951	0	0
DisabledNoDetection_A	7034196	5928228	0	0
EnterDebounceSt_A	7034196	1474	0	0
EnterDetectSt_A	7034196	1429	0	0
EnterStableSt_A	7034196	744	0	0
PulseIsPulse_A	7034196	744	0	0
StayInStableSt	7034196	68376	0	0
gen_high_event_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	658	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	2902	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	46	0	0
T16	0	30	0	0
T40	13327	8	0	0
T41	4865	31	0	0
T42	0	44	0	0
T46	0	24	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	22	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	48	0	0
T69	0	18	0	0
T70	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	97795	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	1978	0	0
T16	0	645	0	0
T40	13327	368	0	0
T41	4865	1058	0	0
T42	0	1099	0	0
T46	0	492	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	654	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	1271	0	0
T69	0	225	0	0
T70	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6345185	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	468	0	0
T11	841	0	0	0
T41	4865	8	0	0
T42	5121	22	0	0
T48	693	0	0	0
T49	0	11	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T68	0	24	0	0
T70	0	2	0	0
T75	0	1	0	0
T79	0	9	0	0
T89	0	1	0	0
T90	0	5	0	0
T91	0	25	0	0
T151	1671	0	0	0
T152	422	0	0	0
T169	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	69205	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	1231	0	0
T16	0	1478	0	0
T40	13327	355	0	0
T41	4865	0	0	0
T44	0	8652	0	0
T45	0	3227	0	0
T46	0	428	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	956	0	0
T226	0	763	0	0
T227	0	1093	0	0
T228	0	1892	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	744	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	23	0	0
T16	0	15	0	0
T40	13327	4	0	0
T41	4865	0	0	0
T44	0	27	0	0
T45	0	11	0	0
T46	0	12	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	9	0	0
T226	0	8	0	0
T227	0	14	0	0
T228	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5925951	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5928228	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1474	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	23	0	0
T16	0	15	0	0
T40	13327	4	0	0
T41	4865	23	0	0
T42	0	22	0	0
T46	0	12	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	11	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	24	0	0
T69	0	9	0	0
T70	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1429	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	23	0	0
T16	0	15	0	0
T40	13327	4	0	0
T41	4865	8	0	0
T42	0	22	0	0
T46	0	12	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	11	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	24	0	0
T69	0	9	0	0
T70	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	744	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	23	0	0
T16	0	15	0	0
T40	13327	4	0	0
T41	4865	0	0	0
T44	0	27	0	0
T45	0	11	0	0
T46	0	12	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	9	0	0
T226	0	8	0	0
T227	0	14	0	0
T228	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	744	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	23	0	0
T16	0	15	0	0
T40	13327	4	0	0
T41	4865	0	0	0
T44	0	27	0	0
T45	0	11	0	0
T46	0	12	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	9	0	0
T226	0	8	0	0
T227	0	14	0	0
T228	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	68376	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	1207	0	0
T16	0	1463	0	0
T40	13327	351	0	0
T41	4865	0	0	0
T44	0	8621	0	0
T45	0	3214	0	0
T46	0	415	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	945	0	0
T226	0	751	0	0
T227	0	1078	0	0
T228	0	1867	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	658	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	22	0	0
T16	0	15	0	0
T40	13327	4	0	0
T41	4865	0	0	0
T44	0	23	0	0
T45	0	9	0	0
T46	0	11	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	7	0	0
T226	0	4	0	0
T227	0	13	0	0
T228	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T88,T92,T93
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T1,T8,T9
DetectSt->IdleSt	186	Covered	T88,T75,T92
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T8,T9
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T88,T75,T92
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	994	0	0
CntIncr_A	7034196	51132	0	0
CntNoWrap_A	7034196	6347093	0	0
DetectStDropOut_A	7034196	50	0	0
DetectedOut_A	7034196	18136	0	0
DetectedPulseOut_A	7034196	398	0	0
DisabledIdleSt_A	7034196	5914204	0	0
DisabledNoDetection_A	7034196	5915841	0	0
EnterDebounceSt_A	7034196	543	0	0
EnterDetectSt_A	7034196	452	0	0
EnterStableSt_A	7034196	398	0	0
PulseIsPulse_A	7034196	398	0	0
StayInStableSt	7034196	17708	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	365	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	994	0	0
T1	35063	7	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	26	0	0
T9	0	2	0	0
T10	0	7	0	0
T12	0	1	0	0
T13	0	10	0	0
T14	0	2	0	0
T15	0	3	0	0
T16	0	3	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	51132	0	0
T1	35063	320	0	0
T2	13507	25	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	1292	0	0
T9	0	40	0	0
T10	0	422	0	0
T12	0	83	0	0
T13	0	353	0	0
T14	0	83	0	0
T15	0	45	0	0
T16	0	76	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347093	0	0
T1	35063	34560	0	0
T2	13507	6260	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	50	0	0
T81	51213	0	0	0
T86	757	0	0	0
T87	8693	0	0	0
T88	12760	1	0	0
T92	0	9	0	0
T93	0	2	0	0
T94	0	2	0	0
T95	0	2	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	0	4	0	0
T99	0	4	0	0
T100	0	2	0	0
T101	3297	0	0	0
T102	721	0	0	0
T103	752	0	0	0
T104	632	0	0	0
T105	454	0	0	0
T106	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	18136	0	0
T1	35063	220	0	0
T2	13507	3	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	626	0	0
T10	0	12	0	0
T13	0	137	0	0
T14	0	99	0	0
T15	0	4	0	0
T16	0	85	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	81	0	0
T69	0	157	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	398	0	0
T1	35063	3	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5914204	0	0
T1	35063	30219	0	0
T2	13507	4931	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5915841	0	0
T1	35063	30219	0	0
T2	13507	4949	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	543	0	0
T1	35063	4	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	14	0	0
T9	0	2	0	0
T10	0	4	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	452	0	0
T1	35063	3	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	398	0	0
T1	35063	3	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	398	0	0
T1	35063	3	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	17708	0	0
T1	35063	217	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	614	0	0
T10	0	9	0	0
T13	0	132	0	0
T14	0	98	0	0
T15	0	3	0	0
T16	0	84	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	80	0	0
T69	0	155	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	365	0	0
T1	35063	3	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	3	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T42
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T40,T14,T16
1	1	Covered	T40,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T42,T14
0	1	Covered	T40,T41,T42
1	0	Covered	T40,T16,T46

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T44,T45
0	1	Covered	T14,T44,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T44,T45
1	-	Covered	T14,T44,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T41,T42
DetectSt	168	Covered	T40,T41,T42
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T41,T42
DebounceSt->IdleSt	163	Covered	T41,T75,T225
DetectSt->IdleSt	186	Covered	T40,T41,T42
DetectSt->StableSt	191	Covered	T14,T44,T45
IdleSt->DebounceSt	148	Covered	T40,T41,T42
StableSt->IdleSt	206	Covered	T14,T44,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T41,T42
0	1	Covered	T40,T41,T42
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T42
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T40,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T42
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T75,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	0	1	-	Covered	T14,T44,T45
DetectSt	-	-	-	-	0	0	-	Covered	T40,T42,T14
StableSt	-	-	-	-	-	-	1	Covered	T14,T44,T45
StableSt	-	-	-	-	-	-	0	Covered	T14,T44,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	2986	0	0
CntIncr_A	7034196	101144	0	0
CntNoWrap_A	7034196	6345101	0	0
DetectStDropOut_A	7034196	475	0	0
DetectedOut_A	7034196	63044	0	0
DetectedPulseOut_A	7034196	796	0	0
DisabledIdleSt_A	7034196	5933043	0	0
DisabledNoDetection_A	7034196	5935305	0	0
EnterDebounceSt_A	7034196	1521	0	0
EnterDetectSt_A	7034196	1467	0	0
EnterStableSt_A	7034196	796	0	0
PulseIsPulse_A	7034196	796	0	0
StayInStableSt	7034196	62148	0	0
gen_high_event_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	695	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	2986	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	62	0	0
T16	0	18	0	0
T40	13327	10	0	0
T41	4865	30	0	0
T42	0	20	0	0
T46	0	60	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	22	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	10	0	0
T69	0	52	0	0
T70	0	62	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	101144	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	2449	0	0
T16	0	458	0	0
T40	13327	893	0	0
T41	4865	1196	0	0
T42	0	496	0	0
T46	0	1548	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	654	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	260	0	0
T69	0	1247	0	0
T70	0	1183	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6345101	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	475	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T40	13327	2	0	0
T41	4865	5	0	0
T42	0	10	0	0
T46	0	10	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	11	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	5	0	0
T70	0	31	0	0
T75	0	1	0	0
T90	0	16	0	0
T178	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	63044	0	0
T14	12831	3396	0	0
T15	13134	0	0	0
T16	6502	0	0	0
T17	8254	0	0	0
T18	613	0	0	0
T19	2836	0	0	0
T20	26947	0	0	0
T44	0	3202	0	0
T45	0	178	0	0
T79	0	1439	0	0
T89	0	1661	0	0
T183	492	0	0	0
T198	402	0	0	0
T199	486	0	0	0
T224	0	943	0	0
T227	0	1595	0	0
T228	0	305	0	0
T229	0	2446	0	0
T230	0	193	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	796	0	0
T14	12831	31	0	0
T15	13134	0	0	0
T16	6502	0	0	0
T17	8254	0	0	0
T18	613	0	0	0
T19	2836	0	0	0
T20	26947	0	0	0
T44	0	15	0	0
T45	0	8	0	0
T79	0	11	0	0
T89	0	15	0	0
T183	492	0	0	0
T198	402	0	0	0
T199	486	0	0	0
T224	0	16	0	0
T227	0	12	0	0
T228	0	6	0	0
T229	0	28	0	0
T230	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5933043	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5935305	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1521	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	31	0	0
T16	0	9	0	0
T40	13327	5	0	0
T41	4865	26	0	0
T42	0	10	0	0
T46	0	30	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	11	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	5	0	0
T69	0	26	0	0
T70	0	31	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1467	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	31	0	0
T16	0	9	0	0
T40	13327	5	0	0
T41	4865	5	0	0
T42	0	10	0	0
T46	0	30	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	11	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	5	0	0
T69	0	26	0	0
T70	0	31	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	796	0	0
T14	12831	31	0	0
T15	13134	0	0	0
T16	6502	0	0	0
T17	8254	0	0	0
T18	613	0	0	0
T19	2836	0	0	0
T20	26947	0	0	0
T44	0	15	0	0
T45	0	8	0	0
T79	0	11	0	0
T89	0	15	0	0
T183	492	0	0	0
T198	402	0	0	0
T199	486	0	0	0
T224	0	16	0	0
T227	0	12	0	0
T228	0	6	0	0
T229	0	28	0	0
T230	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	796	0	0
T14	12831	31	0	0
T15	13134	0	0	0
T16	6502	0	0	0
T17	8254	0	0	0
T18	613	0	0	0
T19	2836	0	0	0
T20	26947	0	0	0
T44	0	15	0	0
T45	0	8	0	0
T79	0	11	0	0
T89	0	15	0	0
T183	492	0	0	0
T198	402	0	0	0
T199	486	0	0	0
T224	0	16	0	0
T227	0	12	0	0
T228	0	6	0	0
T229	0	28	0	0
T230	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	62148	0	0
T14	12831	3364	0	0
T15	13134	0	0	0
T16	6502	0	0	0
T17	8254	0	0	0
T18	613	0	0	0
T19	2836	0	0	0
T20	26947	0	0	0
T44	0	3185	0	0
T45	0	170	0	0
T79	0	1424	0	0
T89	0	1639	0	0
T183	492	0	0	0
T198	402	0	0	0
T199	486	0	0	0
T224	0	925	0	0
T227	0	1583	0	0
T228	0	298	0	0
T229	0	2414	0	0
T230	0	180	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	695	0	0
T14	12831	30	0	0
T15	13134	0	0	0
T16	6502	0	0	0
T17	8254	0	0	0
T18	613	0	0	0
T19	2836	0	0	0
T20	26947	0	0	0
T44	0	13	0	0
T45	0	8	0	0
T79	0	7	0	0
T89	0	8	0	0
T183	492	0	0	0
T198	402	0	0	0
T199	486	0	0	0
T224	0	14	0	0
T227	0	12	0	0
T228	0	5	0	0
T229	0	24	0	0
T230	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T8,T10,T231
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T9
0	1	Covered	T1,T2,T9
1	0	Covered	T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T9
1	-	Covered	T1,T2,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T1,T13,T20
DetectSt->IdleSt	186	Covered	T8,T10,T231
DetectSt->StableSt	191	Covered	T1,T2,T9
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T13,T20
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T10,T231
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	972	0	0
CntIncr_A	7034196	55308	0	0
CntNoWrap_A	7034196	6347115	0	0
DetectStDropOut_A	7034196	53	0	0
DetectedOut_A	7034196	15904	0	0
DetectedPulseOut_A	7034196	403	0	0
DisabledIdleSt_A	7034196	5936703	0	0
DisabledNoDetection_A	7034196	5938424	0	0
EnterDebounceSt_A	7034196	512	0	0
EnterDetectSt_A	7034196	461	0	0
EnterStableSt_A	7034196	403	0	0
PulseIsPulse_A	7034196	403	0	0
StayInStableSt	7034196	15471	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	371	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	972	0	0
T1	35063	14	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T9	0	4	0	0
T10	0	4	0	0
T12	0	12	0	0
T13	0	4	0	0
T14	0	2	0	0
T20	0	7	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	55308	0	0
T1	35063	1012	0	0
T2	13507	86	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	892	0	0
T9	0	124	0	0
T10	0	265	0	0
T12	0	654	0	0
T13	0	236	0	0
T14	0	84	0	0
T20	0	326	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T73	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347115	0	0
T1	35063	34553	0	0
T2	13507	6260	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	53	0	0
T8	41344	6	0	0
T9	11689	0	0	0
T10	0	2	0	0
T40	13327	0	0	0
T47	737	0	0	0
T52	405	0	0	0
T57	126569	0	0	0
T61	497	0	0	0
T63	502	0	0	0
T64	506	0	0	0
T94	0	1	0	0
T97	0	1	0	0
T192	0	2	0	0
T231	0	7	0	0
T232	0	4	0	0
T233	0	7	0	0
T234	0	9	0	0
T235	0	3	0	0
T236	431	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	15904	0	0
T1	35063	69	0	0
T2	13507	65	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T9	0	14	0	0
T12	0	406	0	0
T13	0	11	0	0
T14	0	97	0	0
T20	0	215	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T72	0	98	0	0
T73	0	42	0	0
T237	0	32	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	403	0	0
T1	35063	6	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T9	0	2	0	0
T12	0	6	0	0
T13	0	1	0	0
T14	0	1	0	0
T20	0	3	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T72	0	3	0	0
T73	0	1	0	0
T237	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5936703	0	0
T1	35063	30219	0	0
T2	13507	5012	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5938424	0	0
T1	35063	30219	0	0
T2	13507	5031	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	512	0	0
T1	35063	8	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	6	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	6	0	0
T13	0	3	0	0
T14	0	1	0	0
T20	0	4	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	461	0	0
T1	35063	6	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	6	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	6	0	0
T13	0	1	0	0
T14	0	1	0	0
T20	0	3	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T73	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	403	0	0
T1	35063	6	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T9	0	2	0	0
T12	0	6	0	0
T13	0	1	0	0
T14	0	1	0	0
T20	0	3	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T72	0	3	0	0
T73	0	1	0	0
T237	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	403	0	0
T1	35063	6	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T9	0	2	0	0
T12	0	6	0	0
T13	0	1	0	0
T14	0	1	0	0
T20	0	3	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T72	0	3	0	0
T73	0	1	0	0
T237	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	15471	0	0
T1	35063	63	0	0
T2	13507	64	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T9	0	12	0	0
T12	0	400	0	0
T13	0	10	0	0
T14	0	96	0	0
T20	0	212	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T72	0	95	0	0
T73	0	41	0	0
T237	0	31	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	371	0	0
T1	35063	6	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T9	0	2	0	0
T12	0	6	0	0
T13	0	1	0	0
T14	0	1	0	0
T20	0	3	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T72	0	3	0	0
T73	0	1	0	0
T237	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T42
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T40,T14,T16
1	1	Covered	T40,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T42,T14
0	1	Covered	T41,T42,T16
1	0	Covered	T16,T44,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T14,T46
0	1	Covered	T40,T14,T46
1	0	Covered	T79,T238

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T14,T46
1	-	Covered	T40,T14,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T41,T42
DetectSt	168	Covered	T40,T41,T42
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T40,T14,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T41,T42
DebounceSt->IdleSt	163	Covered	T41,T75,T225
DetectSt->IdleSt	186	Covered	T41,T42,T16
DetectSt->StableSt	191	Covered	T40,T14,T46
IdleSt->DebounceSt	148	Covered	T40,T41,T42
StableSt->IdleSt	206	Covered	T40,T14,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T41,T42
0	1	Covered	T40,T41,T42
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T42
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T40,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T42
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T75,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T41,T42,T16
DetectSt	-	-	-	-	0	1	-	Covered	T40,T14,T46
DetectSt	-	-	-	-	0	0	-	Covered	T40,T42,T14
StableSt	-	-	-	-	-	-	1	Covered	T40,T14,T46
StableSt	-	-	-	-	-	-	0	Covered	T40,T14,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	2696	0	0
CntIncr_A	7034196	96937	0	0
CntNoWrap_A	7034196	6345391	0	0
DetectStDropOut_A	7034196	465	0	0
DetectedOut_A	7034196	55071	0	0
DetectedPulseOut_A	7034196	640	0	0
DisabledIdleSt_A	7034196	5935704	0	0
DisabledNoDetection_A	7034196	5937994	0	0
EnterDebounceSt_A	7034196	1372	0	0
EnterDetectSt_A	7034196	1325	0	0
EnterStableSt_A	7034196	640	0	0
PulseIsPulse_A	7034196	640	0	0
StayInStableSt	7034196	54359	0	0
gen_high_event_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	565	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	2696	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	14	0	0
T16	0	54	0	0
T40	13327	32	0	0
T41	4865	14	0	0
T42	0	42	0	0
T46	0	10	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	4	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	48	0	0
T69	0	14	0	0
T70	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	96937	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	581	0	0
T16	0	1365	0	0
T40	13327	2304	0	0
T41	4865	598	0	0
T42	0	1046	0	0
T46	0	220	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	119	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	1271	0	0
T69	0	168	0	0
T70	0	564	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6345391	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	465	0	0
T11	841	0	0	0
T16	0	12	0	0
T41	4865	1	0	0
T42	5121	21	0	0
T44	0	8	0	0
T48	693	0	0	0
T49	0	2	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T68	0	24	0	0
T70	0	15	0	0
T90	0	17	0	0
T151	1671	0	0	0
T152	422	0	0	0
T169	427	0	0	0
T178	0	11	0	0
T228	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	55071	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	273	0	0
T40	13327	584	0	0
T41	4865	0	0	0
T45	0	3280	0	0
T46	0	46	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	544	0	0
T79	0	1	0	0
T224	0	392	0	0
T226	0	1252	0	0
T227	0	1144	0	0
T239	0	1644	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	640	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	7	0	0
T40	13327	16	0	0
T41	4865	0	0	0
T45	0	18	0	0
T46	0	5	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	7	0	0
T79	0	1	0	0
T224	0	7	0	0
T226	0	13	0	0
T227	0	13	0	0
T239	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5935704	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5937994	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1372	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	7	0	0
T16	0	27	0	0
T40	13327	16	0	0
T41	4865	13	0	0
T42	0	21	0	0
T46	0	5	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	2	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	24	0	0
T69	0	7	0	0
T70	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1325	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	7	0	0
T16	0	27	0	0
T40	13327	16	0	0
T41	4865	1	0	0
T42	0	21	0	0
T46	0	5	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	2	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	24	0	0
T69	0	7	0	0
T70	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	640	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	7	0	0
T40	13327	16	0	0
T41	4865	0	0	0
T45	0	18	0	0
T46	0	5	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	7	0	0
T79	0	1	0	0
T224	0	7	0	0
T226	0	13	0	0
T227	0	13	0	0
T239	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	640	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	7	0	0
T40	13327	16	0	0
T41	4865	0	0	0
T45	0	18	0	0
T46	0	5	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	7	0	0
T79	0	1	0	0
T224	0	7	0	0
T226	0	13	0	0
T227	0	13	0	0
T239	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	54359	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	266	0	0
T40	13327	568	0	0
T41	4865	0	0	0
T45	0	3258	0	0
T46	0	41	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	536	0	0
T224	0	384	0	0
T226	0	1237	0	0
T227	0	1130	0	0
T229	0	42	0	0
T239	0	1630	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	565	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	7	0	0
T40	13327	16	0	0
T41	4865	0	0	0
T45	0	14	0	0
T46	0	5	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	6	0	0
T224	0	6	0	0
T226	0	11	0	0
T227	0	12	0	0
T229	0	1	0	0
T239	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T9,T12,T185
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T8,T10,T12
DetectSt->IdleSt	186	Covered	T9,T12,T185
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T10,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T9,T12,T185
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	937	0	0
CntIncr_A	7034196	56106	0	0
CntNoWrap_A	7034196	6347150	0	0
DetectStDropOut_A	7034196	64	0	0
DetectedOut_A	7034196	15024	0	0
DetectedPulseOut_A	7034196	370	0	0
DisabledIdleSt_A	7034196	5933265	0	0
DisabledNoDetection_A	7034196	5935010	0	0
EnterDebounceSt_A	7034196	500	0	0
EnterDetectSt_A	7034196	438	0	0
EnterStableSt_A	7034196	370	0	0
PulseIsPulse_A	7034196	370	0	0
StayInStableSt	7034196	14629	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	343	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	937	0	0
T1	35063	18	0	0
T2	13507	2	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	27	0	0
T9	0	2	0	0
T10	0	9	0	0
T12	0	8	0	0
T13	0	1	0	0
T20	0	21	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T69	0	2	0	0
T185	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	56106	0	0
T1	35063	1359	0	0
T2	13507	118	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	1208	0	0
T9	0	68	0	0
T10	0	550	0	0
T12	0	696	0	0
T13	0	52	0	0
T20	0	1202	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T69	0	59	0	0
T185	0	735	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347150	0	0
T1	35063	34549	0	0
T2	13507	6260	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	64	0	0
T9	11689	1	0	0
T10	14540	0	0	0
T12	0	3	0	0
T41	4865	0	0	0
T48	693	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T73	0	2	0	0
T97	0	4	0	0
T151	1671	0	0	0
T152	422	0	0	0
T163	0	3	0	0
T177	0	6	0	0
T185	0	5	0	0
T240	0	10	0	0
T241	0	6	0	0
T242	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	15024	0	0
T1	35063	65	0	0
T2	13507	33	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	796	0	0
T10	0	17	0	0
T20	0	463	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T45	0	1116	0	0
T69	0	58	0	0
T72	0	20	0	0
T231	0	74	0	0
T237	0	421	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	370	0	0
T1	35063	9	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	13	0	0
T10	0	4	0	0
T20	0	10	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T45	0	4	0	0
T69	0	1	0	0
T72	0	2	0	0
T231	0	4	0	0
T237	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5933265	0	0
T1	35063	30219	0	0
T2	13507	5012	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5935010	0	0
T1	35063	30219	0	0
T2	13507	5031	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	500	0	0
T1	35063	9	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	14	0	0
T9	0	1	0	0
T10	0	5	0	0
T12	0	5	0	0
T13	0	1	0	0
T20	0	11	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T69	0	1	0	0
T185	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	438	0	0
T1	35063	9	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	13	0	0
T9	0	1	0	0
T10	0	4	0	0
T12	0	3	0	0
T20	0	10	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T69	0	1	0	0
T73	0	2	0	0
T185	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	370	0	0
T1	35063	9	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	13	0	0
T10	0	4	0	0
T20	0	10	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T45	0	4	0	0
T69	0	1	0	0
T72	0	2	0	0
T231	0	4	0	0
T237	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	370	0	0
T1	35063	9	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	13	0	0
T10	0	4	0	0
T20	0	10	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T45	0	4	0	0
T69	0	1	0	0
T72	0	2	0	0
T231	0	4	0	0
T237	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	14629	0	0
T1	35063	56	0	0
T2	13507	32	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	783	0	0
T10	0	13	0	0
T20	0	453	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T45	0	1112	0	0
T69	0	57	0	0
T72	0	18	0	0
T231	0	70	0	0
T237	0	413	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	343	0	0
T1	35063	9	0	0
T2	13507	1	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	13	0	0
T10	0	4	0	0
T20	0	10	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T45	0	4	0	0
T69	0	1	0	0
T72	0	2	0	0
T231	0	4	0	0
T237	0	8	0	0