Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T42
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T42
1	0	Covered	T40,T14,T16
1	1	Covered	T40,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T42,T14
0	1	Covered	T41,T42,T49
1	0	Covered	T228,T89,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T14,T16
0	1	Covered	T40,T14,T16
1	0	Covered	T80,T158

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T14,T16
1	-	Covered	T40,T14,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T41,T42
DetectSt	168	Covered	T40,T41,T42
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T40,T14,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T41,T42
DebounceSt->IdleSt	163	Covered	T41,T75,T225
DetectSt->IdleSt	186	Covered	T41,T42,T49
DetectSt->StableSt	191	Covered	T40,T14,T16
IdleSt->DebounceSt	148	Covered	T40,T41,T42
StableSt->IdleSt	206	Covered	T40,T14,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T41,T42
0	1	Covered	T40,T41,T42
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T42
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T40,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T42
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T75,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T41,T42,T49
DetectSt	-	-	-	-	0	1	-	Covered	T40,T14,T16
DetectSt	-	-	-	-	0	0	-	Covered	T40,T42,T14
StableSt	-	-	-	-	-	-	1	Covered	T40,T14,T16
StableSt	-	-	-	-	-	-	0	Covered	T40,T14,T16
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	3221	0	0
CntIncr_A	7034196	105181	0	0
CntNoWrap_A	7034196	6344866	0	0
DetectStDropOut_A	7034196	501	0	0
DetectedOut_A	7034196	85477	0	0
DetectedPulseOut_A	7034196	934	0	0
DisabledIdleSt_A	7034196	5911000	0	0
DisabledNoDetection_A	7034196	5913263	0	0
EnterDebounceSt_A	7034196	1645	0	0
EnterDetectSt_A	7034196	1578	0	0
EnterStableSt_A	7034196	934	0	0
PulseIsPulse_A	7034196	934	0	0
StayInStableSt	7034196	84444	0	0
gen_high_event_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	832	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	3221	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	26	0	0
T16	0	10	0	0
T40	13327	60	0	0
T41	4865	31	0	0
T42	0	30	0	0
T46	0	44	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	22	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	24	0	0
T69	0	52	0	0
T70	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	105181	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	1196	0	0
T16	0	235	0	0
T40	13327	2700	0	0
T41	4865	1242	0	0
T42	0	739	0	0
T46	0	946	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	654	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	627	0	0
T69	0	884	0	0
T70	0	261	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6344866	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	501	0	0
T11	841	0	0	0
T41	4865	5	0	0
T42	5121	15	0	0
T48	693	0	0	0
T49	0	11	0	0
T54	433	0	0	0
T58	1041	0	0	0
T65	525	0	0	0
T68	0	12	0	0
T70	0	7	0	0
T75	0	1	0	0
T89	0	2	0	0
T90	0	14	0	0
T151	1671	0	0	0
T152	422	0	0	0
T169	427	0	0	0
T228	0	14	0	0
T243	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	85477	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	397	0	0
T16	0	300	0	0
T40	13327	4416	0	0
T41	4865	0	0	0
T44	0	3624	0	0
T45	0	197	0	0
T46	0	1460	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	1739	0	0
T79	0	528	0	0
T226	0	352	0	0
T227	0	291	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	934	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	13	0	0
T16	0	5	0	0
T40	13327	30	0	0
T41	4865	0	0	0
T44	0	16	0	0
T45	0	5	0	0
T46	0	22	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	26	0	0
T79	0	6	0	0
T226	0	12	0	0
T227	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5911000	0	0
T1	35063	34567	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5913263	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1645	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	13	0	0
T16	0	5	0	0
T40	13327	30	0	0
T41	4865	27	0	0
T42	0	15	0	0
T46	0	22	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	11	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	12	0	0
T69	0	26	0	0
T70	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	1578	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	13	0	0
T16	0	5	0	0
T40	13327	30	0	0
T41	4865	5	0	0
T42	0	15	0	0
T46	0	22	0	0
T47	737	0	0	0
T48	693	0	0	0
T49	0	11	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T68	0	12	0	0
T69	0	26	0	0
T70	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	934	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	13	0	0
T16	0	5	0	0
T40	13327	30	0	0
T41	4865	0	0	0
T44	0	16	0	0
T45	0	5	0	0
T46	0	22	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	26	0	0
T79	0	6	0	0
T226	0	12	0	0
T227	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	934	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	13	0	0
T16	0	5	0	0
T40	13327	30	0	0
T41	4865	0	0	0
T44	0	16	0	0
T45	0	5	0	0
T46	0	22	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	26	0	0
T79	0	6	0	0
T226	0	12	0	0
T227	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	84444	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	384	0	0
T16	0	295	0	0
T40	13327	4386	0	0
T41	4865	0	0	0
T44	0	3606	0	0
T45	0	192	0	0
T46	0	1438	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	1710	0	0
T79	0	521	0	0
T226	0	338	0	0
T227	0	282	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	832	0	0
T9	11689	0	0	0
T10	14540	0	0	0
T14	0	13	0	0
T16	0	5	0	0
T40	13327	30	0	0
T41	4865	0	0	0
T44	0	14	0	0
T45	0	5	0	0
T46	0	22	0	0
T47	737	0	0	0
T48	693	0	0	0
T52	405	0	0	0
T53	501	0	0	0
T54	433	0	0	0
T65	525	0	0	0
T69	0	23	0	0
T79	0	5	0	0
T226	0	10	0	0
T227	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T12,T200,T244
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T10
1	-	Covered	T1,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T10
DetectSt	168	Covered	T1,T8,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T10
DebounceSt->IdleSt	163	Covered	T8,T10,T237
DetectSt->IdleSt	186	Covered	T12,T200,T75
DetectSt->StableSt	191	Covered	T1,T8,T10
IdleSt->DebounceSt	148	Covered	T1,T8,T10
StableSt->IdleSt	206	Covered	T1,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T10,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T12,T200,T75
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7034196	931	0	0
CntIncr_A	7034196	53460	0	0
CntNoWrap_A	7034196	6347156	0	0
DetectStDropOut_A	7034196	83	0	0
DetectedOut_A	7034196	15643	0	0
DetectedPulseOut_A	7034196	353	0	0
DisabledIdleSt_A	7034196	5908619	0	0
DisabledNoDetection_A	7034196	5910337	0	0
EnterDebounceSt_A	7034196	491	0	0
EnterDetectSt_A	7034196	441	0	0
EnterStableSt_A	7034196	353	0	0
PulseIsPulse_A	7034196	353	0	0
StayInStableSt	7034196	15261	0	0
gen_high_level_sva.HighLevelEvent_A	7034196	6350539	0	0
gen_not_sticky_sva.StableStDropOut_A	7034196	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	931	0	0
T1	35063	12	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	26	0	0
T10	0	14	0	0
T12	0	4	0	0
T13	0	4	0	0
T16	0	2	0	0
T22	0	2	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	2	0	0
T69	0	6	0	0
T185	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	53460	0	0
T1	35063	666	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	1736	0	0
T10	0	550	0	0
T12	0	353	0	0
T13	0	274	0	0
T16	0	47	0	0
T22	0	71	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	78	0	0
T69	0	168	0	0
T185	0	565	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6347156	0	0
T1	35063	34555	0	0
T2	13507	6262	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	83	0	0
T12	7398	2	0	0
T13	20329	0	0	0
T14	12831	0	0	0
T15	13134	0	0	0
T16	6502	0	0	0
T17	8254	0	0	0
T62	494	0	0	0
T67	502	0	0	0
T94	0	1	0	0
T95	0	4	0	0
T98	0	3	0	0
T192	0	2	0	0
T197	423	0	0	0
T200	0	10	0	0
T233	0	7	0	0
T242	0	6	0	0
T244	0	2	0	0
T245	0	2	0	0
T246	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	15643	0	0
T1	35063	280	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	182	0	0
T10	0	319	0	0
T13	0	14	0	0
T16	0	83	0	0
T22	0	56	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	54	0	0
T69	0	179	0	0
T73	0	51	0	0
T185	0	114	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	353	0	0
T1	35063	6	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	6	0	0
T13	0	2	0	0
T16	0	1	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	3	0	0
T73	0	6	0	0
T185	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5908619	0	0
T1	35063	30219	0	0
T2	13507	5012	0	0
T3	1601	1200	0	0
T4	425	24	0	0
T5	427	26	0	0
T6	41075	36954	0	0
T24	716	315	0	0
T25	496	95	0	0
T26	759	358	0	0
T27	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	5910337	0	0
T1	35063	30219	0	0
T2	13507	5031	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	491	0	0
T1	35063	6	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	14	0	0
T10	0	8	0	0
T12	0	2	0	0
T13	0	2	0	0
T16	0	1	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	3	0	0
T185	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	441	0	0
T1	35063	6	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	6	0	0
T12	0	2	0	0
T13	0	2	0	0
T16	0	1	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	3	0	0
T185	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	353	0	0
T1	35063	6	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	6	0	0
T13	0	2	0	0
T16	0	1	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	3	0	0
T73	0	6	0	0
T185	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	353	0	0
T1	35063	6	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	6	0	0
T13	0	2	0	0
T16	0	1	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	3	0	0
T73	0	6	0	0
T185	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	15261	0	0
T1	35063	274	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	170	0	0
T10	0	313	0	0
T13	0	12	0	0
T16	0	82	0	0
T22	0	55	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	53	0	0
T69	0	174	0	0
T73	0	45	0	0
T185	0	109	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	6350539	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7034196	320	0	0
T1	35063	6	0	0
T2	13507	0	0	0
T3	1601	0	0	0
T4	425	0	0	0
T5	427	0	0	0
T6	41075	0	0	0
T8	0	12	0	0
T10	0	6	0	0
T13	0	2	0	0
T16	0	1	0	0
T22	0	1	0	0
T24	716	0	0	0
T25	496	0	0	0
T26	759	0	0	0
T27	493	0	0	0
T46	0	1	0	0
T69	0	1	0	0
T73	0	6	0	0
T185	0	5	0	0