Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.99 99.39 96.35 100.00 97.44 98.78 99.63 94.31


Total test records in report: 905
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T38 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3152108660 Feb 21 12:36:17 PM PST 24 Feb 21 12:38:04 PM PST 24 42412527552 ps
T39 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2749326161 Feb 21 12:36:14 PM PST 24 Feb 21 12:37:05 PM PST 24 10792440368 ps
T792 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1978163192 Feb 21 12:36:27 PM PST 24 Feb 21 12:36:33 PM PST 24 2010674744 ps
T253 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.4101065360 Feb 21 12:36:29 PM PST 24 Feb 21 12:36:34 PM PST 24 2253414283 ps
T793 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.153870120 Feb 21 12:36:35 PM PST 24 Feb 21 12:36:37 PM PST 24 2076121368 ps
T290 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1672440684 Feb 21 12:36:20 PM PST 24 Feb 21 12:36:22 PM PST 24 2124758514 ps
T254 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.500734411 Feb 21 12:36:15 PM PST 24 Feb 21 12:36:19 PM PST 24 2065038650 ps
T315 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.133470337 Feb 21 12:36:27 PM PST 24 Feb 21 12:36:33 PM PST 24 2509896936 ps
T794 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3225039509 Feb 21 12:36:31 PM PST 24 Feb 21 12:36:35 PM PST 24 2043067701 ps
T795 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1859525098 Feb 21 12:36:04 PM PST 24 Feb 21 12:36:11 PM PST 24 2016072732 ps
T796 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2896589990 Feb 21 12:36:25 PM PST 24 Feb 21 12:36:33 PM PST 24 2015690324 ps
T255 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.813111526 Feb 21 12:36:06 PM PST 24 Feb 21 12:36:09 PM PST 24 2112833168 ps
T797 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3481942258 Feb 21 12:36:42 PM PST 24 Feb 21 12:36:48 PM PST 24 2016110566 ps
T292 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1440954640 Feb 21 12:36:10 PM PST 24 Feb 21 12:36:17 PM PST 24 2055025298 ps
T798 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3131107877 Feb 21 12:36:32 PM PST 24 Feb 21 12:36:35 PM PST 24 2135450044 ps
T799 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2737004358 Feb 21 12:36:26 PM PST 24 Feb 21 12:36:29 PM PST 24 2030700432 ps
T800 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1242245567 Feb 21 12:36:21 PM PST 24 Feb 21 12:36:24 PM PST 24 2056949559 ps
T801 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3971231612 Feb 21 12:36:32 PM PST 24 Feb 21 12:36:40 PM PST 24 2010895587 ps
T301 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1122583709 Feb 21 12:36:11 PM PST 24 Feb 21 12:36:22 PM PST 24 4030771086 ps
T71 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2344963791 Feb 21 12:36:01 PM PST 24 Feb 21 12:36:15 PM PST 24 10333852617 ps
T302 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.128179551 Feb 21 12:36:03 PM PST 24 Feb 21 12:36:07 PM PST 24 2058192682 ps
T802 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2699557806 Feb 21 12:36:30 PM PST 24 Feb 21 12:36:43 PM PST 24 2015721254 ps
T311 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1332429950 Feb 21 12:35:56 PM PST 24 Feb 21 12:36:05 PM PST 24 10670014530 ps
T247 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.4086122115 Feb 21 12:36:12 PM PST 24 Feb 21 12:36:17 PM PST 24 2221491268 ps
T248 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2457239890 Feb 21 12:36:21 PM PST 24 Feb 21 12:36:26 PM PST 24 2582374635 ps
T303 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.865036734 Feb 21 12:36:17 PM PST 24 Feb 21 12:36:21 PM PST 24 2184209948 ps
T312 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3870731411 Feb 21 12:36:24 PM PST 24 Feb 21 12:36:26 PM PST 24 2189335093 ps
T251 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.391974687 Feb 21 12:36:12 PM PST 24 Feb 21 12:36:42 PM PST 24 42823539322 ps
T803 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.837597515 Feb 21 12:36:30 PM PST 24 Feb 21 12:36:35 PM PST 24 2035964019 ps
T252 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3859340412 Feb 21 12:36:02 PM PST 24 Feb 21 12:36:22 PM PST 24 22357544397 ps
T313 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3997468126 Feb 21 12:36:06 PM PST 24 Feb 21 12:36:08 PM PST 24 2082988013 ps
T314 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.10002031 Feb 21 12:36:11 PM PST 24 Feb 21 12:36:36 PM PST 24 5648637982 ps
T259 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3388352779 Feb 21 12:36:05 PM PST 24 Feb 21 12:36:14 PM PST 24 2115095541 ps
T804 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2071069347 Feb 21 12:36:38 PM PST 24 Feb 21 12:37:02 PM PST 24 5043716042 ps
T805 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1712502485 Feb 21 12:36:33 PM PST 24 Feb 21 12:36:49 PM PST 24 2025632339 ps
T304 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1781377175 Feb 21 12:36:12 PM PST 24 Feb 21 12:36:30 PM PST 24 6032434574 ps
T806 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1872941581 Feb 21 12:36:04 PM PST 24 Feb 21 12:36:10 PM PST 24 2014233320 ps
T305 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1598287680 Feb 21 12:36:30 PM PST 24 Feb 21 12:36:37 PM PST 24 2074418868 ps
T256 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3389693243 Feb 21 12:36:27 PM PST 24 Feb 21 12:36:32 PM PST 24 2531991567 ps
T807 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1961319767 Feb 21 12:36:32 PM PST 24 Feb 21 12:37:09 PM PST 24 8314160935 ps
T306 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3917650304 Feb 21 12:36:00 PM PST 24 Feb 21 12:37:00 PM PST 24 14879814018 ps
T808 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.674342242 Feb 21 12:36:33 PM PST 24 Feb 21 12:36:40 PM PST 24 2011727869 ps
T809 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3359779966 Feb 21 12:36:13 PM PST 24 Feb 21 12:36:27 PM PST 24 6005601852 ps
T810 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2534308649 Feb 21 12:36:30 PM PST 24 Feb 21 12:37:14 PM PST 24 10911057564 ps
T356 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.73782678 Feb 21 12:36:13 PM PST 24 Feb 21 12:37:10 PM PST 24 42514202249 ps
T811 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1516020926 Feb 21 12:36:22 PM PST 24 Feb 21 12:36:29 PM PST 24 2110806914 ps
T263 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1192434825 Feb 21 12:36:30 PM PST 24 Feb 21 12:36:39 PM PST 24 2025692030 ps
T262 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2827564219 Feb 21 12:36:34 PM PST 24 Feb 21 12:37:06 PM PST 24 42860502848 ps
T812 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1673725519 Feb 21 12:36:05 PM PST 24 Feb 21 12:36:18 PM PST 24 4014709067 ps
T307 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.330647575 Feb 21 12:36:07 PM PST 24 Feb 21 12:36:12 PM PST 24 2044302021 ps
T258 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3467042108 Feb 21 12:36:03 PM PST 24 Feb 21 12:36:11 PM PST 24 2022283466 ps
T813 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.967614593 Feb 21 12:36:35 PM PST 24 Feb 21 12:36:43 PM PST 24 2141161764 ps
T814 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2096610408 Feb 21 12:36:22 PM PST 24 Feb 21 12:36:23 PM PST 24 2157896429 ps
T261 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.812421435 Feb 21 12:36:06 PM PST 24 Feb 21 12:36:13 PM PST 24 2030658185 ps
T308 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2226173876 Feb 21 12:36:18 PM PST 24 Feb 21 12:37:09 PM PST 24 37248325520 ps
T815 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3196672275 Feb 21 12:36:05 PM PST 24 Feb 21 12:36:11 PM PST 24 2011421023 ps
T257 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1602219958 Feb 21 12:36:09 PM PST 24 Feb 21 12:36:14 PM PST 24 2107835925 ps
T309 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2554881422 Feb 21 12:36:18 PM PST 24 Feb 21 12:36:25 PM PST 24 2029069818 ps
T357 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2133726401 Feb 21 12:36:17 PM PST 24 Feb 21 12:36:33 PM PST 24 22251865816 ps
T264 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3210185476 Feb 21 12:36:27 PM PST 24 Feb 21 12:36:31 PM PST 24 2057556294 ps
T816 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1383247585 Feb 21 12:36:31 PM PST 24 Feb 21 12:36:36 PM PST 24 2096151083 ps
T310 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3507332461 Feb 21 12:36:05 PM PST 24 Feb 21 12:36:24 PM PST 24 6802082682 ps
T817 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2677041315 Feb 21 12:36:29 PM PST 24 Feb 21 12:36:46 PM PST 24 5226163917 ps
T818 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3621787594 Feb 21 12:36:41 PM PST 24 Feb 21 12:36:49 PM PST 24 2051710002 ps
T819 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.4080595328 Feb 21 12:36:09 PM PST 24 Feb 21 12:36:16 PM PST 24 3211148314 ps
T260 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.984254700 Feb 21 12:36:44 PM PST 24 Feb 21 12:36:50 PM PST 24 2074083429 ps
T820 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.10373711 Feb 21 12:36:02 PM PST 24 Feb 21 12:36:08 PM PST 24 2061818237 ps
T821 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1086070743 Feb 21 12:36:41 PM PST 24 Feb 21 12:36:50 PM PST 24 2073612804 ps
T822 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.4010806760 Feb 21 12:36:39 PM PST 24 Feb 21 12:36:43 PM PST 24 2045427582 ps
T823 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3161221595 Feb 21 12:36:47 PM PST 24 Feb 21 12:36:50 PM PST 24 2028462407 ps
T824 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.606856332 Feb 21 12:36:02 PM PST 24 Feb 21 12:36:08 PM PST 24 2035719839 ps
T825 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3737613472 Feb 21 12:36:34 PM PST 24 Feb 21 12:36:37 PM PST 24 2252457744 ps
T826 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2067376000 Feb 21 12:36:03 PM PST 24 Feb 21 12:36:06 PM PST 24 2111910144 ps
T827 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.4054383132 Feb 21 12:36:27 PM PST 24 Feb 21 12:36:31 PM PST 24 4895221429 ps
T828 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2993066496 Feb 21 12:35:47 PM PST 24 Feb 21 12:36:03 PM PST 24 6060966546 ps
T829 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1992612047 Feb 21 12:36:57 PM PST 24 Feb 21 12:37:05 PM PST 24 2037220526 ps
T830 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2340007956 Feb 21 12:36:28 PM PST 24 Feb 21 12:36:36 PM PST 24 2011583217 ps
T831 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1599797681 Feb 21 12:36:25 PM PST 24 Feb 21 12:36:28 PM PST 24 2043823163 ps
T832 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3652259851 Feb 21 12:36:03 PM PST 24 Feb 21 12:36:08 PM PST 24 2019747439 ps
T833 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.508904493 Feb 21 12:36:31 PM PST 24 Feb 21 12:36:41 PM PST 24 2031463951 ps
T834 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.810097600 Feb 21 12:36:29 PM PST 24 Feb 21 12:36:36 PM PST 24 2038484618 ps
T835 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2738675589 Feb 21 12:36:35 PM PST 24 Feb 21 12:36:38 PM PST 24 2244244593 ps
T836 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.405635763 Feb 21 12:36:32 PM PST 24 Feb 21 12:36:38 PM PST 24 2069152035 ps
T353 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.247073909 Feb 21 12:36:02 PM PST 24 Feb 21 12:36:36 PM PST 24 42459794908 ps
T837 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1256563728 Feb 21 12:36:02 PM PST 24 Feb 21 12:36:35 PM PST 24 42809316648 ps
T838 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1942370719 Feb 21 12:36:22 PM PST 24 Feb 21 12:36:34 PM PST 24 7791344165 ps
T839 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3900595566 Feb 21 12:36:03 PM PST 24 Feb 21 12:36:07 PM PST 24 2233400719 ps
T840 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.448922960 Feb 21 12:36:30 PM PST 24 Feb 21 12:36:39 PM PST 24 2014159094 ps
T354 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1308202601 Feb 21 12:36:04 PM PST 24 Feb 21 12:37:02 PM PST 24 42386761516 ps
T841 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3645043541 Feb 21 12:36:05 PM PST 24 Feb 21 12:36:10 PM PST 24 5027003029 ps
T842 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1030459205 Feb 21 12:36:34 PM PST 24 Feb 21 12:36:43 PM PST 24 5383394152 ps
T843 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1904343419 Feb 21 12:36:04 PM PST 24 Feb 21 12:36:12 PM PST 24 2060331094 ps
T844 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.167031076 Feb 21 12:36:02 PM PST 24 Feb 21 12:36:06 PM PST 24 2046501512 ps
T845 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2360498650 Feb 21 12:36:02 PM PST 24 Feb 21 12:36:06 PM PST 24 2126542577 ps
T846 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.464294049 Feb 21 12:36:24 PM PST 24 Feb 21 12:36:28 PM PST 24 2065586172 ps
T847 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.312896321 Feb 21 12:36:12 PM PST 24 Feb 21 12:36:15 PM PST 24 2229902361 ps
T848 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1153065528 Feb 21 12:36:23 PM PST 24 Feb 21 12:36:29 PM PST 24 2056977495 ps
T849 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.334642904 Feb 21 12:36:38 PM PST 24 Feb 21 12:36:46 PM PST 24 2013885678 ps
T850 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1561832407 Feb 21 12:36:27 PM PST 24 Feb 21 12:36:33 PM PST 24 2010319607 ps
T851 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1561338887 Feb 21 12:36:28 PM PST 24 Feb 21 12:36:35 PM PST 24 2013228119 ps
T852 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3886181001 Feb 21 12:36:28 PM PST 24 Feb 21 12:36:40 PM PST 24 2091208610 ps
T853 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3205777406 Feb 21 12:36:29 PM PST 24 Feb 21 12:36:36 PM PST 24 2172548587 ps
T854 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.100577012 Feb 21 12:36:33 PM PST 24 Feb 21 12:36:40 PM PST 24 2011455988 ps
T855 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2320192516 Feb 21 12:36:03 PM PST 24 Feb 21 12:36:11 PM PST 24 2033326731 ps
T856 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2665315495 Feb 21 12:36:05 PM PST 24 Feb 21 12:36:13 PM PST 24 2040891569 ps
T857 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.133520316 Feb 21 12:36:04 PM PST 24 Feb 21 12:36:11 PM PST 24 2013693318 ps
T858 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3614172471 Feb 21 12:36:21 PM PST 24 Feb 21 12:36:28 PM PST 24 2011244842 ps
T859 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2199870937 Feb 21 12:36:34 PM PST 24 Feb 21 12:36:37 PM PST 24 2212541725 ps
T860 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3702640302 Feb 21 12:36:02 PM PST 24 Feb 21 12:36:35 PM PST 24 22190602584 ps
T861 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2067694533 Feb 21 12:36:32 PM PST 24 Feb 21 12:36:39 PM PST 24 2012820495 ps
T862 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.2114990936 Feb 21 12:36:21 PM PST 24 Feb 21 12:36:29 PM PST 24 2063155687 ps
T863 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.18128765 Feb 21 12:36:51 PM PST 24 Feb 21 12:36:54 PM PST 24 2254561247 ps
T864 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3807682544 Feb 21 12:36:12 PM PST 24 Feb 21 12:36:17 PM PST 24 2058748194 ps
T865 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1608591918 Feb 21 12:36:29 PM PST 24 Feb 21 12:36:39 PM PST 24 2125144534 ps
T866 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.203511819 Feb 21 12:36:41 PM PST 24 Feb 21 12:36:44 PM PST 24 2059282380 ps
T867 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2377239972 Feb 21 12:36:10 PM PST 24 Feb 21 12:36:16 PM PST 24 12674387801 ps
T868 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.644996935 Feb 21 12:36:30 PM PST 24 Feb 21 12:37:02 PM PST 24 22225984051 ps
T869 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.876620086 Feb 21 12:36:32 PM PST 24 Feb 21 12:36:38 PM PST 24 4850537565 ps
T870 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2781858936 Feb 21 12:36:02 PM PST 24 Feb 21 12:39:11 PM PST 24 74765595892 ps
T871 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.296418484 Feb 21 12:36:07 PM PST 24 Feb 21 12:36:15 PM PST 24 8067947677 ps
T872 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2117808526 Feb 21 12:36:38 PM PST 24 Feb 21 12:36:46 PM PST 24 2015462514 ps
T873 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3351232601 Feb 21 12:36:05 PM PST 24 Feb 21 12:36:52 PM PST 24 42599509307 ps
T874 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.439316494 Feb 21 12:36:30 PM PST 24 Feb 21 12:36:37 PM PST 24 2096601266 ps
T875 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2725408881 Feb 21 12:36:05 PM PST 24 Feb 21 12:36:31 PM PST 24 9757624505 ps
T876 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3122269206 Feb 21 12:36:50 PM PST 24 Feb 21 12:37:22 PM PST 24 22278445251 ps
T877 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.567813305 Feb 21 12:36:35 PM PST 24 Feb 21 12:38:12 PM PST 24 42465341714 ps
T878 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3078198393 Feb 21 12:36:07 PM PST 24 Feb 21 12:36:19 PM PST 24 4017375673 ps
T879 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3069195431 Feb 21 12:36:08 PM PST 24 Feb 21 12:36:14 PM PST 24 2034384706 ps
T880 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3574818533 Feb 21 12:36:05 PM PST 24 Feb 21 12:36:09 PM PST 24 2076460778 ps
T881 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1734967814 Feb 21 12:36:04 PM PST 24 Feb 21 12:37:58 PM PST 24 42367483366 ps
T882 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2417023218 Feb 21 12:36:29 PM PST 24 Feb 21 12:36:34 PM PST 24 2093864144 ps
T883 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3701078468 Feb 21 12:36:16 PM PST 24 Feb 21 12:36:19 PM PST 24 2038977285 ps
T884 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3204429560 Feb 21 12:36:06 PM PST 24 Feb 21 12:36:09 PM PST 24 2037331628 ps
T885 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.354810146 Feb 21 12:36:30 PM PST 24 Feb 21 12:36:39 PM PST 24 2229599777 ps
T886 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.756975769 Feb 21 12:36:31 PM PST 24 Feb 21 12:36:40 PM PST 24 2011770275 ps
T887 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2273923665 Feb 21 12:36:25 PM PST 24 Feb 21 12:36:37 PM PST 24 2041459917 ps
T888 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3382777954 Feb 21 12:36:37 PM PST 24 Feb 21 12:36:40 PM PST 24 2049116811 ps
T889 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3024580573 Feb 21 12:36:11 PM PST 24 Feb 21 12:36:42 PM PST 24 22258890783 ps
T890 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2015677535 Feb 21 12:36:32 PM PST 24 Feb 21 12:37:34 PM PST 24 22221840514 ps
T355 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2968911325 Feb 21 12:36:03 PM PST 24 Feb 21 12:37:03 PM PST 24 22217473675 ps
T891 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3894498952 Feb 21 12:36:14 PM PST 24 Feb 21 12:36:31 PM PST 24 2562532127 ps
T892 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.409209044 Feb 21 12:36:10 PM PST 24 Feb 21 12:36:16 PM PST 24 2038217237 ps
T893 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1833438298 Feb 21 12:36:14 PM PST 24 Feb 21 12:36:26 PM PST 24 5491569601 ps
T894 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3998874065 Feb 21 12:36:21 PM PST 24 Feb 21 12:36:24 PM PST 24 2036950651 ps
T895 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1906631758 Feb 21 12:35:59 PM PST 24 Feb 21 12:36:08 PM PST 24 2122001144 ps
T896 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3118922650 Feb 21 12:36:14 PM PST 24 Feb 21 12:36:23 PM PST 24 11867526114 ps
T897 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.4002757144 Feb 21 12:36:46 PM PST 24 Feb 21 12:36:53 PM PST 24 2031141450 ps
T898 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1130637922 Feb 21 12:36:02 PM PST 24 Feb 21 12:37:02 PM PST 24 42540712351 ps
T899 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2223554757 Feb 21 12:36:34 PM PST 24 Feb 21 12:36:38 PM PST 24 2027177188 ps
T900 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.548546634 Feb 21 12:36:22 PM PST 24 Feb 21 12:36:29 PM PST 24 2122838232 ps
T901 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.891029060 Feb 21 12:36:17 PM PST 24 Feb 21 12:36:19 PM PST 24 2041810857 ps
T902 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3932355014 Feb 21 12:36:22 PM PST 24 Feb 21 12:36:26 PM PST 24 2020478639 ps
T903 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.903985578 Feb 21 12:36:19 PM PST 24 Feb 21 12:36:35 PM PST 24 22262894181 ps
T904 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.267163072 Feb 21 12:36:14 PM PST 24 Feb 21 12:36:22 PM PST 24 2011828264 ps
T905 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.500770156 Feb 21 12:36:29 PM PST 24 Feb 21 12:36:34 PM PST 24 2254561890 ps

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2014383335
Short name T2
Test name
Test status
Simulation time 67539719829 ps
CPU time 85.05 seconds
Started Feb 21 03:00:59 PM PST 24
Finished Feb 21 03:02:24 PM PST 24
Peak memory 210088 kb
Host smart-bcc7188f-1da7-4d24-9205-5c7dd265fa10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014383335 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2014383335
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2810120567
Short name T13
Test name
Test status
Simulation time 101648240350 ps
CPU time 272.48 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:04:54 PM PST 24
Peak memory 210104 kb
Host smart-9df12c6c-29c3-442f-8444-8133b7f8fd7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810120567 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.2810120567
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1511668401
Short name T14
Test name
Test status
Simulation time 64160490848 ps
CPU time 41.28 seconds
Started Feb 21 03:01:41 PM PST 24
Finished Feb 21 03:02:22 PM PST 24
Peak memory 201612 kb
Host smart-9d30d741-e3c1-438c-9fd1-7619f8b94d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511668401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.1511668401
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2305086036
Short name T291
Test name
Test status
Simulation time 326607127427 ps
CPU time 58.27 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:01:10 PM PST 24
Peak memory 210088 kb
Host smart-672cc089-14cc-4add-9583-b0dce0e536ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305086036 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.2305086036
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.518822355
Short name T75
Test name
Test status
Simulation time 29037623633 ps
CPU time 19.44 seconds
Started Feb 21 02:59:33 PM PST 24
Finished Feb 21 02:59:52 PM PST 24
Peak memory 201416 kb
Host smart-489e4bd5-237f-4a30-a86f-29c52e0bcf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518822355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.518822355
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1387132341
Short name T81
Test name
Test status
Simulation time 256068641877 ps
CPU time 82.07 seconds
Started Feb 21 03:01:10 PM PST 24
Finished Feb 21 03:02:32 PM PST 24
Peak memory 218108 kb
Host smart-d38f73f7-4790-4564-a1fa-57aac877c73f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387132341 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1387132341
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3152108660
Short name T38
Test name
Test status
Simulation time 42412527552 ps
CPU time 106.45 seconds
Started Feb 21 12:36:17 PM PST 24
Finished Feb 21 12:38:04 PM PST 24
Peak memory 201636 kb
Host smart-5f4f08c2-f4bc-4f80-b14b-3db218e57f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152108660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.3152108660
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.1430235369
Short name T43
Test name
Test status
Simulation time 3206472822 ps
CPU time 9.2 seconds
Started Feb 21 03:01:16 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201656 kb
Host smart-f324daf5-4c4d-4801-b2a7-bda431961e28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430235369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.1430235369
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.791279542
Short name T17
Test name
Test status
Simulation time 41273760845 ps
CPU time 24.5 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 210056 kb
Host smart-bc6709f7-9981-4196-93e3-e94a2ce699a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791279542 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.791279542
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.527004871
Short name T16
Test name
Test status
Simulation time 32511179555 ps
CPU time 47.72 seconds
Started Feb 21 03:00:05 PM PST 24
Finished Feb 21 03:00:53 PM PST 24
Peak memory 201608 kb
Host smart-11766c5e-5015-40f8-b2f3-62754cab39dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527004871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wit
h_pre_cond.527004871
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.2528883412
Short name T318
Test name
Test status
Simulation time 276706025239 ps
CPU time 188.45 seconds
Started Feb 21 03:00:24 PM PST 24
Finished Feb 21 03:03:33 PM PST 24
Peak memory 201636 kb
Host smart-11012efa-57a7-4a7c-8602-187781f9a2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528883412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.2528883412
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3405013730
Short name T73
Test name
Test status
Simulation time 150589865912 ps
CPU time 199.18 seconds
Started Feb 21 03:01:25 PM PST 24
Finished Feb 21 03:04:45 PM PST 24
Peak memory 209976 kb
Host smart-4d67a0bc-a43a-48e6-9a0b-a854987bfe7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405013730 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3405013730
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3351897042
Short name T10
Test name
Test status
Simulation time 72704251761 ps
CPU time 125.04 seconds
Started Feb 21 03:00:40 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 201644 kb
Host smart-b6764a09-5602-4a82-a640-4cea6212ffbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351897042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.3351897042
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.359466570
Short name T84
Test name
Test status
Simulation time 63695624982 ps
CPU time 24.15 seconds
Started Feb 21 03:00:59 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 210028 kb
Host smart-944a4406-f13f-42d1-a1b9-28766d7fb40b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359466570 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.359466570
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3754666634
Short name T144
Test name
Test status
Simulation time 42008409216 ps
CPU time 100.12 seconds
Started Feb 21 02:59:51 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 221136 kb
Host smart-dad09b20-9b8f-4b17-826d-c98f293c42b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754666634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.3754666634
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.4265875575
Short name T77
Test name
Test status
Simulation time 2494107080 ps
CPU time 6.67 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201424 kb
Host smart-e59eec19-e8ce-4cd1-b216-ea897570ab5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265875575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.4265875575
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2344963791
Short name T71
Test name
Test status
Simulation time 10333852617 ps
CPU time 13.77 seconds
Started Feb 21 12:36:01 PM PST 24
Finished Feb 21 12:36:15 PM PST 24
Peak memory 201648 kb
Host smart-1033f037-a9fa-4c2b-b046-b6ce82e47db5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344963791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.2344963791
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.275489279
Short name T233
Test name
Test status
Simulation time 321651455707 ps
CPU time 89.91 seconds
Started Feb 21 03:00:59 PM PST 24
Finished Feb 21 03:02:30 PM PST 24
Peak memory 214232 kb
Host smart-b75564a9-99c2-4b91-84bf-331aa67a5ce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275489279 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.275489279
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.1040346378
Short name T78
Test name
Test status
Simulation time 105626758696 ps
CPU time 44.38 seconds
Started Feb 21 03:00:39 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201660 kb
Host smart-4ffe2d3c-9840-44bb-9c1a-108a5f670c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040346378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.1040346378
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4175676947
Short name T226
Test name
Test status
Simulation time 88827579107 ps
CPU time 121.68 seconds
Started Feb 21 03:01:50 PM PST 24
Finished Feb 21 03:03:52 PM PST 24
Peak memory 201604 kb
Host smart-2d67a2ef-5d7c-4e4d-a08f-f2f1f99e8df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175676947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.4175676947
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.1465312106
Short name T21
Test name
Test status
Simulation time 1021729163114 ps
CPU time 331.45 seconds
Started Feb 21 03:00:24 PM PST 24
Finished Feb 21 03:05:55 PM PST 24
Peak memory 201476 kb
Host smart-d11e6a0e-c5e3-4968-979f-0d66450adaf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465312106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.1465312106
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3389693243
Short name T256
Test name
Test status
Simulation time 2531991567 ps
CPU time 4.11 seconds
Started Feb 21 12:36:27 PM PST 24
Finished Feb 21 12:36:32 PM PST 24
Peak memory 201520 kb
Host smart-590f2aff-9070-4b42-8cdb-0a011410a00c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389693243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.3389693243
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.4094018210
Short name T194
Test name
Test status
Simulation time 583693937955 ps
CPU time 275.09 seconds
Started Feb 21 03:00:32 PM PST 24
Finished Feb 21 03:05:08 PM PST 24
Peak memory 218032 kb
Host smart-00cf86e6-6f87-42d6-9902-abc1c7ec5dff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094018210 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.4094018210
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.1832870632
Short name T145
Test name
Test status
Simulation time 15219927707 ps
CPU time 10.1 seconds
Started Feb 21 03:00:02 PM PST 24
Finished Feb 21 03:00:13 PM PST 24
Peak memory 201428 kb
Host smart-140ac24b-bd48-44d1-8598-6b2e4e64dea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832870632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.1832870632
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3381174209
Short name T69
Test name
Test status
Simulation time 74413897485 ps
CPU time 49.56 seconds
Started Feb 21 03:00:25 PM PST 24
Finished Feb 21 03:01:15 PM PST 24
Peak memory 201620 kb
Host smart-5ce62236-6d6c-425c-8623-dd66c0e11040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381174209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.3381174209
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.4197676670
Short name T99
Test name
Test status
Simulation time 207686419959 ps
CPU time 302.98 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:05:26 PM PST 24
Peak memory 210056 kb
Host smart-9602e13b-e34b-4bd8-a891-e7dd4883868a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197676670 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.4197676670
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1524525101
Short name T3
Test name
Test status
Simulation time 8010299369 ps
CPU time 7.18 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:29 PM PST 24
Peak memory 201420 kb
Host smart-e1e68942-8f82-491c-9a02-6791eb5deff1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524525101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.1524525101
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1598287680
Short name T305
Test name
Test status
Simulation time 2074418868 ps
CPU time 3.75 seconds
Started Feb 21 12:36:30 PM PST 24
Finished Feb 21 12:36:37 PM PST 24
Peak memory 201224 kb
Host smart-bcfa0a99-d437-4492-9c9e-6f288c755189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598287680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1598287680
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.3147745901
Short name T211
Test name
Test status
Simulation time 2025781514 ps
CPU time 2.52 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:11 PM PST 24
Peak memory 201420 kb
Host smart-37f2afa3-0e3a-486b-a0fc-1d01e2e344d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147745901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.3147745901
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3837568047
Short name T244
Test name
Test status
Simulation time 98135836333 ps
CPU time 68.29 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201672 kb
Host smart-78fc661e-e833-4fec-a34c-d018dc585c23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837568047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.3837568047
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1689705132
Short name T224
Test name
Test status
Simulation time 66914919814 ps
CPU time 90.29 seconds
Started Feb 21 03:01:36 PM PST 24
Finished Feb 21 03:03:06 PM PST 24
Peak memory 201672 kb
Host smart-e308477d-1d16-4dd8-8f0e-1aa018c958b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689705132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.1689705132
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1031156267
Short name T76
Test name
Test status
Simulation time 34752802412 ps
CPU time 85.71 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:01:38 PM PST 24
Peak memory 201408 kb
Host smart-94269b1b-86d2-469e-a079-a75df022a084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031156267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.1031156267
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.395536319
Short name T15
Test name
Test status
Simulation time 65675826589 ps
CPU time 82.46 seconds
Started Feb 21 02:59:57 PM PST 24
Finished Feb 21 03:01:21 PM PST 24
Peak memory 213808 kb
Host smart-7313ecde-e6aa-41d6-823c-793d73689356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395536319 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.395536319
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.1912983446
Short name T350
Test name
Test status
Simulation time 150766998352 ps
CPU time 35.39 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:58 PM PST 24
Peak memory 201596 kb
Host smart-b22eaa12-e756-4840-bff1-ea2fa508e0fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912983446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.1912983446
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.404441779
Short name T45
Test name
Test status
Simulation time 113285410828 ps
CPU time 242.3 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:05:23 PM PST 24
Peak memory 201696 kb
Host smart-cb503ae5-c799-4892-9255-bccf4ab8a337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404441779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_wi
th_pre_cond.404441779
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.984254700
Short name T260
Test name
Test status
Simulation time 2074083429 ps
CPU time 4.49 seconds
Started Feb 21 12:36:44 PM PST 24
Finished Feb 21 12:36:50 PM PST 24
Peak memory 201496 kb
Host smart-0a4d5b8c-a345-4700-88cd-f9d93dec0b58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984254700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_error
s.984254700
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.3134815957
Short name T324
Test name
Test status
Simulation time 109728764795 ps
CPU time 236.18 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:03:57 PM PST 24
Peak memory 201624 kb
Host smart-c554c104-5cdf-40bd-9caa-a5dbea0d3779
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134815957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.3134815957
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.1639062452
Short name T316
Test name
Test status
Simulation time 108173981475 ps
CPU time 260.69 seconds
Started Feb 21 03:01:15 PM PST 24
Finished Feb 21 03:05:37 PM PST 24
Peak memory 201604 kb
Host smart-d534b318-290e-4e6f-af9f-7d9abccd2669
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639062452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.1639062452
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3021572834
Short name T338
Test name
Test status
Simulation time 139663678046 ps
CPU time 176.27 seconds
Started Feb 21 03:01:48 PM PST 24
Finished Feb 21 03:04:45 PM PST 24
Peak memory 201624 kb
Host smart-c61475fa-0805-4454-809e-24cb498d0b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021572834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.3021572834
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1071199293
Short name T79
Test name
Test status
Simulation time 74046074992 ps
CPU time 95.51 seconds
Started Feb 21 03:01:40 PM PST 24
Finished Feb 21 03:03:16 PM PST 24
Peak memory 200992 kb
Host smart-7f92b26e-3a34-4bac-80d7-d04b17d40347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071199293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.1071199293
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1717290358
Short name T24
Test name
Test status
Simulation time 3582288764 ps
CPU time 5.48 seconds
Started Feb 21 03:01:03 PM PST 24
Finished Feb 21 03:01:09 PM PST 24
Peak memory 201512 kb
Host smart-4c49fb12-b35b-4435-a86e-ca26572ac817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717290358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.1
717290358
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.3764018201
Short name T166
Test name
Test status
Simulation time 7723304236 ps
CPU time 5.19 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:35 PM PST 24
Peak memory 201436 kb
Host smart-e4b9bfa6-e19b-46ef-af89-b4a1ea30c8e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764018201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.3764018201
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.2875331987
Short name T147
Test name
Test status
Simulation time 3229473333 ps
CPU time 2.5 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:15 PM PST 24
Peak memory 201460 kb
Host smart-3ec9b7a9-d40d-4320-bbfe-710c37e649c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875331987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.2875331987
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1308202601
Short name T354
Test name
Test status
Simulation time 42386761516 ps
CPU time 56.47 seconds
Started Feb 21 12:36:04 PM PST 24
Finished Feb 21 12:37:02 PM PST 24
Peak memory 201608 kb
Host smart-18bc60a1-483e-4b3d-ae6d-3b9c83a2cbe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308202601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.1308202601
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.2693587655
Short name T362
Test name
Test status
Simulation time 1156969288883 ps
CPU time 575.72 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:09:55 PM PST 24
Peak memory 201716 kb
Host smart-d0c027b1-783f-4b72-ab3f-a806d7983564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693587655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.2693587655
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.948292034
Short name T40
Test name
Test status
Simulation time 66638151538 ps
CPU time 175.01 seconds
Started Feb 21 03:00:05 PM PST 24
Finished Feb 21 03:03:01 PM PST 24
Peak memory 201676 kb
Host smart-d83312b8-9e70-4cbb-bcef-d267fca7f444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948292034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_wi
th_pre_cond.948292034
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.325442458
Short name T339
Test name
Test status
Simulation time 55925080436 ps
CPU time 37.39 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:59 PM PST 24
Peak memory 201668 kb
Host smart-8e209c25-d9ba-40f6-be72-b02e52085c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325442458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_wi
th_pre_cond.325442458
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.423061911
Short name T243
Test name
Test status
Simulation time 146603356727 ps
CPU time 390.53 seconds
Started Feb 21 03:01:42 PM PST 24
Finished Feb 21 03:08:14 PM PST 24
Peak memory 201640 kb
Host smart-b264c852-4545-471d-9d3d-85996d07940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423061911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_wi
th_pre_cond.423061911
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2407666242
Short name T341
Test name
Test status
Simulation time 98948995857 ps
CPU time 255.08 seconds
Started Feb 21 03:01:48 PM PST 24
Finished Feb 21 03:06:04 PM PST 24
Peak memory 201608 kb
Host smart-a93cb6dd-5f90-4114-b9c7-78013a664c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407666242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.2407666242
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.4281318458
Short name T164
Test name
Test status
Simulation time 12319701711 ps
CPU time 28.34 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:52 PM PST 24
Peak memory 201488 kb
Host smart-dbd2a59a-5325-4d82-8be0-904d037d1f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281318458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.4281318458
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2345460779
Short name T195
Test name
Test status
Simulation time 3991956005 ps
CPU time 9.18 seconds
Started Feb 21 02:59:50 PM PST 24
Finished Feb 21 03:00:00 PM PST 24
Peak memory 201388 kb
Host smart-95cb8ed1-e870-4a94-a27e-f377308f8e13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345460779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.2345460779
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3206285996
Short name T594
Test name
Test status
Simulation time 6737134442 ps
CPU time 1.3 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:00:13 PM PST 24
Peak memory 201432 kb
Host smart-b7f6ae15-dc71-41b5-bbca-b5286d54c700
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206285996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.3206285996
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.4005443310
Short name T239
Test name
Test status
Simulation time 51660775627 ps
CPU time 65.04 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 03:00:37 PM PST 24
Peak memory 201612 kb
Host smart-dafb20e5-02dd-4d5a-8d92-2f5f95a1259a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005443310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.4005443310
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.415506399
Short name T126
Test name
Test status
Simulation time 126538536432 ps
CPU time 33.65 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201432 kb
Host smart-6ee9176f-20f6-41c7-a548-a673b91659fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415506399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_ultra_low_pwr.415506399
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3015247213
Short name T335
Test name
Test status
Simulation time 111241421537 ps
CPU time 139.77 seconds
Started Feb 21 03:00:51 PM PST 24
Finished Feb 21 03:03:11 PM PST 24
Peak memory 201620 kb
Host smart-85793157-6da4-4c59-92cd-41e18186877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015247213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.3015247213
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.2180603597
Short name T320
Test name
Test status
Simulation time 96015370007 ps
CPU time 136.61 seconds
Started Feb 21 03:00:58 PM PST 24
Finished Feb 21 03:03:15 PM PST 24
Peak memory 201620 kb
Host smart-29284777-5f13-4cdd-9566-1bb3cb3d2678
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180603597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.2180603597
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.764630702
Short name T225
Test name
Test status
Simulation time 78852391987 ps
CPU time 56.3 seconds
Started Feb 21 03:01:16 PM PST 24
Finished Feb 21 03:02:13 PM PST 24
Peak memory 201612 kb
Host smart-50501cd4-b09c-4886-9ed5-e8c253ca5355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764630702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_wi
th_pre_cond.764630702
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2893648517
Short name T334
Test name
Test status
Simulation time 71402789906 ps
CPU time 91.69 seconds
Started Feb 21 03:01:29 PM PST 24
Finished Feb 21 03:03:01 PM PST 24
Peak memory 201660 kb
Host smart-42036ccd-06a2-4948-9f7d-e34bed0c5e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893648517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2893648517
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3804458876
Short name T337
Test name
Test status
Simulation time 115017297886 ps
CPU time 310.66 seconds
Started Feb 21 03:01:41 PM PST 24
Finished Feb 21 03:06:53 PM PST 24
Peak memory 201640 kb
Host smart-160a7df0-90cf-4092-9840-83645488da71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804458876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.3804458876
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2854998592
Short name T336
Test name
Test status
Simulation time 87696678981 ps
CPU time 54.82 seconds
Started Feb 21 03:01:38 PM PST 24
Finished Feb 21 03:02:33 PM PST 24
Peak memory 201700 kb
Host smart-bfd2f7c2-bb24-4a47-8b2b-3b22dbd2074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854998592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2854998592
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3088478675
Short name T342
Test name
Test status
Simulation time 38228081963 ps
CPU time 30.45 seconds
Started Feb 21 03:01:43 PM PST 24
Finished Feb 21 03:02:14 PM PST 24
Peak memory 201636 kb
Host smart-de8b99a1-eb76-48b0-a875-925bc06f7f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088478675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.3088478675
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2682374751
Short name T347
Test name
Test status
Simulation time 111999615552 ps
CPU time 303.67 seconds
Started Feb 21 03:01:36 PM PST 24
Finished Feb 21 03:06:41 PM PST 24
Peak memory 201624 kb
Host smart-1850b5b7-f3b5-44a2-8697-05b08ea4866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682374751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.2682374751
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.2657487333
Short name T170
Test name
Test status
Simulation time 2188698074 ps
CPU time 1.11 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:50 PM PST 24
Peak memory 201392 kb
Host smart-6d7d7992-5307-4dff-a337-d465b6fe5f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657487333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.2657487333
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3388352779
Short name T259
Test name
Test status
Simulation time 2115095541 ps
CPU time 7.84 seconds
Started Feb 21 12:36:05 PM PST 24
Finished Feb 21 12:36:14 PM PST 24
Peak memory 201384 kb
Host smart-9f11510c-d1ba-4c7f-9c58-d521613b08be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388352779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.3388352779
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1871026207
Short name T158
Test name
Test status
Simulation time 31047500823 ps
CPU time 79.45 seconds
Started Feb 21 03:01:37 PM PST 24
Finished Feb 21 03:02:57 PM PST 24
Peak memory 201804 kb
Host smart-dd215980-f5c9-4f0a-a343-df74dec723af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871026207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.1871026207
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3894498952
Short name T891
Test name
Test status
Simulation time 2562532127 ps
CPU time 11.33 seconds
Started Feb 21 12:36:14 PM PST 24
Finished Feb 21 12:36:31 PM PST 24
Peak memory 201548 kb
Host smart-6ed01413-d1e2-4302-957d-66af0ae82cda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894498952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.3894498952
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2377239972
Short name T867
Test name
Test status
Simulation time 12674387801 ps
CPU time 6.05 seconds
Started Feb 21 12:36:10 PM PST 24
Finished Feb 21 12:36:16 PM PST 24
Peak memory 201492 kb
Host smart-7df01fc3-7062-473b-b7e9-f00ff5e8b3d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377239972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.2377239972
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2993066496
Short name T828
Test name
Test status
Simulation time 6060966546 ps
CPU time 15.92 seconds
Started Feb 21 12:35:47 PM PST 24
Finished Feb 21 12:36:03 PM PST 24
Peak memory 201208 kb
Host smart-5d4d6990-226b-441d-a881-d7b8c6082a50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993066496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.2993066496
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1516020926
Short name T811
Test name
Test status
Simulation time 2110806914 ps
CPU time 6.3 seconds
Started Feb 21 12:36:22 PM PST 24
Finished Feb 21 12:36:29 PM PST 24
Peak memory 201408 kb
Host smart-748fc2af-f425-4745-bd91-258467017a98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516020926 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1516020926
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.167031076
Short name T844
Test name
Test status
Simulation time 2046501512 ps
CPU time 1.94 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:36:06 PM PST 24
Peak memory 200932 kb
Host smart-ab2b2a64-cdb3-4e08-86f7-90e929fa9fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167031076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test
.167031076
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1332429950
Short name T311
Test name
Test status
Simulation time 10670014530 ps
CPU time 8.45 seconds
Started Feb 21 12:35:56 PM PST 24
Finished Feb 21 12:36:05 PM PST 24
Peak memory 201628 kb
Host smart-a9ac7caa-50fa-47b2-9edf-784763e785b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332429950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.1332429950
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.812421435
Short name T261
Test name
Test status
Simulation time 2030658185 ps
CPU time 6.85 seconds
Started Feb 21 12:36:06 PM PST 24
Finished Feb 21 12:36:13 PM PST 24
Peak memory 209588 kb
Host smart-d2b44c12-d890-4d13-a52e-deb6735257f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812421435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors
.812421435
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1130637922
Short name T898
Test name
Test status
Simulation time 42540712351 ps
CPU time 57.83 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:37:02 PM PST 24
Peak memory 201592 kb
Host smart-bb095ef0-a8c2-4f35-870e-33d2fd753bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130637922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.1130637922
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.354810146
Short name T885
Test name
Test status
Simulation time 2229599777 ps
CPU time 6.08 seconds
Started Feb 21 12:36:30 PM PST 24
Finished Feb 21 12:36:39 PM PST 24
Peak memory 201804 kb
Host smart-ed862828-a64e-439a-bb98-606cc370948d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354810146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_aliasing.354810146
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2226173876
Short name T308
Test name
Test status
Simulation time 37248325520 ps
CPU time 50.08 seconds
Started Feb 21 12:36:18 PM PST 24
Finished Feb 21 12:37:09 PM PST 24
Peak memory 201828 kb
Host smart-8c822977-3cde-453c-9df7-ba5b5f2e1e5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226173876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.2226173876
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3078198393
Short name T878
Test name
Test status
Simulation time 4017375673 ps
CPU time 11.26 seconds
Started Feb 21 12:36:07 PM PST 24
Finished Feb 21 12:36:19 PM PST 24
Peak memory 201256 kb
Host smart-b221a5e8-6716-4006-a4fb-1315a660f19d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078198393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.3078198393
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1440954640
Short name T292
Test name
Test status
Simulation time 2055025298 ps
CPU time 6.17 seconds
Started Feb 21 12:36:10 PM PST 24
Finished Feb 21 12:36:17 PM PST 24
Peak memory 201312 kb
Host smart-3ab3d616-21fa-47bd-bac6-1ad663b56005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440954640 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1440954640
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2554881422
Short name T309
Test name
Test status
Simulation time 2029069818 ps
CPU time 6.5 seconds
Started Feb 21 12:36:18 PM PST 24
Finished Feb 21 12:36:25 PM PST 24
Peak memory 201184 kb
Host smart-40e99340-dd62-4481-9f3f-7523ae321fcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554881422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2554881422
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3196672275
Short name T815
Test name
Test status
Simulation time 2011421023 ps
CPU time 5.33 seconds
Started Feb 21 12:36:05 PM PST 24
Finished Feb 21 12:36:11 PM PST 24
Peak memory 200872 kb
Host smart-edb6907b-f10b-45a9-8037-23e66e3f0ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196672275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.3196672275
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3118922650
Short name T896
Test name
Test status
Simulation time 11867526114 ps
CPU time 6.72 seconds
Started Feb 21 12:36:14 PM PST 24
Finished Feb 21 12:36:23 PM PST 24
Peak memory 201572 kb
Host smart-231dc088-5bbf-46e8-a96a-63da6070c348
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118922650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.3118922650
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1734967814
Short name T881
Test name
Test status
Simulation time 42367483366 ps
CPU time 112.73 seconds
Started Feb 21 12:36:04 PM PST 24
Finished Feb 21 12:37:58 PM PST 24
Peak memory 201728 kb
Host smart-5daa55d0-2ac0-4186-a147-c72d443dd6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734967814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.1734967814
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.500770156
Short name T905
Test name
Test status
Simulation time 2254561890 ps
CPU time 2.41 seconds
Started Feb 21 12:36:29 PM PST 24
Finished Feb 21 12:36:34 PM PST 24
Peak memory 201396 kb
Host smart-598f373c-d6b6-4004-aca3-57e32ba1dde1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500770156 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.500770156
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3997468126
Short name T313
Test name
Test status
Simulation time 2082988013 ps
CPU time 1.57 seconds
Started Feb 21 12:36:06 PM PST 24
Finished Feb 21 12:36:08 PM PST 24
Peak memory 201288 kb
Host smart-b5034ec0-4d6f-463e-b483-2f204d785464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997468126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3997468126
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.267163072
Short name T904
Test name
Test status
Simulation time 2011828264 ps
CPU time 6.3 seconds
Started Feb 21 12:36:14 PM PST 24
Finished Feb 21 12:36:22 PM PST 24
Peak memory 200908 kb
Host smart-bc40962e-6984-464a-82aa-a1da0a22e208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267163072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_tes
t.267163072
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.296418484
Short name T871
Test name
Test status
Simulation time 8067947677 ps
CPU time 6.9 seconds
Started Feb 21 12:36:07 PM PST 24
Finished Feb 21 12:36:15 PM PST 24
Peak memory 201588 kb
Host smart-2268adb8-cc43-47eb-8583-b1a12505ba27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296418484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_same_csr_outstanding.296418484
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1608591918
Short name T865
Test name
Test status
Simulation time 2125144534 ps
CPU time 6.46 seconds
Started Feb 21 12:36:29 PM PST 24
Finished Feb 21 12:36:39 PM PST 24
Peak memory 201384 kb
Host smart-2a64f4e6-2c32-4b31-8db4-6d518800ff45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608591918 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1608591918
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3870731411
Short name T312
Test name
Test status
Simulation time 2189335093 ps
CPU time 1.64 seconds
Started Feb 21 12:36:24 PM PST 24
Finished Feb 21 12:36:26 PM PST 24
Peak memory 201344 kb
Host smart-9974857f-8eef-4ac7-8b18-b89c5a017d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870731411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.3870731411
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.590437704
Short name T788
Test name
Test status
Simulation time 2013962322 ps
CPU time 5.67 seconds
Started Feb 21 12:36:29 PM PST 24
Finished Feb 21 12:36:35 PM PST 24
Peak memory 201036 kb
Host smart-9296878f-d786-48c2-bb21-4f2fd9f703bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590437704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.590437704
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1942370719
Short name T838
Test name
Test status
Simulation time 7791344165 ps
CPU time 11.02 seconds
Started Feb 21 12:36:22 PM PST 24
Finished Feb 21 12:36:34 PM PST 24
Peak memory 201560 kb
Host smart-c4702c79-47dd-4f91-b927-103ed43b1cfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942370719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.1942370719
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2665315495
Short name T856
Test name
Test status
Simulation time 2040891569 ps
CPU time 7.58 seconds
Started Feb 21 12:36:05 PM PST 24
Finished Feb 21 12:36:13 PM PST 24
Peak memory 201576 kb
Host smart-5945928b-2c35-4a5d-89ff-5c7356802fad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665315495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2665315495
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3024580573
Short name T889
Test name
Test status
Simulation time 22258890783 ps
CPU time 31.1 seconds
Started Feb 21 12:36:11 PM PST 24
Finished Feb 21 12:36:42 PM PST 24
Peak memory 201580 kb
Host smart-9d46a285-b5ff-4752-a530-a79b8d0bb447
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024580573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.3024580573
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3900595566
Short name T839
Test name
Test status
Simulation time 2233400719 ps
CPU time 2.41 seconds
Started Feb 21 12:36:03 PM PST 24
Finished Feb 21 12:36:07 PM PST 24
Peak memory 201460 kb
Host smart-0a4b9ef1-0206-4bfc-8eb5-24b304203990
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900595566 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3900595566
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2320192516
Short name T855
Test name
Test status
Simulation time 2033326731 ps
CPU time 6 seconds
Started Feb 21 12:36:03 PM PST 24
Finished Feb 21 12:36:11 PM PST 24
Peak memory 201368 kb
Host smart-61a5ff02-31af-4b8a-811b-82b798e06df7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320192516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.2320192516
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2096610408
Short name T814
Test name
Test status
Simulation time 2157896429 ps
CPU time 1.05 seconds
Started Feb 21 12:36:22 PM PST 24
Finished Feb 21 12:36:23 PM PST 24
Peak memory 200884 kb
Host smart-e07cd7ad-0e5a-4d7f-b38f-88772939c111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096610408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2096610408
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.4054383132
Short name T827
Test name
Test status
Simulation time 4895221429 ps
CPU time 3.03 seconds
Started Feb 21 12:36:27 PM PST 24
Finished Feb 21 12:36:31 PM PST 24
Peak memory 201692 kb
Host smart-ba7b3f37-0f10-4243-8a06-4222b127c242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054383132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.4054383132
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.810097600
Short name T834
Test name
Test status
Simulation time 2038484618 ps
CPU time 5.16 seconds
Started Feb 21 12:36:29 PM PST 24
Finished Feb 21 12:36:36 PM PST 24
Peak memory 201448 kb
Host smart-cde4546f-d0bb-4f48-aeda-0ed445668ec5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810097600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_error
s.810097600
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.247073909
Short name T353
Test name
Test status
Simulation time 42459794908 ps
CPU time 31.49 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:36:36 PM PST 24
Peak memory 201568 kb
Host smart-9ee2faa2-6fb9-4b81-8175-d11f396bbea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247073909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_tl_intg_err.247073909
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1383247585
Short name T816
Test name
Test status
Simulation time 2096151083 ps
CPU time 2.27 seconds
Started Feb 21 12:36:31 PM PST 24
Finished Feb 21 12:36:36 PM PST 24
Peak memory 201400 kb
Host smart-4249a855-4720-4513-a829-14354d6244b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383247585 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1383247585
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.10373711
Short name T820
Test name
Test status
Simulation time 2061818237 ps
CPU time 3.56 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:36:08 PM PST 24
Peak memory 201232 kb
Host smart-135569e9-bf41-4f1d-a3fa-c35d84a6c0a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10373711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw
.10373711
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1859525098
Short name T795
Test name
Test status
Simulation time 2016072732 ps
CPU time 5.48 seconds
Started Feb 21 12:36:04 PM PST 24
Finished Feb 21 12:36:11 PM PST 24
Peak memory 200912 kb
Host smart-209d2c9b-dc0b-4a7a-b2b5-3a3536203684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859525098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.1859525098
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3645043541
Short name T841
Test name
Test status
Simulation time 5027003029 ps
CPU time 4.04 seconds
Started Feb 21 12:36:05 PM PST 24
Finished Feb 21 12:36:10 PM PST 24
Peak memory 201552 kb
Host smart-d6001aaa-c56c-4c67-a79b-069f64f72c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645043541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.3645043541
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1904343419
Short name T843
Test name
Test status
Simulation time 2060331094 ps
CPU time 6.65 seconds
Started Feb 21 12:36:04 PM PST 24
Finished Feb 21 12:36:12 PM PST 24
Peak memory 201480 kb
Host smart-0eaa0c9e-262b-4c16-978d-7b6001780d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904343419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.1904343419
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.903985578
Short name T903
Test name
Test status
Simulation time 22262894181 ps
CPU time 16.03 seconds
Started Feb 21 12:36:19 PM PST 24
Finished Feb 21 12:36:35 PM PST 24
Peak memory 201652 kb
Host smart-93de015c-e206-4d60-a53c-72ce219d0f28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903985578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_tl_intg_err.903985578
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.464294049
Short name T846
Test name
Test status
Simulation time 2065586172 ps
CPU time 3.58 seconds
Started Feb 21 12:36:24 PM PST 24
Finished Feb 21 12:36:28 PM PST 24
Peak memory 201324 kb
Host smart-2b3c2ae3-444f-4208-922f-80629fae6844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464294049 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.464294049
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.409209044
Short name T892
Test name
Test status
Simulation time 2038217237 ps
CPU time 5.85 seconds
Started Feb 21 12:36:10 PM PST 24
Finished Feb 21 12:36:16 PM PST 24
Peak memory 201276 kb
Host smart-19861227-506e-4d97-bc7c-a0649a85bd82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409209044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r
w.409209044
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3206669282
Short name T787
Test name
Test status
Simulation time 2034729943 ps
CPU time 2.02 seconds
Started Feb 21 12:36:28 PM PST 24
Finished Feb 21 12:36:32 PM PST 24
Peak memory 200796 kb
Host smart-1394af9d-0141-4467-8cec-9c932800083a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206669282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.3206669282
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2679264981
Short name T37
Test name
Test status
Simulation time 5149700033 ps
CPU time 2.59 seconds
Started Feb 21 12:36:31 PM PST 24
Finished Feb 21 12:36:36 PM PST 24
Peak memory 201672 kb
Host smart-dedaa962-ae63-467e-af04-bf5b96054bf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679264981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.2679264981
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.439316494
Short name T874
Test name
Test status
Simulation time 2096601266 ps
CPU time 4.06 seconds
Started Feb 21 12:36:30 PM PST 24
Finished Feb 21 12:36:37 PM PST 24
Peak memory 201488 kb
Host smart-5b734774-ed69-4673-b93c-f7e6e6f66584
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439316494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_error
s.439316494
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.567813305
Short name T877
Test name
Test status
Simulation time 42465341714 ps
CPU time 95.92 seconds
Started Feb 21 12:36:35 PM PST 24
Finished Feb 21 12:38:12 PM PST 24
Peak memory 201728 kb
Host smart-ab50e4b1-809c-48eb-b117-bd6bdff22aee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567813305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_tl_intg_err.567813305
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2199870937
Short name T859
Test name
Test status
Simulation time 2212541725 ps
CPU time 2.53 seconds
Started Feb 21 12:36:34 PM PST 24
Finished Feb 21 12:36:37 PM PST 24
Peak memory 201460 kb
Host smart-dc9990ac-9241-42d0-8a19-eee751943e6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199870937 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2199870937
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.4002757144
Short name T897
Test name
Test status
Simulation time 2031141450 ps
CPU time 6 seconds
Started Feb 21 12:36:46 PM PST 24
Finished Feb 21 12:36:53 PM PST 24
Peak memory 201308 kb
Host smart-89726c42-3c19-4b7f-b20f-d0cf644cd820
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002757144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.4002757144
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.153870120
Short name T793
Test name
Test status
Simulation time 2076121368 ps
CPU time 1.31 seconds
Started Feb 21 12:36:35 PM PST 24
Finished Feb 21 12:36:37 PM PST 24
Peak memory 200920 kb
Host smart-0f57417b-629b-45b5-b3ac-7921f08af916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153870120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_tes
t.153870120
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2534308649
Short name T810
Test name
Test status
Simulation time 10911057564 ps
CPU time 40.99 seconds
Started Feb 21 12:36:30 PM PST 24
Finished Feb 21 12:37:14 PM PST 24
Peak memory 201616 kb
Host smart-b2ae2519-8c7c-4039-8628-17b8767fb287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534308649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.2534308649
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3122269206
Short name T876
Test name
Test status
Simulation time 22278445251 ps
CPU time 32.01 seconds
Started Feb 21 12:36:50 PM PST 24
Finished Feb 21 12:37:22 PM PST 24
Peak memory 201628 kb
Host smart-eaaf453d-03cc-4459-a2ff-8e7eb24dc333
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122269206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.3122269206
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2738675589
Short name T835
Test name
Test status
Simulation time 2244244593 ps
CPU time 2.62 seconds
Started Feb 21 12:36:35 PM PST 24
Finished Feb 21 12:36:38 PM PST 24
Peak memory 201396 kb
Host smart-6b7d8c2b-f104-4fbd-8d8b-a434f36cd0de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738675589 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2738675589
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3886181001
Short name T852
Test name
Test status
Simulation time 2091208610 ps
CPU time 1.58 seconds
Started Feb 21 12:36:28 PM PST 24
Finished Feb 21 12:36:40 PM PST 24
Peak memory 201580 kb
Host smart-a431255e-3f7c-42f9-abec-d2a0df5550ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886181001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3886181001
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1599797681
Short name T831
Test name
Test status
Simulation time 2043823163 ps
CPU time 2 seconds
Started Feb 21 12:36:25 PM PST 24
Finished Feb 21 12:36:28 PM PST 24
Peak memory 201092 kb
Host smart-5506f4cd-2029-47c9-8981-a3d567b04601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599797681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.1599797681
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2677041315
Short name T817
Test name
Test status
Simulation time 5226163917 ps
CPU time 14.07 seconds
Started Feb 21 12:36:29 PM PST 24
Finished Feb 21 12:36:46 PM PST 24
Peak memory 201236 kb
Host smart-95debaed-f9b1-49dd-9685-15716e3f2958
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677041315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2677041315
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3210185476
Short name T264
Test name
Test status
Simulation time 2057556294 ps
CPU time 3.04 seconds
Started Feb 21 12:36:27 PM PST 24
Finished Feb 21 12:36:31 PM PST 24
Peak memory 201404 kb
Host smart-4c3c7e27-10b6-4d57-b0f4-617bd6d14f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210185476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.3210185476
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.644996935
Short name T868
Test name
Test status
Simulation time 22225984051 ps
CPU time 29.34 seconds
Started Feb 21 12:36:30 PM PST 24
Finished Feb 21 12:37:02 PM PST 24
Peak memory 201584 kb
Host smart-c7e3c258-6873-486f-bf54-8ac82146ba1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644996935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_tl_intg_err.644996935
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.967614593
Short name T813
Test name
Test status
Simulation time 2141161764 ps
CPU time 7.05 seconds
Started Feb 21 12:36:35 PM PST 24
Finished Feb 21 12:36:43 PM PST 24
Peak memory 201252 kb
Host smart-5005d29b-908e-4ef2-a696-ed5000d7d425
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967614593 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.967614593
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1992612047
Short name T829
Test name
Test status
Simulation time 2037220526 ps
CPU time 6.19 seconds
Started Feb 21 12:36:57 PM PST 24
Finished Feb 21 12:37:05 PM PST 24
Peak memory 201308 kb
Host smart-20231fbc-16f8-46ae-8864-589b1d936cf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992612047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.1992612047
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2117808526
Short name T872
Test name
Test status
Simulation time 2015462514 ps
CPU time 5.67 seconds
Started Feb 21 12:36:38 PM PST 24
Finished Feb 21 12:36:46 PM PST 24
Peak memory 200828 kb
Host smart-9aedd6fe-fc48-463a-8f00-7041027fac4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117808526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.2117808526
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1030459205
Short name T842
Test name
Test status
Simulation time 5383394152 ps
CPU time 8.25 seconds
Started Feb 21 12:36:34 PM PST 24
Finished Feb 21 12:36:43 PM PST 24
Peak memory 201708 kb
Host smart-bfd71e2f-57c5-4290-8215-caadc319e9eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030459205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.1030459205
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.405635763
Short name T836
Test name
Test status
Simulation time 2069152035 ps
CPU time 4.79 seconds
Started Feb 21 12:36:32 PM PST 24
Finished Feb 21 12:36:38 PM PST 24
Peak memory 201536 kb
Host smart-61ed1a2e-4283-482e-ac06-acc220737747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405635763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_error
s.405635763
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2015677535
Short name T890
Test name
Test status
Simulation time 22221840514 ps
CPU time 60.18 seconds
Started Feb 21 12:36:32 PM PST 24
Finished Feb 21 12:37:34 PM PST 24
Peak memory 201600 kb
Host smart-84b8d791-0058-4bc3-915c-fd9e4aebceae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015677535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.2015677535
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.18128765
Short name T863
Test name
Test status
Simulation time 2254561247 ps
CPU time 2.43 seconds
Started Feb 21 12:36:51 PM PST 24
Finished Feb 21 12:36:54 PM PST 24
Peak memory 201536 kb
Host smart-1e229df8-8d99-4cb5-9a84-2e6ab6b47232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128765 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.18128765
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2417023218
Short name T882
Test name
Test status
Simulation time 2093864144 ps
CPU time 1.86 seconds
Started Feb 21 12:36:29 PM PST 24
Finished Feb 21 12:36:34 PM PST 24
Peak memory 201276 kb
Host smart-eb2131e3-9642-4b5f-8158-2030e247885e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417023218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.2417023218
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.203511819
Short name T866
Test name
Test status
Simulation time 2059282380 ps
CPU time 1.61 seconds
Started Feb 21 12:36:41 PM PST 24
Finished Feb 21 12:36:44 PM PST 24
Peak memory 200928 kb
Host smart-571ae058-d845-4ed6-ae18-854c584a1779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203511819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_tes
t.203511819
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1961319767
Short name T807
Test name
Test status
Simulation time 8314160935 ps
CPU time 34.68 seconds
Started Feb 21 12:36:32 PM PST 24
Finished Feb 21 12:37:09 PM PST 24
Peak memory 201732 kb
Host smart-4fb00382-afa6-4c7f-b089-6a57ff9a3b85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961319767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.1961319767
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.508904493
Short name T833
Test name
Test status
Simulation time 2031463951 ps
CPU time 6.94 seconds
Started Feb 21 12:36:31 PM PST 24
Finished Feb 21 12:36:41 PM PST 24
Peak memory 201536 kb
Host smart-92d3c3f1-50cd-4084-a884-ddd52053623d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508904493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_error
s.508904493
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.391974687
Short name T251
Test name
Test status
Simulation time 42823539322 ps
CPU time 28.35 seconds
Started Feb 21 12:36:12 PM PST 24
Finished Feb 21 12:36:42 PM PST 24
Peak memory 201648 kb
Host smart-ac458f12-bbf1-457f-a261-6ce0f702c560
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391974687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_tl_intg_err.391974687
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1086070743
Short name T821
Test name
Test status
Simulation time 2073612804 ps
CPU time 6.04 seconds
Started Feb 21 12:36:41 PM PST 24
Finished Feb 21 12:36:50 PM PST 24
Peak memory 201316 kb
Host smart-3b7072d9-358a-4417-bcf2-dfa00e053e90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086070743 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1086070743
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2273923665
Short name T887
Test name
Test status
Simulation time 2041459917 ps
CPU time 3.66 seconds
Started Feb 21 12:36:25 PM PST 24
Finished Feb 21 12:36:37 PM PST 24
Peak memory 201148 kb
Host smart-588af2cc-8ce8-403d-aa01-8f88689d26b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273923665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.2273923665
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1242245567
Short name T800
Test name
Test status
Simulation time 2056949559 ps
CPU time 1.31 seconds
Started Feb 21 12:36:21 PM PST 24
Finished Feb 21 12:36:24 PM PST 24
Peak memory 200916 kb
Host smart-4f33e84f-c1eb-4f3b-8204-02981ef419fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242245567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.1242245567
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2071069347
Short name T804
Test name
Test status
Simulation time 5043716042 ps
CPU time 21.78 seconds
Started Feb 21 12:36:38 PM PST 24
Finished Feb 21 12:37:02 PM PST 24
Peak memory 201604 kb
Host smart-2df05de9-0862-44d8-9c58-1f511649bbae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071069347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.2071069347
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1192434825
Short name T263
Test name
Test status
Simulation time 2025692030 ps
CPU time 7.15 seconds
Started Feb 21 12:36:30 PM PST 24
Finished Feb 21 12:36:39 PM PST 24
Peak memory 201812 kb
Host smart-5410530f-7c2a-4928-89e4-4a20e3e56e59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192434825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.1192434825
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2827564219
Short name T262
Test name
Test status
Simulation time 42860502848 ps
CPU time 30.53 seconds
Started Feb 21 12:36:34 PM PST 24
Finished Feb 21 12:37:06 PM PST 24
Peak memory 201592 kb
Host smart-65d9a9c4-c7ea-4f05-b2af-77e3cddfc75a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827564219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2827564219
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.133470337
Short name T315
Test name
Test status
Simulation time 2509896936 ps
CPU time 5.29 seconds
Started Feb 21 12:36:27 PM PST 24
Finished Feb 21 12:36:33 PM PST 24
Peak memory 201416 kb
Host smart-7c825441-b31b-43b4-8e0e-a648c5c963dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133470337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_aliasing.133470337
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2781858936
Short name T870
Test name
Test status
Simulation time 74765595892 ps
CPU time 186.41 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:39:11 PM PST 24
Peak memory 201508 kb
Host smart-b696291d-1899-4e53-bcdd-05bc88bf067c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781858936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.2781858936
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1673725519
Short name T812
Test name
Test status
Simulation time 4014709067 ps
CPU time 11.54 seconds
Started Feb 21 12:36:05 PM PST 24
Finished Feb 21 12:36:18 PM PST 24
Peak memory 201236 kb
Host smart-30e3b4a4-663e-4a01-8f73-d2cd09795a8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673725519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.1673725519
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.548546634
Short name T900
Test name
Test status
Simulation time 2122838232 ps
CPU time 6.52 seconds
Started Feb 21 12:36:22 PM PST 24
Finished Feb 21 12:36:29 PM PST 24
Peak memory 201312 kb
Host smart-bbc64666-0955-499e-b407-eb7e95be5bbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548546634 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.548546634
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3807682544
Short name T864
Test name
Test status
Simulation time 2058748194 ps
CPU time 3.52 seconds
Started Feb 21 12:36:12 PM PST 24
Finished Feb 21 12:36:17 PM PST 24
Peak memory 201192 kb
Host smart-688c53d8-b0a8-4b51-aeef-94c54cb6197c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807682544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.3807682544
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1872941581
Short name T806
Test name
Test status
Simulation time 2014233320 ps
CPU time 4.96 seconds
Started Feb 21 12:36:04 PM PST 24
Finished Feb 21 12:36:10 PM PST 24
Peak memory 200996 kb
Host smart-5b1d4ef2-33f3-4a69-92ac-7d1941b47139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872941581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.1872941581
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2725408881
Short name T875
Test name
Test status
Simulation time 9757624505 ps
CPU time 25.25 seconds
Started Feb 21 12:36:05 PM PST 24
Finished Feb 21 12:36:31 PM PST 24
Peak memory 201588 kb
Host smart-c7be58c8-a81a-4a11-8df3-430560f6e652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725408881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.2725408881
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1153065528
Short name T848
Test name
Test status
Simulation time 2056977495 ps
CPU time 4.44 seconds
Started Feb 21 12:36:23 PM PST 24
Finished Feb 21 12:36:29 PM PST 24
Peak memory 201488 kb
Host smart-f57a510e-9ed1-4394-abf1-2b3129816872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153065528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.1153065528
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1256563728
Short name T837
Test name
Test status
Simulation time 42809316648 ps
CPU time 31.02 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:36:35 PM PST 24
Peak memory 201564 kb
Host smart-a15a10a4-ffc5-455e-b585-36610ef11c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256563728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.1256563728
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.448922960
Short name T840
Test name
Test status
Simulation time 2014159094 ps
CPU time 5.92 seconds
Started Feb 21 12:36:30 PM PST 24
Finished Feb 21 12:36:39 PM PST 24
Peak memory 200924 kb
Host smart-3a5b3840-05dd-4765-b762-0e97e6e57a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448922960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_tes
t.448922960
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3701078468
Short name T883
Test name
Test status
Simulation time 2038977285 ps
CPU time 1.9 seconds
Started Feb 21 12:36:16 PM PST 24
Finished Feb 21 12:36:19 PM PST 24
Peak memory 200808 kb
Host smart-0d217a0a-05a1-4f22-98d9-5316c2c26416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701078468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.3701078468
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2737004358
Short name T799
Test name
Test status
Simulation time 2030700432 ps
CPU time 2.22 seconds
Started Feb 21 12:36:26 PM PST 24
Finished Feb 21 12:36:29 PM PST 24
Peak memory 200872 kb
Host smart-75fe3fde-e6f9-4892-8f0e-db95d20d421f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737004358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.2737004358
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2067694533
Short name T861
Test name
Test status
Simulation time 2012820495 ps
CPU time 5.67 seconds
Started Feb 21 12:36:32 PM PST 24
Finished Feb 21 12:36:39 PM PST 24
Peak memory 200876 kb
Host smart-c08dcb8f-f444-4d53-8d32-cc1ca2c4d92c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067694533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.2067694533
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.891029060
Short name T901
Test name
Test status
Simulation time 2041810857 ps
CPU time 1.79 seconds
Started Feb 21 12:36:17 PM PST 24
Finished Feb 21 12:36:19 PM PST 24
Peak memory 200904 kb
Host smart-e5919fb4-0457-46ec-af62-cfcf65b5e4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891029060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_tes
t.891029060
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1561338887
Short name T851
Test name
Test status
Simulation time 2013228119 ps
CPU time 5.97 seconds
Started Feb 21 12:36:28 PM PST 24
Finished Feb 21 12:36:35 PM PST 24
Peak memory 200812 kb
Host smart-393a8b45-8f39-4909-b26b-7a59dc9bb566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561338887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.1561338887
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.674342242
Short name T808
Test name
Test status
Simulation time 2011727869 ps
CPU time 5.89 seconds
Started Feb 21 12:36:33 PM PST 24
Finished Feb 21 12:36:40 PM PST 24
Peak memory 200932 kb
Host smart-96f0fd0f-ce2d-47ac-a9f4-5434b11eaa90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674342242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_tes
t.674342242
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.4010806760
Short name T822
Test name
Test status
Simulation time 2045427582 ps
CPU time 2.05 seconds
Started Feb 21 12:36:39 PM PST 24
Finished Feb 21 12:36:43 PM PST 24
Peak memory 200972 kb
Host smart-86dacaa5-6d9a-4a44-ae32-90fde352aea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010806760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.4010806760
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.756975769
Short name T886
Test name
Test status
Simulation time 2011770275 ps
CPU time 6.06 seconds
Started Feb 21 12:36:31 PM PST 24
Finished Feb 21 12:36:40 PM PST 24
Peak memory 200988 kb
Host smart-09429c62-2653-4724-9693-7a672526a123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756975769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_tes
t.756975769
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3932355014
Short name T902
Test name
Test status
Simulation time 2020478639 ps
CPU time 3.36 seconds
Started Feb 21 12:36:22 PM PST 24
Finished Feb 21 12:36:26 PM PST 24
Peak memory 200900 kb
Host smart-99a3888a-4128-469a-862d-c06b4d8834d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932355014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.3932355014
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.4080595328
Short name T819
Test name
Test status
Simulation time 3211148314 ps
CPU time 5.71 seconds
Started Feb 21 12:36:09 PM PST 24
Finished Feb 21 12:36:16 PM PST 24
Peak memory 201588 kb
Host smart-8978dd07-b161-4cfe-9f02-08655b4eeacb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080595328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.4080595328
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3507332461
Short name T310
Test name
Test status
Simulation time 6802082682 ps
CPU time 17.95 seconds
Started Feb 21 12:36:05 PM PST 24
Finished Feb 21 12:36:24 PM PST 24
Peak memory 201564 kb
Host smart-f90f5cc1-618e-4a01-b6fd-0bcbbdd26158
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507332461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.3507332461
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1122583709
Short name T301
Test name
Test status
Simulation time 4030771086 ps
CPU time 10.53 seconds
Started Feb 21 12:36:11 PM PST 24
Finished Feb 21 12:36:22 PM PST 24
Peak memory 201236 kb
Host smart-728e8995-08db-4c25-a3ee-ef660b1afa59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122583709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.1122583709
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3737613472
Short name T825
Test name
Test status
Simulation time 2252457744 ps
CPU time 2.45 seconds
Started Feb 21 12:36:34 PM PST 24
Finished Feb 21 12:36:37 PM PST 24
Peak memory 201472 kb
Host smart-7fbd2d57-5e3a-4dc2-a0fa-a0a2cdbc6232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737613472 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3737613472
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.128179551
Short name T302
Test name
Test status
Simulation time 2058192682 ps
CPU time 2.2 seconds
Started Feb 21 12:36:03 PM PST 24
Finished Feb 21 12:36:07 PM PST 24
Peak memory 201172 kb
Host smart-d8f30003-2df7-479d-8348-0b038178f2cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128179551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw
.128179551
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3614172471
Short name T858
Test name
Test status
Simulation time 2011244842 ps
CPU time 5.99 seconds
Started Feb 21 12:36:21 PM PST 24
Finished Feb 21 12:36:28 PM PST 24
Peak memory 200856 kb
Host smart-4d5a1079-29ba-4d23-ae7a-5e571ea7cde6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614172471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.3614172471
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.10002031
Short name T314
Test name
Test status
Simulation time 5648637982 ps
CPU time 23.51 seconds
Started Feb 21 12:36:11 PM PST 24
Finished Feb 21 12:36:36 PM PST 24
Peak memory 201648 kb
Host smart-b0b47f52-5b25-45df-ba31-08cfb6823ff7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10002031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=
sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
ysrst_ctrl_same_csr_outstanding.10002031
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1906631758
Short name T895
Test name
Test status
Simulation time 2122001144 ps
CPU time 7.79 seconds
Started Feb 21 12:35:59 PM PST 24
Finished Feb 21 12:36:08 PM PST 24
Peak memory 201544 kb
Host smart-89d78636-5556-464f-a0ee-e6ef357d122f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906631758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.1906631758
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3702640302
Short name T860
Test name
Test status
Simulation time 22190602584 ps
CPU time 30.77 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:36:35 PM PST 24
Peak memory 201636 kb
Host smart-5c233d64-2661-4aef-b298-240720500689
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702640302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3702640302
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2699557806
Short name T802
Test name
Test status
Simulation time 2015721254 ps
CPU time 5.48 seconds
Started Feb 21 12:36:30 PM PST 24
Finished Feb 21 12:36:43 PM PST 24
Peak memory 201068 kb
Host smart-32884b18-d880-4c1e-a17e-6010f8b21a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699557806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.2699557806
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2340007956
Short name T830
Test name
Test status
Simulation time 2011583217 ps
CPU time 5.94 seconds
Started Feb 21 12:36:28 PM PST 24
Finished Feb 21 12:36:36 PM PST 24
Peak memory 200848 kb
Host smart-6ef14df5-fac1-458b-86e5-f64e223fc478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340007956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2340007956
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1712502485
Short name T805
Test name
Test status
Simulation time 2025632339 ps
CPU time 3.22 seconds
Started Feb 21 12:36:33 PM PST 24
Finished Feb 21 12:36:49 PM PST 24
Peak memory 200868 kb
Host smart-50efd707-1c40-4448-854c-1638836bfa54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712502485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.1712502485
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3481942258
Short name T797
Test name
Test status
Simulation time 2016110566 ps
CPU time 3.23 seconds
Started Feb 21 12:36:42 PM PST 24
Finished Feb 21 12:36:48 PM PST 24
Peak memory 200828 kb
Host smart-37b46e0b-663d-4231-bc31-4a6d46719cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481942258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.3481942258
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.100577012
Short name T854
Test name
Test status
Simulation time 2011455988 ps
CPU time 5.42 seconds
Started Feb 21 12:36:33 PM PST 24
Finished Feb 21 12:36:40 PM PST 24
Peak memory 200892 kb
Host smart-291f1243-3098-40a4-a863-0abf43db0308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100577012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_tes
t.100577012
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2896589990
Short name T796
Test name
Test status
Simulation time 2015690324 ps
CPU time 6.27 seconds
Started Feb 21 12:36:25 PM PST 24
Finished Feb 21 12:36:33 PM PST 24
Peak memory 200804 kb
Host smart-1cb7b3e4-2e34-466c-90dd-8704a65f6d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896589990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.2896589990
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3225039509
Short name T794
Test name
Test status
Simulation time 2043067701 ps
CPU time 1.83 seconds
Started Feb 21 12:36:31 PM PST 24
Finished Feb 21 12:36:35 PM PST 24
Peak memory 200956 kb
Host smart-bd6003d8-db56-41e1-8a6c-255b07776d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225039509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.3225039509
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.334642904
Short name T849
Test name
Test status
Simulation time 2013885678 ps
CPU time 5.7 seconds
Started Feb 21 12:36:38 PM PST 24
Finished Feb 21 12:36:46 PM PST 24
Peak memory 200928 kb
Host smart-ad86993c-997c-4f5f-b569-22f66884b966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334642904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_tes
t.334642904
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2223554757
Short name T899
Test name
Test status
Simulation time 2027177188 ps
CPU time 3.33 seconds
Started Feb 21 12:36:34 PM PST 24
Finished Feb 21 12:36:38 PM PST 24
Peak memory 200876 kb
Host smart-73829fe0-8453-476b-bead-8c4bd2680199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223554757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.2223554757
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3373260001
Short name T790
Test name
Test status
Simulation time 2034227397 ps
CPU time 2.04 seconds
Started Feb 21 12:36:33 PM PST 24
Finished Feb 21 12:36:37 PM PST 24
Peak memory 200932 kb
Host smart-5a6ff70b-3390-4219-9b5a-4ece789cab28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373260001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.3373260001
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.865036734
Short name T303
Test name
Test status
Simulation time 2184209948 ps
CPU time 3.5 seconds
Started Feb 21 12:36:17 PM PST 24
Finished Feb 21 12:36:21 PM PST 24
Peak memory 201356 kb
Host smart-68038ef5-74b7-4eb5-8c09-5a14a4249dff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865036734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_aliasing.865036734
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3917650304
Short name T306
Test name
Test status
Simulation time 14879814018 ps
CPU time 59.43 seconds
Started Feb 21 12:36:00 PM PST 24
Finished Feb 21 12:37:00 PM PST 24
Peak memory 201512 kb
Host smart-8a88bf9b-8ea4-4e8b-8f1e-26a6173582a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917650304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.3917650304
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1781377175
Short name T304
Test name
Test status
Simulation time 6032434574 ps
CPU time 15.92 seconds
Started Feb 21 12:36:12 PM PST 24
Finished Feb 21 12:36:30 PM PST 24
Peak memory 201240 kb
Host smart-8290312d-24a5-480e-a6b0-32f5682c5516
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781377175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.1781377175
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2360498650
Short name T845
Test name
Test status
Simulation time 2126542577 ps
CPU time 2.27 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:36:06 PM PST 24
Peak memory 201428 kb
Host smart-8e4a336a-e307-48bf-bacc-73bc110c142d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360498650 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2360498650
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.813111526
Short name T255
Test name
Test status
Simulation time 2112833168 ps
CPU time 2.24 seconds
Started Feb 21 12:36:06 PM PST 24
Finished Feb 21 12:36:09 PM PST 24
Peak memory 201268 kb
Host smart-9c7c664b-fdfe-42cd-a015-29d359df8ae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813111526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw
.813111526
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2067376000
Short name T826
Test name
Test status
Simulation time 2111910144 ps
CPU time 1.05 seconds
Started Feb 21 12:36:03 PM PST 24
Finished Feb 21 12:36:06 PM PST 24
Peak memory 200992 kb
Host smart-72f2cf9e-8a13-4d59-a4e8-b12a74a044fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067376000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.2067376000
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2457239890
Short name T248
Test name
Test status
Simulation time 2582374635 ps
CPU time 3.9 seconds
Started Feb 21 12:36:21 PM PST 24
Finished Feb 21 12:36:26 PM PST 24
Peak memory 201512 kb
Host smart-f521a5ed-ecac-4399-956e-9b014a1710ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457239890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.2457239890
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2968911325
Short name T355
Test name
Test status
Simulation time 22217473675 ps
CPU time 58.28 seconds
Started Feb 21 12:36:03 PM PST 24
Finished Feb 21 12:37:03 PM PST 24
Peak memory 201560 kb
Host smart-937362c3-ed80-44f5-8571-186e3f6fa171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968911325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.2968911325
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1978163192
Short name T792
Test name
Test status
Simulation time 2010674744 ps
CPU time 6.01 seconds
Started Feb 21 12:36:27 PM PST 24
Finished Feb 21 12:36:33 PM PST 24
Peak memory 200896 kb
Host smart-3268cd3b-cc36-4976-92e1-c66dd2410c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978163192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.1978163192
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1233928258
Short name T791
Test name
Test status
Simulation time 2039145321 ps
CPU time 1.95 seconds
Started Feb 21 12:36:28 PM PST 24
Finished Feb 21 12:36:30 PM PST 24
Peak memory 200868 kb
Host smart-7f06a310-2a15-4de0-a702-5f852c918d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233928258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.1233928258
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1561832407
Short name T850
Test name
Test status
Simulation time 2010319607 ps
CPU time 5.89 seconds
Started Feb 21 12:36:27 PM PST 24
Finished Feb 21 12:36:33 PM PST 24
Peak memory 200852 kb
Host smart-77009a82-0556-4459-95eb-4c6f189ab183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561832407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.1561832407
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.837597515
Short name T803
Test name
Test status
Simulation time 2035964019 ps
CPU time 2.01 seconds
Started Feb 21 12:36:30 PM PST 24
Finished Feb 21 12:36:35 PM PST 24
Peak memory 200952 kb
Host smart-5f9cf2d7-1bea-4398-ab03-f734c091a0ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837597515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.837597515
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3971231612
Short name T801
Test name
Test status
Simulation time 2010895587 ps
CPU time 6.15 seconds
Started Feb 21 12:36:32 PM PST 24
Finished Feb 21 12:36:40 PM PST 24
Peak memory 200832 kb
Host smart-3c5ba0e6-25fe-4b7c-9fc8-6e18478895d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971231612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.3971231612
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3161221595
Short name T823
Test name
Test status
Simulation time 2028462407 ps
CPU time 2.87 seconds
Started Feb 21 12:36:47 PM PST 24
Finished Feb 21 12:36:50 PM PST 24
Peak memory 200880 kb
Host smart-055838b1-2f76-4fb6-913f-f7fc9ae8a090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161221595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.3161221595
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3382777954
Short name T888
Test name
Test status
Simulation time 2049116811 ps
CPU time 1.94 seconds
Started Feb 21 12:36:37 PM PST 24
Finished Feb 21 12:36:40 PM PST 24
Peak memory 200880 kb
Host smart-9dd13f25-78be-4528-8e45-5d18df05a1bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382777954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.3382777954
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3131107877
Short name T798
Test name
Test status
Simulation time 2135450044 ps
CPU time 0.95 seconds
Started Feb 21 12:36:32 PM PST 24
Finished Feb 21 12:36:35 PM PST 24
Peak memory 200876 kb
Host smart-2ac92e63-abc7-42a3-9a87-f883dfadbbe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131107877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3131107877
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1909886739
Short name T786
Test name
Test status
Simulation time 2039651134 ps
CPU time 2.21 seconds
Started Feb 21 12:36:36 PM PST 24
Finished Feb 21 12:36:39 PM PST 24
Peak memory 201060 kb
Host smart-e78bc5aa-09b5-40b7-96f0-1c315d893619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909886739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.1909886739
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.16478261
Short name T789
Test name
Test status
Simulation time 2037646860 ps
CPU time 1.52 seconds
Started Feb 21 12:36:33 PM PST 24
Finished Feb 21 12:36:36 PM PST 24
Peak memory 200968 kb
Host smart-7d833236-e9c6-445b-bb10-da2cfa4b08a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16478261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test
.16478261
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3205777406
Short name T853
Test name
Test status
Simulation time 2172548587 ps
CPU time 3.79 seconds
Started Feb 21 12:36:29 PM PST 24
Finished Feb 21 12:36:36 PM PST 24
Peak memory 201760 kb
Host smart-78f7d0d0-1611-46d3-964a-8d7cc3ea345c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205777406 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3205777406
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3574818533
Short name T880
Test name
Test status
Simulation time 2076460778 ps
CPU time 2.47 seconds
Started Feb 21 12:36:05 PM PST 24
Finished Feb 21 12:36:09 PM PST 24
Peak memory 201308 kb
Host smart-d091f639-464a-4099-9336-029899aad383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574818533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.3574818533
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3652259851
Short name T832
Test name
Test status
Simulation time 2019747439 ps
CPU time 3.18 seconds
Started Feb 21 12:36:03 PM PST 24
Finished Feb 21 12:36:08 PM PST 24
Peak memory 200812 kb
Host smart-4b3467bc-c999-45fe-9143-18c4833ed671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652259851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.3652259851
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2749326161
Short name T39
Test name
Test status
Simulation time 10792440368 ps
CPU time 48.91 seconds
Started Feb 21 12:36:14 PM PST 24
Finished Feb 21 12:37:05 PM PST 24
Peak memory 201636 kb
Host smart-e932f712-5a04-4c66-850e-93fdbf94edc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749326161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.2749326161
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.4086122115
Short name T247
Test name
Test status
Simulation time 2221491268 ps
CPU time 2.89 seconds
Started Feb 21 12:36:12 PM PST 24
Finished Feb 21 12:36:17 PM PST 24
Peak memory 201520 kb
Host smart-fe8d3798-7318-4f61-8578-cfb318767190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086122115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.4086122115
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3351232601
Short name T873
Test name
Test status
Simulation time 42599509307 ps
CPU time 46.28 seconds
Started Feb 21 12:36:05 PM PST 24
Finished Feb 21 12:36:52 PM PST 24
Peak memory 201612 kb
Host smart-3d554668-ccdc-42af-bfc2-c812c5d97001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351232601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.3351232601
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1672440684
Short name T290
Test name
Test status
Simulation time 2124758514 ps
CPU time 2.39 seconds
Started Feb 21 12:36:20 PM PST 24
Finished Feb 21 12:36:22 PM PST 24
Peak memory 201624 kb
Host smart-25da9704-8423-4e42-831a-7d4fd49320ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672440684 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1672440684
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1611858392
Short name T35
Test name
Test status
Simulation time 2046377571 ps
CPU time 6.15 seconds
Started Feb 21 12:36:07 PM PST 24
Finished Feb 21 12:36:13 PM PST 24
Peak memory 201152 kb
Host smart-e68bfa0a-e448-4cf2-9cb5-23c103353ee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611858392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.1611858392
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.133520316
Short name T857
Test name
Test status
Simulation time 2013693318 ps
CPU time 5.98 seconds
Started Feb 21 12:36:04 PM PST 24
Finished Feb 21 12:36:11 PM PST 24
Peak memory 200936 kb
Host smart-ceddc13b-a347-4d5b-86f3-d91844ad3630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133520316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test
.133520316
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3376311400
Short name T36
Test name
Test status
Simulation time 8450207118 ps
CPU time 10.17 seconds
Started Feb 21 12:36:01 PM PST 24
Finished Feb 21 12:36:12 PM PST 24
Peak memory 201608 kb
Host smart-eac41d1a-5fbd-4fdd-9a8f-c913d031dcab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376311400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.3376311400
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.2114990936
Short name T862
Test name
Test status
Simulation time 2063155687 ps
CPU time 7.04 seconds
Started Feb 21 12:36:21 PM PST 24
Finished Feb 21 12:36:29 PM PST 24
Peak memory 201476 kb
Host smart-a41da14d-9eed-4207-967e-89f9f4869574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114990936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.2114990936
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3859340412
Short name T252
Test name
Test status
Simulation time 22357544397 ps
CPU time 17.75 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:36:22 PM PST 24
Peak memory 201652 kb
Host smart-3f5a499c-7e9d-4eba-ac04-d095aad11b98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859340412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3859340412
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.312896321
Short name T847
Test name
Test status
Simulation time 2229902361 ps
CPU time 2.32 seconds
Started Feb 21 12:36:12 PM PST 24
Finished Feb 21 12:36:15 PM PST 24
Peak memory 201460 kb
Host smart-e29cf3bc-2888-4fbb-9635-305727097da1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312896321 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.312896321
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3069195431
Short name T879
Test name
Test status
Simulation time 2034384706 ps
CPU time 4.76 seconds
Started Feb 21 12:36:08 PM PST 24
Finished Feb 21 12:36:14 PM PST 24
Peak memory 201188 kb
Host smart-831a3d60-f6a1-4dfe-be00-384bc9828f3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069195431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.3069195431
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3204429560
Short name T884
Test name
Test status
Simulation time 2037331628 ps
CPU time 1.81 seconds
Started Feb 21 12:36:06 PM PST 24
Finished Feb 21 12:36:09 PM PST 24
Peak memory 200868 kb
Host smart-db3fd92c-95af-4ccd-b53a-cfd326a116df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204429560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.3204429560
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.876620086
Short name T869
Test name
Test status
Simulation time 4850537565 ps
CPU time 3.8 seconds
Started Feb 21 12:36:32 PM PST 24
Finished Feb 21 12:36:38 PM PST 24
Peak memory 201636 kb
Host smart-6f82b726-2857-438c-8704-8d50b7f9b391
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876620086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
sysrst_ctrl_same_csr_outstanding.876620086
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3467042108
Short name T258
Test name
Test status
Simulation time 2022283466 ps
CPU time 6.16 seconds
Started Feb 21 12:36:03 PM PST 24
Finished Feb 21 12:36:11 PM PST 24
Peak memory 201212 kb
Host smart-aa321722-3e8d-4439-8518-042626cc23dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467042108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.3467042108
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.73782678
Short name T356
Test name
Test status
Simulation time 42514202249 ps
CPU time 55.06 seconds
Started Feb 21 12:36:13 PM PST 24
Finished Feb 21 12:37:10 PM PST 24
Peak memory 201956 kb
Host smart-e0689725-9fca-459f-8bed-d6b645008857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73782678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_tl_intg_err.73782678
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.4101065360
Short name T253
Test name
Test status
Simulation time 2253414283 ps
CPU time 2.43 seconds
Started Feb 21 12:36:29 PM PST 24
Finished Feb 21 12:36:34 PM PST 24
Peak memory 201040 kb
Host smart-9a023b52-b85f-4e86-b853-7e5e20c8ffdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101065360 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.4101065360
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.330647575
Short name T307
Test name
Test status
Simulation time 2044302021 ps
CPU time 3.87 seconds
Started Feb 21 12:36:07 PM PST 24
Finished Feb 21 12:36:12 PM PST 24
Peak memory 201280 kb
Host smart-7b107bad-5bae-4a9f-8368-08d282e37dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330647575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw
.330647575
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3621342379
Short name T785
Test name
Test status
Simulation time 2039226494 ps
CPU time 1.96 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:36:06 PM PST 24
Peak memory 200900 kb
Host smart-e34d3511-3ab8-4350-a136-5451881c40d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621342379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.3621342379
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3359779966
Short name T809
Test name
Test status
Simulation time 6005601852 ps
CPU time 12.45 seconds
Started Feb 21 12:36:13 PM PST 24
Finished Feb 21 12:36:27 PM PST 24
Peak memory 201784 kb
Host smart-0d9ef817-800f-4993-af61-3a9274a9d9d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359779966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.3359779966
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1602219958
Short name T257
Test name
Test status
Simulation time 2107835925 ps
CPU time 4.14 seconds
Started Feb 21 12:36:09 PM PST 24
Finished Feb 21 12:36:14 PM PST 24
Peak memory 201436 kb
Host smart-7f2ed828-652c-496b-aa31-0de3b7f26ef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602219958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.1602219958
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.500734411
Short name T254
Test name
Test status
Simulation time 2065038650 ps
CPU time 2.8 seconds
Started Feb 21 12:36:15 PM PST 24
Finished Feb 21 12:36:19 PM PST 24
Peak memory 201468 kb
Host smart-f8972cc4-4112-424b-95b0-56c67873c1f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500734411 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.500734411
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3621787594
Short name T818
Test name
Test status
Simulation time 2051710002 ps
CPU time 6.28 seconds
Started Feb 21 12:36:41 PM PST 24
Finished Feb 21 12:36:49 PM PST 24
Peak memory 201276 kb
Host smart-849f6604-cfd5-4941-ac93-0a2fb418cac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621787594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.3621787594
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3998874065
Short name T894
Test name
Test status
Simulation time 2036950651 ps
CPU time 1.97 seconds
Started Feb 21 12:36:21 PM PST 24
Finished Feb 21 12:36:24 PM PST 24
Peak memory 200692 kb
Host smart-b73b9f37-9751-47cc-9c5c-4eefa2655e03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998874065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.3998874065
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1833438298
Short name T893
Test name
Test status
Simulation time 5491569601 ps
CPU time 11 seconds
Started Feb 21 12:36:14 PM PST 24
Finished Feb 21 12:36:26 PM PST 24
Peak memory 201560 kb
Host smart-0008eb51-8f0e-4712-9d68-468bb6151fbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833438298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.1833438298
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.606856332
Short name T824
Test name
Test status
Simulation time 2035719839 ps
CPU time 3.92 seconds
Started Feb 21 12:36:02 PM PST 24
Finished Feb 21 12:36:08 PM PST 24
Peak memory 201436 kb
Host smart-11f14d4b-cc53-4b00-a42f-a6824c10c350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606856332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors
.606856332
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2133726401
Short name T357
Test name
Test status
Simulation time 22251865816 ps
CPU time 15.58 seconds
Started Feb 21 12:36:17 PM PST 24
Finished Feb 21 12:36:33 PM PST 24
Peak memory 201632 kb
Host smart-d87aaf09-3fdb-4866-ba24-fe33be439d81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133726401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2133726401
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.1532295848
Short name T139
Test name
Test status
Simulation time 2021404904 ps
CPU time 2.51 seconds
Started Feb 21 02:59:54 PM PST 24
Finished Feb 21 02:59:57 PM PST 24
Peak memory 201260 kb
Host smart-8dd27134-4c73-412f-97de-59d36a3e7ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532295848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.1532295848
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2739052927
Short name T592
Test name
Test status
Simulation time 3679276854 ps
CPU time 6.05 seconds
Started Feb 21 02:59:35 PM PST 24
Finished Feb 21 02:59:42 PM PST 24
Peak memory 201496 kb
Host smart-57901e82-16e0-4c46-b998-750f8ba544d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739052927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.2739052927
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.3361725942
Short name T177
Test name
Test status
Simulation time 146044817138 ps
CPU time 55.3 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 03:00:27 PM PST 24
Peak memory 201556 kb
Host smart-330741d4-61e3-4811-be66-46f78048831a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361725942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.3361725942
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2337739477
Short name T616
Test name
Test status
Simulation time 2424901362 ps
CPU time 3.99 seconds
Started Feb 21 02:59:26 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 201416 kb
Host smart-9ffdcc99-c396-41c6-9e5a-a0b8008e0b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337739477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2337739477
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.486308240
Short name T105
Test name
Test status
Simulation time 2272973040 ps
CPU time 3.87 seconds
Started Feb 21 02:59:34 PM PST 24
Finished Feb 21 02:59:38 PM PST 24
Peak memory 201400 kb
Host smart-044d8411-7873-42c3-a7cf-df0727e5b5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486308240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.486308240
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2136232817
Short name T701
Test name
Test status
Simulation time 3595104615 ps
CPU time 4.44 seconds
Started Feb 21 02:59:27 PM PST 24
Finished Feb 21 02:59:32 PM PST 24
Peak memory 201428 kb
Host smart-26d3e2f9-5bdf-4140-b348-578086168f4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136232817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.2136232817
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.4121969504
Short name T496
Test name
Test status
Simulation time 3012143644 ps
CPU time 6.74 seconds
Started Feb 21 02:59:23 PM PST 24
Finished Feb 21 02:59:30 PM PST 24
Peak memory 201404 kb
Host smart-779eb9aa-05d1-4bfe-a91f-c76000618af8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121969504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.4121969504
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3373982833
Short name T554
Test name
Test status
Simulation time 2614246542 ps
CPU time 7.07 seconds
Started Feb 21 02:59:39 PM PST 24
Finished Feb 21 02:59:46 PM PST 24
Peak memory 201384 kb
Host smart-d9d9fafa-e185-4dbb-beff-25856c8fd9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373982833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.3373982833
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1943634203
Short name T464
Test name
Test status
Simulation time 2471123812 ps
CPU time 7.26 seconds
Started Feb 21 02:59:35 PM PST 24
Finished Feb 21 02:59:43 PM PST 24
Peak memory 201424 kb
Host smart-7174ab90-e6ee-4ff2-86a5-acff30310699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943634203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1943634203
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.790852778
Short name T738
Test name
Test status
Simulation time 2202147687 ps
CPU time 6.55 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:38 PM PST 24
Peak memory 201404 kb
Host smart-dadf1fde-0a29-4f2a-9581-5bd14b30985a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790852778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.790852778
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.4201243684
Short name T521
Test name
Test status
Simulation time 2514934131 ps
CPU time 4.01 seconds
Started Feb 21 02:59:31 PM PST 24
Finished Feb 21 02:59:36 PM PST 24
Peak memory 201432 kb
Host smart-226730fa-a184-4400-a060-5277500b5865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201243684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.4201243684
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.496134496
Short name T249
Test name
Test status
Simulation time 42007658041 ps
CPU time 106.44 seconds
Started Feb 21 02:59:54 PM PST 24
Finished Feb 21 03:01:41 PM PST 24
Peak memory 221324 kb
Host smart-cef12c43-1ea7-489b-b044-9550d1c439ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496134496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.496134496
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.4127204735
Short name T455
Test name
Test status
Simulation time 2127871830 ps
CPU time 2.18 seconds
Started Feb 21 02:59:32 PM PST 24
Finished Feb 21 02:59:35 PM PST 24
Peak memory 201348 kb
Host smart-a233c6ba-2ebc-4880-a123-ed09a469e543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127204735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.4127204735
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.1069312246
Short name T698
Test name
Test status
Simulation time 6214774484 ps
CPU time 16.15 seconds
Started Feb 21 02:59:41 PM PST 24
Finished Feb 21 02:59:57 PM PST 24
Peak memory 201456 kb
Host smart-7d42ee7e-d39d-4047-bd97-8e0b46a0af63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069312246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.1069312246
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.4248848635
Short name T613
Test name
Test status
Simulation time 77704785002 ps
CPU time 112.19 seconds
Started Feb 21 02:59:30 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 218120 kb
Host smart-79f8df8f-aee8-4bc7-805d-6b6283104a68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248848635 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.4248848635
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1963222994
Short name T725
Test name
Test status
Simulation time 7276747304 ps
CPU time 6.28 seconds
Started Feb 21 02:59:32 PM PST 24
Finished Feb 21 02:59:39 PM PST 24
Peak memory 201432 kb
Host smart-cb74c95d-cbc2-4f7b-97dd-00128270beb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963222994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.1963222994
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.3011105419
Short name T533
Test name
Test status
Simulation time 2026564039 ps
CPU time 1.86 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:18 PM PST 24
Peak memory 201436 kb
Host smart-cc6068c2-88c3-49dc-b26a-f5522d3eca5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011105419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.3011105419
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2506669709
Short name T55
Test name
Test status
Simulation time 3293157738 ps
CPU time 9.12 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:58 PM PST 24
Peak memory 201432 kb
Host smart-35590cc8-1576-4822-a36f-2574498edfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506669709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.2506669709
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.3341100978
Short name T349
Test name
Test status
Simulation time 116941741804 ps
CPU time 39.93 seconds
Started Feb 21 02:59:58 PM PST 24
Finished Feb 21 03:00:38 PM PST 24
Peak memory 201580 kb
Host smart-15b80f8c-156c-41a3-8b93-184029ef0974
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341100978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.3341100978
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1460002577
Short name T437
Test name
Test status
Simulation time 2399522883 ps
CPU time 6.98 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201416 kb
Host smart-c8776ec2-229c-45cb-896d-742715b8f925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460002577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1460002577
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.44112350
Short name T732
Test name
Test status
Simulation time 2263479526 ps
CPU time 2.54 seconds
Started Feb 21 02:59:48 PM PST 24
Finished Feb 21 02:59:51 PM PST 24
Peak memory 201436 kb
Host smart-e5f6f7e2-baff-417b-a34f-304cf1b8db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44112350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_c
ond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_dete
ct_ec_rst_with_pre_cond.44112350
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2716229300
Short name T345
Test name
Test status
Simulation time 75445444610 ps
CPU time 85.55 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:01:37 PM PST 24
Peak memory 201612 kb
Host smart-887b6796-76aa-45e6-9eda-3a74e392dfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716229300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2716229300
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3107431895
Short name T387
Test name
Test status
Simulation time 4255718816 ps
CPU time 6.46 seconds
Started Feb 21 02:59:47 PM PST 24
Finished Feb 21 02:59:53 PM PST 24
Peak memory 201648 kb
Host smart-67d1fe47-5a65-488a-9bc1-7d0b6e2cb776
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107431895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.3107431895
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1301577324
Short name T130
Test name
Test status
Simulation time 3098036568 ps
CPU time 5.39 seconds
Started Feb 21 02:59:48 PM PST 24
Finished Feb 21 02:59:54 PM PST 24
Peak memory 201424 kb
Host smart-e1bed753-ee08-4d37-b247-3bf3f4138929
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301577324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.1301577324
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3494030149
Short name T388
Test name
Test status
Simulation time 2636799566 ps
CPU time 2.53 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201416 kb
Host smart-4abaee1b-721f-41ae-bdbd-ba2d22634345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494030149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.3494030149
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.4162243039
Short name T591
Test name
Test status
Simulation time 2460674487 ps
CPU time 8.27 seconds
Started Feb 21 02:59:41 PM PST 24
Finished Feb 21 02:59:50 PM PST 24
Peak memory 201376 kb
Host smart-51e05ef5-c5d2-42b2-aa74-273f407b166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162243039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.4162243039
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3564209938
Short name T526
Test name
Test status
Simulation time 2224823720 ps
CPU time 6.62 seconds
Started Feb 21 02:59:41 PM PST 24
Finished Feb 21 02:59:48 PM PST 24
Peak memory 201436 kb
Host smart-79674a07-2d7b-4fb9-a55f-48f494c29f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564209938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.3564209938
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3055001067
Short name T67
Test name
Test status
Simulation time 2514164030 ps
CPU time 7.45 seconds
Started Feb 21 03:00:03 PM PST 24
Finished Feb 21 03:00:11 PM PST 24
Peak memory 201436 kb
Host smart-9714881c-1b00-4203-8619-a6b33724b1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055001067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.3055001067
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.2079392314
Short name T443
Test name
Test status
Simulation time 2137502483 ps
CPU time 1.98 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:00:02 PM PST 24
Peak memory 201372 kb
Host smart-1455332b-7d9d-460a-895e-948f97567cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079392314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2079392314
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.3377663238
Short name T514
Test name
Test status
Simulation time 182397288901 ps
CPU time 449.09 seconds
Started Feb 21 02:59:42 PM PST 24
Finished Feb 21 03:07:11 PM PST 24
Peak memory 201572 kb
Host smart-f53a97f5-1ba1-49dd-81c3-ceacdc5baa08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377663238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.3377663238
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.977356875
Short name T602
Test name
Test status
Simulation time 2030139026 ps
CPU time 2.08 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:00:13 PM PST 24
Peak memory 201428 kb
Host smart-80748943-e39e-434f-9130-ea2785c6d032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977356875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_tes
t.977356875
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2651189558
Short name T430
Test name
Test status
Simulation time 3441884951 ps
CPU time 2.79 seconds
Started Feb 21 02:59:50 PM PST 24
Finished Feb 21 02:59:53 PM PST 24
Peak memory 201512 kb
Host smart-b81c345d-ba69-4ae7-bc11-2d460b037a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651189558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.2
651189558
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.3266873924
Short name T352
Test name
Test status
Simulation time 138241766541 ps
CPU time 364.24 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:06:23 PM PST 24
Peak memory 201620 kb
Host smart-5109a6d8-6626-48ad-9cb7-9f546e273c07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266873924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.3266873924
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2012269393
Short name T227
Test name
Test status
Simulation time 74496720002 ps
CPU time 96.27 seconds
Started Feb 21 03:00:09 PM PST 24
Finished Feb 21 03:01:46 PM PST 24
Peak memory 201608 kb
Host smart-82f35f8b-3434-4b30-9031-786a20dd3651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012269393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.2012269393
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1923355814
Short name T107
Test name
Test status
Simulation time 4531133416 ps
CPU time 12.07 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 201412 kb
Host smart-79ca7364-9fe7-4e45-a33a-adcdfff5cca1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923355814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.1923355814
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1403811368
Short name T85
Test name
Test status
Simulation time 4790818513 ps
CPU time 5.77 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:00:17 PM PST 24
Peak memory 201492 kb
Host smart-067de415-952c-4917-b90c-a674ce7184cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403811368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.1403811368
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1779131134
Short name T695
Test name
Test status
Simulation time 2629641640 ps
CPU time 2.09 seconds
Started Feb 21 02:59:56 PM PST 24
Finished Feb 21 02:59:59 PM PST 24
Peak memory 201220 kb
Host smart-ceccff6a-6ac4-4d8f-93eb-822179385ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779131134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.1779131134
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.842347446
Short name T281
Test name
Test status
Simulation time 2492730013 ps
CPU time 2.38 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:15 PM PST 24
Peak memory 201412 kb
Host smart-172a5909-d8f0-4c59-803f-ae3a842388e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842347446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.842347446
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.2103630045
Short name T131
Test name
Test status
Simulation time 2204985535 ps
CPU time 1.96 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:10 PM PST 24
Peak memory 201424 kb
Host smart-7f649155-eaad-410b-abda-449ea6538e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103630045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.2103630045
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.204062417
Short name T629
Test name
Test status
Simulation time 2532204721 ps
CPU time 2.42 seconds
Started Feb 21 02:59:50 PM PST 24
Finished Feb 21 02:59:53 PM PST 24
Peak memory 201408 kb
Host smart-e3863e9b-d280-4184-a15c-5c8ec56ee883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204062417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.204062417
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3789274078
Short name T358
Test name
Test status
Simulation time 110996528135 ps
CPU time 151.97 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:02:49 PM PST 24
Peak memory 210012 kb
Host smart-70b791b1-7be6-4da0-a27c-a981bf63a533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789274078 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.3789274078
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2121343280
Short name T746
Test name
Test status
Simulation time 6426719547 ps
CPU time 1.74 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201408 kb
Host smart-c5072a59-ef6d-476d-a0ed-14ed2060e278
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121343280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.2121343280
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.589776523
Short name T638
Test name
Test status
Simulation time 3533049367 ps
CPU time 5.67 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:35 PM PST 24
Peak memory 201532 kb
Host smart-e3d78096-1138-470a-bc44-3cf5cea14850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589776523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.589776523
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.2461566776
Short name T750
Test name
Test status
Simulation time 83236602207 ps
CPU time 57.39 seconds
Started Feb 21 03:00:33 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201608 kb
Host smart-3485269e-c728-4fc7-9892-5597f02ebd9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461566776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.2461566776
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1378384109
Short name T340
Test name
Test status
Simulation time 124788143047 ps
CPU time 180.66 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:03:23 PM PST 24
Peak memory 201672 kb
Host smart-4946ebfa-c628-4690-81fb-2f30e554ad88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378384109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.1378384109
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.4116842757
Short name T401
Test name
Test status
Simulation time 2961945761 ps
CPU time 1.7 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201376 kb
Host smart-5ffd8f58-6e86-4aa2-9465-26d037454183
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116842757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.4116842757
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.749703852
Short name T190
Test name
Test status
Simulation time 2724063707 ps
CPU time 2.17 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201456 kb
Host smart-bae53650-7e6a-419a-89ce-7f27e07c93cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749703852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctr
l_edge_detect.749703852
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.826561633
Short name T65
Test name
Test status
Simulation time 2625643510 ps
CPU time 2.37 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:25 PM PST 24
Peak memory 201456 kb
Host smart-aff26833-0fca-4462-865e-8b84278e1101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826561633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.826561633
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3121215219
Short name T27
Test name
Test status
Simulation time 2469635543 ps
CPU time 8.22 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:38 PM PST 24
Peak memory 201472 kb
Host smart-7aad6fdd-0ba3-4ae2-893d-a8c4a848dfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121215219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3121215219
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.875156310
Short name T429
Test name
Test status
Simulation time 2254061681 ps
CPU time 1.45 seconds
Started Feb 21 03:00:18 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201436 kb
Host smart-0fbd5b01-ff03-41cf-b12e-ea0829286907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875156310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.875156310
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.1290920319
Short name T389
Test name
Test status
Simulation time 2512211075 ps
CPU time 7.62 seconds
Started Feb 21 03:00:18 PM PST 24
Finished Feb 21 03:00:27 PM PST 24
Peak memory 201432 kb
Host smart-a45e175d-994d-428b-901c-723eb756c2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290920319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.1290920319
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.1151484598
Short name T417
Test name
Test status
Simulation time 2201634971 ps
CPU time 0.99 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:00:13 PM PST 24
Peak memory 201484 kb
Host smart-ec59e7e5-4004-4c45-9268-21d5fa65220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151484598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.1151484598
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.1208350379
Short name T678
Test name
Test status
Simulation time 8026531228 ps
CPU time 4.48 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201516 kb
Host smart-5190a864-3a51-413d-8789-38e166b5ce03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208350379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.1208350379
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2770592394
Short name T117
Test name
Test status
Simulation time 1315699249433 ps
CPU time 326.35 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:05:37 PM PST 24
Peak memory 210056 kb
Host smart-43916c5c-c5e3-4ac1-b1b8-47dd8abb7aa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770592394 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2770592394
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.2842499553
Short name T34
Test name
Test status
Simulation time 6985394659 ps
CPU time 4.16 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:00:22 PM PST 24
Peak memory 201408 kb
Host smart-a614c176-ef39-4146-8045-cae6d0da6a92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842499553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.2842499553
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1027792509
Short name T422
Test name
Test status
Simulation time 2070809252 ps
CPU time 1.34 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:17 PM PST 24
Peak memory 201432 kb
Host smart-66896813-7563-4b47-8d32-a616a922d32f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027792509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1027792509
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2357796387
Short name T505
Test name
Test status
Simulation time 3685969170 ps
CPU time 3.58 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201452 kb
Host smart-5d71fa91-f36b-47cb-98cb-f7b1ce0d0001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357796387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.2
357796387
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.916617768
Short name T90
Test name
Test status
Simulation time 27177529769 ps
CPU time 7.05 seconds
Started Feb 21 02:59:54 PM PST 24
Finished Feb 21 03:00:02 PM PST 24
Peak memory 201708 kb
Host smart-36f362e9-cf18-4343-b585-8e98a2701930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916617768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_wi
th_pre_cond.916617768
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2988610912
Short name T482
Test name
Test status
Simulation time 3012643395 ps
CPU time 7.8 seconds
Started Feb 21 03:00:01 PM PST 24
Finished Feb 21 03:00:10 PM PST 24
Peak memory 201424 kb
Host smart-d0b720e3-ebd0-4546-bb09-33f7ffead049
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988610912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.2988610912
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.405703763
Short name T478
Test name
Test status
Simulation time 2958402485 ps
CPU time 1.77 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:51 PM PST 24
Peak memory 201428 kb
Host smart-3222fc03-8845-4443-bdcb-9a0e6adc893f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405703763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctr
l_edge_detect.405703763
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.304400364
Short name T683
Test name
Test status
Simulation time 2636504041 ps
CPU time 2.28 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201432 kb
Host smart-a6d2c15c-adae-40b3-8269-9fcc42db7423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304400364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.304400364
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.726088992
Short name T477
Test name
Test status
Simulation time 2498655056 ps
CPU time 2.38 seconds
Started Feb 21 02:59:50 PM PST 24
Finished Feb 21 02:59:53 PM PST 24
Peak memory 201436 kb
Host smart-27f40490-bc79-4ac2-9495-d652fa41d5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726088992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.726088992
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3599696860
Short name T733
Test name
Test status
Simulation time 2151280060 ps
CPU time 1.36 seconds
Started Feb 21 02:59:48 PM PST 24
Finished Feb 21 02:59:50 PM PST 24
Peak memory 201448 kb
Host smart-bacbea33-3248-42fb-a521-bd6f242918b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599696860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.3599696860
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.2631231818
Short name T63
Test name
Test status
Simulation time 2512182262 ps
CPU time 7.03 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:00:25 PM PST 24
Peak memory 201380 kb
Host smart-8c5adc2e-2c71-4fd7-b0ab-fa37ae5dd802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631231818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.2631231818
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.2794901279
Short name T371
Test name
Test status
Simulation time 2125100143 ps
CPU time 2.86 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:00:14 PM PST 24
Peak memory 201296 kb
Host smart-10e3f213-f0ba-4563-8203-5d97d6e284b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794901279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2794901279
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.745431956
Short name T119
Test name
Test status
Simulation time 16307926301 ps
CPU time 10.08 seconds
Started Feb 21 03:00:06 PM PST 24
Finished Feb 21 03:00:16 PM PST 24
Peak memory 201468 kb
Host smart-b293983b-580b-4da5-983f-4e53463745fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745431956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_st
ress_all.745431956
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1361196506
Short name T617
Test name
Test status
Simulation time 6118455064 ps
CPU time 4.05 seconds
Started Feb 21 02:59:51 PM PST 24
Finished Feb 21 02:59:55 PM PST 24
Peak memory 201424 kb
Host smart-fdf86bdf-873d-4425-a146-cab6ca1f819e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361196506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.1361196506
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.1667788251
Short name T769
Test name
Test status
Simulation time 2022054541 ps
CPU time 3.44 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:00:03 PM PST 24
Peak memory 201452 kb
Host smart-45ff82b7-ddb6-49d2-a59d-707f8153bace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667788251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.1667788251
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1191114472
Short name T569
Test name
Test status
Simulation time 3998647788 ps
CPU time 3.34 seconds
Started Feb 21 03:00:01 PM PST 24
Finished Feb 21 03:00:05 PM PST 24
Peak memory 201508 kb
Host smart-7f00213a-b3b8-4325-9403-90994ec3ed11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191114472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.1
191114472
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.138195465
Short name T94
Test name
Test status
Simulation time 63620040838 ps
CPU time 162.75 seconds
Started Feb 21 02:59:52 PM PST 24
Finished Feb 21 03:02:35 PM PST 24
Peak memory 201576 kb
Host smart-ea50c101-a51a-4210-a1d5-b4c28624f15f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138195465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_combo_detect.138195465
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.3914761099
Short name T344
Test name
Test status
Simulation time 60492391459 ps
CPU time 82.69 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:01:41 PM PST 24
Peak memory 201660 kb
Host smart-509fb353-b788-4631-8be9-f322be77fbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914761099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.3914761099
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3684564593
Short name T609
Test name
Test status
Simulation time 3819785043 ps
CPU time 10.27 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:00:29 PM PST 24
Peak memory 201412 kb
Host smart-ed5603f5-a7ed-4c79-b244-93b1a7460a3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684564593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.3684564593
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.3367650782
Short name T149
Test name
Test status
Simulation time 2502471457 ps
CPU time 6.85 seconds
Started Feb 21 02:59:59 PM PST 24
Finished Feb 21 03:00:07 PM PST 24
Peak memory 201432 kb
Host smart-069c6472-ff98-41a1-91e9-88eb32545e33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367650782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.3367650782
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.945914856
Short name T555
Test name
Test status
Simulation time 2636977049 ps
CPU time 2.31 seconds
Started Feb 21 03:00:13 PM PST 24
Finished Feb 21 03:00:15 PM PST 24
Peak memory 201372 kb
Host smart-154c24ab-ad44-412d-865c-57f42fd5dd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945914856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.945914856
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.2300901756
Short name T598
Test name
Test status
Simulation time 2463572917 ps
CPU time 8.06 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:20 PM PST 24
Peak memory 201432 kb
Host smart-f2f0f5e7-bc47-4fb3-979c-8212e0889893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300901756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.2300901756
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1798432330
Short name T670
Test name
Test status
Simulation time 2180788680 ps
CPU time 6.31 seconds
Started Feb 21 03:00:14 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201444 kb
Host smart-a596ebde-9f16-4021-bf66-2548489492f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798432330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1798432330
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.2953047577
Short name T286
Test name
Test status
Simulation time 2511785608 ps
CPU time 7.28 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201432 kb
Host smart-6ff19ab8-da39-4ccd-bccd-8782e382a019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953047577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.2953047577
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.2965920024
Short name T152
Test name
Test status
Simulation time 2109330770 ps
CPU time 6.54 seconds
Started Feb 21 03:00:03 PM PST 24
Finished Feb 21 03:00:10 PM PST 24
Peak memory 201372 kb
Host smart-82810be9-671d-4f9d-991a-7b5688e23789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965920024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2965920024
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.1201835072
Short name T716
Test name
Test status
Simulation time 287460321343 ps
CPU time 284.67 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:05:04 PM PST 24
Peak memory 201476 kb
Host smart-0d5ce5b7-d4aa-4ee5-82c4-92f16e6515c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201835072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.1201835072
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2547158315
Short name T100
Test name
Test status
Simulation time 60857398632 ps
CPU time 42.66 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:55 PM PST 24
Peak memory 209936 kb
Host smart-4b5b9eda-6a01-4b91-80a1-43f885df0eac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547158315 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.2547158315
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.3890253952
Short name T213
Test name
Test status
Simulation time 2035952894 ps
CPU time 2 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:14 PM PST 24
Peak memory 201484 kb
Host smart-2c4cd229-2ce9-495e-9cbb-68977ffe607c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890253952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.3890253952
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1729160515
Short name T720
Test name
Test status
Simulation time 3620934149 ps
CPU time 1.1 seconds
Started Feb 21 03:00:09 PM PST 24
Finished Feb 21 03:00:11 PM PST 24
Peak memory 201436 kb
Host smart-2b39795b-5891-484f-a459-ea631f401ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729160515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1
729160515
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2937645679
Short name T473
Test name
Test status
Simulation time 41938882315 ps
CPU time 60.38 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:01:20 PM PST 24
Peak memory 201624 kb
Host smart-3f013795-ffa1-48ef-b3d9-1bccecf4a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937645679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.2937645679
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1664274770
Short name T394
Test name
Test status
Simulation time 2938964168 ps
CPU time 3.9 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:00:22 PM PST 24
Peak memory 201412 kb
Host smart-78993d62-09d7-496e-9edd-2602442505a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664274770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.1664274770
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.536616513
Short name T162
Test name
Test status
Simulation time 4340670713 ps
CPU time 1.2 seconds
Started Feb 21 03:00:14 PM PST 24
Finished Feb 21 03:00:15 PM PST 24
Peak memory 201408 kb
Host smart-b0f69371-455e-43c7-9aaa-b47adccd7373
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536616513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_edge_detect.536616513
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3986833843
Short name T378
Test name
Test status
Simulation time 2609239830 ps
CPU time 7.82 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201412 kb
Host smart-2b7ba97e-98cd-46b0-a807-8c224ba61197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986833843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.3986833843
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.607703854
Short name T445
Test name
Test status
Simulation time 2452762119 ps
CPU time 4.47 seconds
Started Feb 21 03:00:14 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201428 kb
Host smart-ecae2b86-765f-428c-a948-63ea4e827f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607703854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.607703854
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.1160189202
Short name T427
Test name
Test status
Simulation time 2245733544 ps
CPU time 2.21 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:00:03 PM PST 24
Peak memory 201404 kb
Host smart-8bb31a70-edeb-4e0c-a50a-f6a9451185dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160189202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.1160189202
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.4110952945
Short name T416
Test name
Test status
Simulation time 2518855602 ps
CPU time 2.6 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:00:03 PM PST 24
Peak memory 201380 kb
Host smart-6fb2b0d5-ff51-4efa-a8ab-ce619453fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110952945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.4110952945
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3712983946
Short name T439
Test name
Test status
Simulation time 2136298198 ps
CPU time 2.03 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:00:20 PM PST 24
Peak memory 201364 kb
Host smart-0156d768-b605-441c-9749-67ec19f8304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712983946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3712983946
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2630316844
Short name T484
Test name
Test status
Simulation time 7394683819 ps
CPU time 11.49 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 201488 kb
Host smart-d6d95d7c-4e59-4043-8148-af328381f1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630316844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2630316844
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.1500039697
Short name T33
Test name
Test status
Simulation time 6673843200 ps
CPU time 4.85 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 201428 kb
Host smart-5eb609f2-4163-493f-a348-25f186cfebe3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500039697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.1500039697
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.270275418
Short name T474
Test name
Test status
Simulation time 2026160822 ps
CPU time 1.98 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:10 PM PST 24
Peak memory 201448 kb
Host smart-f0b3c721-12ee-4eba-b72b-4e2c372999ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270275418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.270275418
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1719437502
Short name T619
Test name
Test status
Simulation time 3689821903 ps
CPU time 5.27 seconds
Started Feb 21 03:00:18 PM PST 24
Finished Feb 21 03:00:25 PM PST 24
Peak memory 201504 kb
Host smart-71491d9c-c4b7-4d54-8fd7-15b4a6e15813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719437502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.1
719437502
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.754438733
Short name T93
Test name
Test status
Simulation time 152880838988 ps
CPU time 211.07 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:03:50 PM PST 24
Peak memory 201576 kb
Host smart-29811457-bc60-4b2e-9d8d-4fe2b9cde5db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754438733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_combo_detect.754438733
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2524155639
Short name T500
Test name
Test status
Simulation time 3552010839 ps
CPU time 2.98 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:33 PM PST 24
Peak memory 201408 kb
Host smart-2c098349-528b-40e6-ac1b-3358573c96c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524155639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.2524155639
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3387192270
Short name T196
Test name
Test status
Simulation time 4548885978 ps
CPU time 3.98 seconds
Started Feb 21 03:00:18 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201428 kb
Host smart-fc9644cb-4f8c-448a-9732-ba9e4c009993
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387192270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.3387192270
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.367444194
Short name T133
Test name
Test status
Simulation time 2623333773 ps
CPU time 3.57 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:00:25 PM PST 24
Peak memory 201456 kb
Host smart-b73a723b-849c-4729-9ae7-1cfaecc1f1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367444194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.367444194
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1050507515
Short name T770
Test name
Test status
Simulation time 2455372580 ps
CPU time 6.92 seconds
Started Feb 21 03:00:24 PM PST 24
Finished Feb 21 03:00:31 PM PST 24
Peak memory 201460 kb
Host smart-2c130626-61e0-4dcb-860e-819d855c7374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050507515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1050507515
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1721931280
Short name T723
Test name
Test status
Simulation time 2241712995 ps
CPU time 6.11 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201460 kb
Host smart-e46d21e2-196f-4593-81b1-f52eb79da3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721931280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.1721931280
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.3557950745
Short name T395
Test name
Test status
Simulation time 2537858960 ps
CPU time 2.42 seconds
Started Feb 21 03:00:18 PM PST 24
Finished Feb 21 03:00:22 PM PST 24
Peak memory 201432 kb
Host smart-98346f43-95ec-4c94-a5f8-500c94e6860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557950745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.3557950745
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3102508521
Short name T673
Test name
Test status
Simulation time 2107086002 ps
CPU time 5.93 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:18 PM PST 24
Peak memory 201428 kb
Host smart-ce36bc0c-bb2a-4706-be20-6c85268c1778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102508521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3102508521
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.1238582598
Short name T684
Test name
Test status
Simulation time 13071196616 ps
CPU time 10.17 seconds
Started Feb 21 03:00:25 PM PST 24
Finished Feb 21 03:00:36 PM PST 24
Peak memory 201516 kb
Host smart-25b3efbf-dd7a-4638-b2a4-a24625a498b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238582598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.1238582598
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1872166535
Short name T274
Test name
Test status
Simulation time 52191459860 ps
CPU time 143.63 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 210092 kb
Host smart-e9d6d274-716e-44d3-8eae-0020ea64be3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872166535 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.1872166535
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1534838905
Short name T688
Test name
Test status
Simulation time 7743195544 ps
CPU time 6.52 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:30 PM PST 24
Peak memory 201424 kb
Host smart-2684f8f7-a9b1-490c-b533-ff899a782fec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534838905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.1534838905
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.3695951774
Short name T721
Test name
Test status
Simulation time 2016368580 ps
CPU time 5.85 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:28 PM PST 24
Peak memory 201460 kb
Host smart-9499a115-06ad-4694-a753-0c403e499a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695951774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.3695951774
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3040516260
Short name T490
Test name
Test status
Simulation time 3427860628 ps
CPU time 2.98 seconds
Started Feb 21 03:00:13 PM PST 24
Finished Feb 21 03:00:16 PM PST 24
Peak memory 201520 kb
Host smart-0c6bf15d-037e-45b7-8339-80926b1bee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040516260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.3
040516260
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.3604490614
Short name T241
Test name
Test status
Simulation time 35177209016 ps
CPU time 69.26 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:01:22 PM PST 24
Peak memory 200568 kb
Host smart-d4f6440e-b1a0-4017-938e-ac155006d470
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604490614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.3604490614
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2213543249
Short name T544
Test name
Test status
Simulation time 28581504881 ps
CPU time 55.09 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:01:07 PM PST 24
Peak memory 201644 kb
Host smart-b5e56018-6632-4457-94c3-3858c3d80b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213543249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2213543249
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.481988721
Short name T57
Test name
Test status
Simulation time 632847148937 ps
CPU time 1386.25 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:23:18 PM PST 24
Peak memory 201376 kb
Host smart-97cd6105-44f1-46fa-b771-77da283c9ff7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481988721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_ec_pwr_on_rst.481988721
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.3221391768
Short name T626
Test name
Test status
Simulation time 2961189287 ps
CPU time 1.95 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201404 kb
Host smart-b24a55e3-2ef4-45a6-b914-b7971b4d68e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221391768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.3221391768
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1946969509
Short name T419
Test name
Test status
Simulation time 2626840637 ps
CPU time 3.31 seconds
Started Feb 21 03:00:35 PM PST 24
Finished Feb 21 03:00:39 PM PST 24
Peak memory 201428 kb
Host smart-23a43ed7-19a0-41ea-bf3b-c34bb1ce83a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946969509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.1946969509
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.3418843486
Short name T677
Test name
Test status
Simulation time 2504377140 ps
CPU time 1.57 seconds
Started Feb 21 03:00:18 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201432 kb
Host smart-da247d2a-77ba-40b1-a3b1-6a8b4cd6544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418843486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3418843486
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2560551508
Short name T431
Test name
Test status
Simulation time 2234513884 ps
CPU time 1.97 seconds
Started Feb 21 03:00:27 PM PST 24
Finished Feb 21 03:00:30 PM PST 24
Peak memory 201448 kb
Host smart-bbefa6f6-bedc-4c9a-963a-eadc1e4d32aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560551508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.2560551508
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.3263259995
Short name T423
Test name
Test status
Simulation time 2519049887 ps
CPU time 4.04 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:00:15 PM PST 24
Peak memory 201412 kb
Host smart-ca22468a-e598-48d2-b909-7468464cb094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263259995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.3263259995
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.2168282727
Short name T646
Test name
Test status
Simulation time 2116223606 ps
CPU time 3.39 seconds
Started Feb 21 03:00:18 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201364 kb
Host smart-2f3f8957-c097-4c53-a144-cb04609f2178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168282727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2168282727
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.1306539291
Short name T351
Test name
Test status
Simulation time 209993785819 ps
CPU time 569.61 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:09:42 PM PST 24
Peak memory 200240 kb
Host smart-d06413bb-1ec2-497b-ac05-536cc1955ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306539291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.1306539291
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3497987062
Short name T633
Test name
Test status
Simulation time 11571401218 ps
CPU time 30.01 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:47 PM PST 24
Peak memory 201636 kb
Host smart-fb048ca6-fb18-471e-bbc3-87b02a38228a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497987062 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.3497987062
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2723597194
Short name T60
Test name
Test status
Simulation time 2811960199 ps
CPU time 6.13 seconds
Started Feb 21 03:00:14 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201412 kb
Host smart-0a9329ec-3690-4fa4-8b24-82cabf256a14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723597194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.2723597194
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1964852331
Short name T414
Test name
Test status
Simulation time 2025409202 ps
CPU time 2.7 seconds
Started Feb 21 03:00:06 PM PST 24
Finished Feb 21 03:00:09 PM PST 24
Peak memory 201444 kb
Host smart-e9173a3d-e2bb-4c33-8282-e059fd1f12eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964852331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1964852331
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.464723734
Short name T639
Test name
Test status
Simulation time 3840202922 ps
CPU time 10.36 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:30 PM PST 24
Peak memory 201476 kb
Host smart-14771bb4-d0c4-4f7e-a225-20a9172d6e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464723734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.464723734
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.2580945925
Short name T245
Test name
Test status
Simulation time 29662500292 ps
CPU time 87 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:01:45 PM PST 24
Peak memory 201556 kb
Host smart-d45542ca-b2c6-468f-b852-0aa47a673349
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580945925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.2580945925
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2365391491
Short name T599
Test name
Test status
Simulation time 33792922263 ps
CPU time 8.55 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:38 PM PST 24
Peak memory 201604 kb
Host smart-18fbc042-78a9-48c5-9b40-d7debbdee40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365391491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.2365391491
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.937469372
Short name T669
Test name
Test status
Simulation time 3839485897 ps
CPU time 1.08 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:00:20 PM PST 24
Peak memory 201376 kb
Host smart-93938743-c10d-4de2-b829-f1e13108d27d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937469372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ec_pwr_on_rst.937469372
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1925831793
Short name T134
Test name
Test status
Simulation time 5963474361 ps
CPU time 7.07 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201404 kb
Host smart-62e31bed-785f-42d4-aa26-439ff3c60b74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925831793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.1925831793
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.395807566
Short name T186
Test name
Test status
Simulation time 2622426850 ps
CPU time 3.49 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:00:25 PM PST 24
Peak memory 201472 kb
Host smart-a7cedff0-c820-4c0b-b6e2-1633a453f6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395807566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.395807566
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.597045547
Short name T661
Test name
Test status
Simulation time 2459997935 ps
CPU time 2.34 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:00:20 PM PST 24
Peak memory 201408 kb
Host smart-7caa6ba1-fae4-4582-a005-4f15971fd75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597045547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.597045547
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.1809524413
Short name T413
Test name
Test status
Simulation time 2093132336 ps
CPU time 5.52 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201364 kb
Host smart-1b59badf-d100-435a-9c14-ac41ab2cc602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809524413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1809524413
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2444013148
Short name T498
Test name
Test status
Simulation time 2516547212 ps
CPU time 4.16 seconds
Started Feb 21 03:00:13 PM PST 24
Finished Feb 21 03:00:17 PM PST 24
Peak memory 201376 kb
Host smart-7931dbdb-e6ab-437f-9821-f3190a61edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444013148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2444013148
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.428849744
Short name T390
Test name
Test status
Simulation time 2110725597 ps
CPU time 6.16 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:14 PM PST 24
Peak memory 200988 kb
Host smart-c6f5924f-28f4-4d84-9149-30997a7f4b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428849744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.428849744
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2777027427
Short name T87
Test name
Test status
Simulation time 43465385544 ps
CPU time 100.5 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:01:58 PM PST 24
Peak memory 210084 kb
Host smart-5d237a7b-5538-4ea7-ad9e-3c2ff69a204a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777027427 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.2777027427
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2879684882
Short name T665
Test name
Test status
Simulation time 3655114577 ps
CPU time 6.66 seconds
Started Feb 21 03:00:13 PM PST 24
Finished Feb 21 03:00:20 PM PST 24
Peak memory 201424 kb
Host smart-98455fa2-0a04-421d-a806-7dbd10f41acf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879684882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.2879684882
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3613448734
Short name T741
Test name
Test status
Simulation time 2092654155 ps
CPU time 1.11 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:18 PM PST 24
Peak memory 201428 kb
Host smart-9a003afb-157d-473f-8e92-32a0cb41965f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613448734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3613448734
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3492955036
Short name T299
Test name
Test status
Simulation time 231757144616 ps
CPU time 314.79 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:05:33 PM PST 24
Peak memory 201480 kb
Host smart-66a6e7e5-3599-440c-81b8-f2d93f5b192b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492955036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.3
492955036
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3240221265
Short name T729
Test name
Test status
Simulation time 79480131926 ps
CPU time 104.66 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:02:06 PM PST 24
Peak memory 201620 kb
Host smart-18cb784a-ee2a-45a7-ace3-8f21c3e8a01e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240221265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3240221265
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.88898931
Short name T681
Test name
Test status
Simulation time 72437953763 ps
CPU time 95.35 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:01:48 PM PST 24
Peak memory 200148 kb
Host smart-6e9600ce-d70e-420c-b73f-7ee8d2f814da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88898931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wit
h_pre_cond.88898931
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3912664230
Short name T298
Test name
Test status
Simulation time 4773777496 ps
CPU time 14.02 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:34 PM PST 24
Peak memory 201428 kb
Host smart-7a9fa72f-1d79-4928-92cc-6e25970af1e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912664230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.3912664230
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1964637887
Short name T674
Test name
Test status
Simulation time 2622754237 ps
CPU time 3.88 seconds
Started Feb 21 03:00:14 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201444 kb
Host smart-16a37edb-2495-45cf-9d67-133d00e6fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964637887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1964637887
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.2135874277
Short name T282
Test name
Test status
Simulation time 2469635079 ps
CPU time 4.16 seconds
Started Feb 21 03:00:09 PM PST 24
Finished Feb 21 03:00:14 PM PST 24
Peak memory 201440 kb
Host smart-c583e8dc-76b8-4c40-a499-61ab29d128bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135874277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.2135874277
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.589299610
Short name T634
Test name
Test status
Simulation time 2344841016 ps
CPU time 1.11 seconds
Started Feb 21 03:00:14 PM PST 24
Finished Feb 21 03:00:17 PM PST 24
Peak memory 201432 kb
Host smart-88f001a7-7435-48b5-9912-e7310a54fabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589299610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.589299610
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1655539287
Short name T363
Test name
Test status
Simulation time 2510267169 ps
CPU time 7.11 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:31 PM PST 24
Peak memory 201428 kb
Host smart-09c64e2d-eba5-44df-bc01-c001e6ab984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655539287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1655539287
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.3377272242
Short name T606
Test name
Test status
Simulation time 2125131940 ps
CPU time 2.32 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:00:03 PM PST 24
Peak memory 201316 kb
Host smart-45e0a928-49e1-4e3e-9859-4671b3462674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377272242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3377272242
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3428856599
Short name T319
Test name
Test status
Simulation time 144060163801 ps
CPU time 62.87 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:01:16 PM PST 24
Peak memory 209876 kb
Host smart-9ea23b3f-eeac-4002-bafa-8fc421796fa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428856599 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.3428856599
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3343965167
Short name T124
Test name
Test status
Simulation time 4377392442 ps
CPU time 7.29 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:16 PM PST 24
Peak memory 201412 kb
Host smart-3c5452ec-0bdb-4408-8816-218386447414
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343965167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.3343965167
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.2938613007
Short name T187
Test name
Test status
Simulation time 2063146966 ps
CPU time 1.15 seconds
Started Feb 21 03:00:06 PM PST 24
Finished Feb 21 03:00:08 PM PST 24
Peak memory 201380 kb
Host smart-df31f085-178b-426c-899f-c7aabc1fcb43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938613007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.2938613007
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.4156009789
Short name T433
Test name
Test status
Simulation time 3324096404 ps
CPU time 8.8 seconds
Started Feb 21 03:00:13 PM PST 24
Finished Feb 21 03:00:22 PM PST 24
Peak memory 201480 kb
Host smart-959f247f-c0e8-4324-8dec-0633b33f0919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156009789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.4
156009789
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.1634509185
Short name T632
Test name
Test status
Simulation time 49995327464 ps
CPU time 32.93 seconds
Started Feb 21 03:00:13 PM PST 24
Finished Feb 21 03:00:46 PM PST 24
Peak memory 201624 kb
Host smart-05dc9d51-b818-4266-aa16-da00ab018f05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634509185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.1634509185
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.986400644
Short name T230
Test name
Test status
Simulation time 58294341268 ps
CPU time 70.89 seconds
Started Feb 21 03:00:14 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201696 kb
Host smart-10d67cfa-a9c5-4a7f-a8a0-591a970b3f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986400644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_wi
th_pre_cond.986400644
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2330551629
Short name T647
Test name
Test status
Simulation time 3918182371 ps
CPU time 11 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:00:29 PM PST 24
Peak memory 201404 kb
Host smart-a1fe132f-07de-4081-8e01-78be7c696c3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330551629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.2330551629
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.1497400772
Short name T181
Test name
Test status
Simulation time 2921810683 ps
CPU time 7.73 seconds
Started Feb 21 03:00:13 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201372 kb
Host smart-5bde4120-283b-4e63-bc93-f2037979eba0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497400772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.1497400772
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1023780954
Short name T212
Test name
Test status
Simulation time 2633478414 ps
CPU time 2.32 seconds
Started Feb 21 03:00:20 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201472 kb
Host smart-6537c739-a0ec-4ce1-a80b-6082190bed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023780954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.1023780954
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3030433640
Short name T109
Test name
Test status
Simulation time 2514348751 ps
CPU time 1.65 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 201472 kb
Host smart-13451276-fec3-4e38-808d-ab4c6fbeb21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030433640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.3030433640
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.3301556073
Short name T768
Test name
Test status
Simulation time 2069986918 ps
CPU time 6.57 seconds
Started Feb 21 02:59:56 PM PST 24
Finished Feb 21 03:00:04 PM PST 24
Peak memory 201336 kb
Host smart-3ed469d8-08b9-4d0c-82f5-49c9b864a0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301556073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3301556073
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3394157218
Short name T610
Test name
Test status
Simulation time 2534441519 ps
CPU time 2.54 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:11 PM PST 24
Peak memory 201416 kb
Host smart-37c87d66-d676-4ca6-80f5-958f325d30a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394157218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3394157218
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.4215928877
Short name T369
Test name
Test status
Simulation time 2127858353 ps
CPU time 2.27 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201344 kb
Host smart-c52835db-3d3d-4e00-8261-7db322f94706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215928877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.4215928877
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.3796469564
Short name T348
Test name
Test status
Simulation time 178578571150 ps
CPU time 213.65 seconds
Started Feb 21 03:00:14 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 201644 kb
Host smart-9b384e9c-516e-48c9-a6fd-b1ad1eb51b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796469564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.3796469564
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2891495458
Short name T360
Test name
Test status
Simulation time 33503128429 ps
CPU time 6.83 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:00:38 PM PST 24
Peak memory 201376 kb
Host smart-0c9b565d-5241-41d1-ba35-8dbac4e3f7f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891495458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.2891495458
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.2904931507
Short name T379
Test name
Test status
Simulation time 2008416672 ps
CPU time 5.64 seconds
Started Feb 21 02:59:48 PM PST 24
Finished Feb 21 02:59:55 PM PST 24
Peak memory 201464 kb
Host smart-bd5b8398-011e-419e-8a61-758aade74164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904931507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.2904931507
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2957321392
Short name T86
Test name
Test status
Simulation time 3787489393 ps
CPU time 10.89 seconds
Started Feb 21 02:59:51 PM PST 24
Finished Feb 21 03:00:02 PM PST 24
Peak memory 201516 kb
Host smart-7880825e-088e-4174-b2a8-4e32893f7091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957321392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.2957321392
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.1944485984
Short name T98
Test name
Test status
Simulation time 102859970769 ps
CPU time 132.91 seconds
Started Feb 21 03:00:06 PM PST 24
Finished Feb 21 03:02:19 PM PST 24
Peak memory 201600 kb
Host smart-1196231c-2165-4ae9-864a-1f781be3133e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944485984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.1944485984
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3773754682
Short name T527
Test name
Test status
Simulation time 2221805091 ps
CPU time 2.31 seconds
Started Feb 21 02:59:40 PM PST 24
Finished Feb 21 02:59:43 PM PST 24
Peak memory 201428 kb
Host smart-34729527-59a6-4671-a077-07c9942c8bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773754682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3773754682
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3119020406
Short name T459
Test name
Test status
Simulation time 2359702913 ps
CPU time 3.51 seconds
Started Feb 21 02:59:57 PM PST 24
Finished Feb 21 03:00:02 PM PST 24
Peak memory 201420 kb
Host smart-d1847f67-18d6-44e1-baf3-4553d89511c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119020406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3119020406
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2681693271
Short name T651
Test name
Test status
Simulation time 3361763431 ps
CPU time 2.6 seconds
Started Feb 21 02:59:44 PM PST 24
Finished Feb 21 02:59:47 PM PST 24
Peak memory 201428 kb
Host smart-2dc8049c-fc0b-4702-a9ac-a6b488995277
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681693271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.2681693271
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.4162665745
Short name T83
Test name
Test status
Simulation time 2727665081 ps
CPU time 3.47 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:00:22 PM PST 24
Peak memory 201412 kb
Host smart-c3eec4c3-8591-4e05-9453-7f019c461b2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162665745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.4162665745
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3398778690
Short name T537
Test name
Test status
Simulation time 2612750406 ps
CPU time 8.01 seconds
Started Feb 21 02:59:55 PM PST 24
Finished Feb 21 03:00:05 PM PST 24
Peak memory 201476 kb
Host smart-b4219ada-d529-4abe-8f4b-0bb16dd003eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398778690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3398778690
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.3652799817
Short name T412
Test name
Test status
Simulation time 2453862704 ps
CPU time 8.13 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:00:08 PM PST 24
Peak memory 201428 kb
Host smart-95d1a255-8e19-44dd-873f-ac10db7a31e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652799817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.3652799817
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2364744901
Short name T567
Test name
Test status
Simulation time 2095996945 ps
CPU time 3.36 seconds
Started Feb 21 03:00:07 PM PST 24
Finished Feb 21 03:00:11 PM PST 24
Peak memory 201348 kb
Host smart-836723cd-8f18-4c14-b160-44ae96c92b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364744901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2364744901
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.2386523128
Short name T752
Test name
Test status
Simulation time 2535349126 ps
CPU time 2.45 seconds
Started Feb 21 02:59:54 PM PST 24
Finished Feb 21 02:59:57 PM PST 24
Peak memory 201440 kb
Host smart-ff166eb7-69ee-4713-be89-f4aac4d0af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386523128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.2386523128
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1805998510
Short name T265
Test name
Test status
Simulation time 42031374627 ps
CPU time 54.53 seconds
Started Feb 21 02:59:52 PM PST 24
Finished Feb 21 03:00:46 PM PST 24
Peak memory 221900 kb
Host smart-bb7b1ddf-953f-406a-896f-caa48bec199a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805998510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1805998510
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.3420359271
Short name T471
Test name
Test status
Simulation time 2116559361 ps
CPU time 3.18 seconds
Started Feb 21 02:59:44 PM PST 24
Finished Feb 21 02:59:47 PM PST 24
Peak memory 201324 kb
Host smart-206e3ca5-da21-4ec9-8a8a-5f3b9ad98e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420359271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.3420359271
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.1694911894
Short name T19
Test name
Test status
Simulation time 14183849190 ps
CPU time 8.76 seconds
Started Feb 21 03:00:06 PM PST 24
Finished Feb 21 03:00:15 PM PST 24
Peak memory 201444 kb
Host smart-f5cec0ad-2034-420d-a2a5-10974a916e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694911894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.1694911894
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.4241103969
Short name T717
Test name
Test status
Simulation time 134705204376 ps
CPU time 19 seconds
Started Feb 21 02:59:55 PM PST 24
Finished Feb 21 03:00:16 PM PST 24
Peak memory 201852 kb
Host smart-4af57b38-3fcc-4f7f-b01b-98b3f5303d48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241103969 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.4241103969
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3153445674
Short name T118
Test name
Test status
Simulation time 8809695569 ps
CPU time 2.91 seconds
Started Feb 21 02:59:44 PM PST 24
Finished Feb 21 02:59:47 PM PST 24
Peak memory 201376 kb
Host smart-45edcc9b-2f9e-4933-89d1-232391ad54a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153445674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.3153445674
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.2993402376
Short name T411
Test name
Test status
Simulation time 2028430420 ps
CPU time 2.87 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201444 kb
Host smart-22e0336a-dad7-44d9-b8d6-772b54d9b9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993402376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.2993402376
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3621966779
Short name T529
Test name
Test status
Simulation time 3382234008 ps
CPU time 4.82 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 201500 kb
Host smart-3421030c-c08c-4bfb-8179-f27f9b7df011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621966779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3
621966779
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.818475030
Short name T92
Test name
Test status
Simulation time 130959415793 ps
CPU time 100.12 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:02:01 PM PST 24
Peak memory 201688 kb
Host smart-a0796592-1cb2-47b7-977e-27b757bca663
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818475030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_combo_detect.818475030
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1153498367
Short name T102
Test name
Test status
Simulation time 3606513168 ps
CPU time 9.59 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201412 kb
Host smart-38546a2b-34be-4cf1-86bf-c12494cf4d9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153498367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.1153498367
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.943365860
Short name T148
Test name
Test status
Simulation time 4816384305 ps
CPU time 1.35 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:00:12 PM PST 24
Peak memory 201408 kb
Host smart-6f7d83e4-d2c6-493d-ab27-6b743d864e22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943365860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctr
l_edge_detect.943365860
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3297903795
Short name T551
Test name
Test status
Simulation time 2635625036 ps
CPU time 2.39 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:20 PM PST 24
Peak memory 201436 kb
Host smart-e3ef4b0c-3a1c-4ebf-ad36-51b712396728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297903795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.3297903795
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1800429780
Short name T625
Test name
Test status
Simulation time 2493775661 ps
CPU time 1.43 seconds
Started Feb 21 03:00:18 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201428 kb
Host smart-694bb083-3340-41c8-aa3f-7d7606950ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800429780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1800429780
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1260063457
Short name T495
Test name
Test status
Simulation time 2176679465 ps
CPU time 6.66 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 201448 kb
Host smart-47bc0d94-8973-4eee-bdc9-3977334b1504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260063457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1260063457
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2308812386
Short name T515
Test name
Test status
Simulation time 2532748635 ps
CPU time 2.09 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:14 PM PST 24
Peak memory 201452 kb
Host smart-735a46ef-35d4-431d-9539-6587829408d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308812386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.2308812386
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.4082725194
Short name T268
Test name
Test status
Simulation time 2136191560 ps
CPU time 2.01 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:32 PM PST 24
Peak memory 201380 kb
Host smart-ca8a9dfc-f24a-4167-87ef-6002f6d6b874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082725194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.4082725194
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.600418458
Short name T540
Test name
Test status
Simulation time 7898258333 ps
CPU time 6.13 seconds
Started Feb 21 03:00:14 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201492 kb
Host smart-f35659b4-7cad-4a16-add4-d54b481f32be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600418458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_st
ress_all.600418458
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.31588826
Short name T121
Test name
Test status
Simulation time 32214512213 ps
CPU time 75.52 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:01:47 PM PST 24
Peak memory 209948 kb
Host smart-f1d0620b-fe44-40b3-8f72-a00234009ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588826 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.31588826
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1046600701
Short name T127
Test name
Test status
Simulation time 499969149677 ps
CPU time 15.19 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 200996 kb
Host smart-efdd980a-520d-40e5-be63-4a6962eabcb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046600701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.1046600701
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.1075619940
Short name T557
Test name
Test status
Simulation time 2093573876 ps
CPU time 1.23 seconds
Started Feb 21 03:00:25 PM PST 24
Finished Feb 21 03:00:27 PM PST 24
Peak memory 201448 kb
Host smart-4751a275-6d8e-4d0f-afbb-ccd2614647d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075619940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.1075619940
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1772371972
Short name T488
Test name
Test status
Simulation time 33739853891 ps
CPU time 93.05 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:02:04 PM PST 24
Peak memory 201508 kb
Host smart-6a301837-d719-414f-93be-41442b2e88cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772371972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1
772371972
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3915871103
Short name T645
Test name
Test status
Simulation time 56416400178 ps
CPU time 155.02 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:03:05 PM PST 24
Peak memory 201668 kb
Host smart-c82af1c9-0b9a-4b2f-8470-f528b3b4ceb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915871103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3915871103
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3075563069
Short name T776
Test name
Test status
Simulation time 87388691972 ps
CPU time 239.82 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:04:29 PM PST 24
Peak memory 201536 kb
Host smart-8c22094a-abf2-45fa-b777-242982c02441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075563069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.3075563069
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1324500341
Short name T499
Test name
Test status
Simulation time 3444158241 ps
CPU time 4.81 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:00:16 PM PST 24
Peak memory 201408 kb
Host smart-8342a3c2-3a6d-492a-96ad-b393cade3079
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324500341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.1324500341
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.3612471318
Short name T179
Test name
Test status
Simulation time 3135064842 ps
CPU time 4.77 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:27 PM PST 24
Peak memory 201460 kb
Host smart-eb263c59-84e0-4483-bb6b-35bd5eac1196
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612471318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.3612471318
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.720078282
Short name T444
Test name
Test status
Simulation time 2691007529 ps
CPU time 1.35 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 201436 kb
Host smart-71021881-92a4-4673-ab73-3bf9522e526e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720078282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.720078282
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3937709880
Short name T601
Test name
Test status
Simulation time 2474087701 ps
CPU time 4.3 seconds
Started Feb 21 03:00:25 PM PST 24
Finished Feb 21 03:00:29 PM PST 24
Peak memory 201408 kb
Host smart-e78d115e-ad9c-4378-94dc-e7908a0411ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937709880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.3937709880
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.169659975
Short name T578
Test name
Test status
Simulation time 2178044406 ps
CPU time 3.57 seconds
Started Feb 21 03:00:36 PM PST 24
Finished Feb 21 03:00:40 PM PST 24
Peak memory 201428 kb
Host smart-18fe4151-0c6f-471e-bd6b-1241bfc35f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169659975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.169659975
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.1456041567
Short name T450
Test name
Test status
Simulation time 2552666474 ps
CPU time 1.54 seconds
Started Feb 21 03:00:26 PM PST 24
Finished Feb 21 03:00:28 PM PST 24
Peak memory 201412 kb
Host smart-ea34f0b2-fcdf-4042-ad0e-ad1b09fb0219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456041567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.1456041567
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.620473189
Short name T171
Test name
Test status
Simulation time 2112927750 ps
CPU time 5.89 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:28 PM PST 24
Peak memory 201384 kb
Host smart-e2cb0b6d-ce53-4414-915c-876db1d5cc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620473189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.620473189
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3465091594
Short name T146
Test name
Test status
Simulation time 115834443746 ps
CPU time 73.74 seconds
Started Feb 21 03:00:27 PM PST 24
Finished Feb 21 03:01:41 PM PST 24
Peak memory 210040 kb
Host smart-fe9418e4-5565-4cd5-be4f-69db5c20e2a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465091594 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3465091594
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2455577182
Short name T662
Test name
Test status
Simulation time 1734450615868 ps
CPU time 184.52 seconds
Started Feb 21 03:00:20 PM PST 24
Finished Feb 21 03:03:25 PM PST 24
Peak memory 201436 kb
Host smart-302c96fd-d167-430d-9413-7a5f64fb1784
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455577182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.2455577182
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.1950235936
Short name T368
Test name
Test status
Simulation time 2048867549 ps
CPU time 1.46 seconds
Started Feb 21 03:00:18 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201420 kb
Host smart-d25e19b8-020c-436c-b991-152a46070ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950235936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.1950235936
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1505094246
Short name T440
Test name
Test status
Simulation time 372006452880 ps
CPU time 966.53 seconds
Started Feb 21 03:00:27 PM PST 24
Finished Feb 21 03:16:35 PM PST 24
Peak memory 201504 kb
Host smart-9f382290-5076-4027-8d72-141003d47619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505094246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.1
505094246
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3667847913
Short name T95
Test name
Test status
Simulation time 32401445408 ps
CPU time 44.17 seconds
Started Feb 21 03:00:26 PM PST 24
Finished Feb 21 03:01:10 PM PST 24
Peak memory 201560 kb
Host smart-72086cef-c440-4bff-b79e-c9a560b080e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667847913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.3667847913
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3181393542
Short name T380
Test name
Test status
Simulation time 4489905359 ps
CPU time 3.39 seconds
Started Feb 21 03:00:30 PM PST 24
Finished Feb 21 03:00:35 PM PST 24
Peak memory 201432 kb
Host smart-059fa8ac-01ae-4ed4-9408-caeaee6e517b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181393542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.3181393542
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.242916712
Short name T774
Test name
Test status
Simulation time 2608973426 ps
CPU time 7.42 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:00:29 PM PST 24
Peak memory 201432 kb
Host smart-30d2853c-f084-4fa2-80f1-59ad4d533b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242916712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.242916712
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2032426693
Short name T702
Test name
Test status
Simulation time 2472141329 ps
CPU time 4.29 seconds
Started Feb 21 03:00:21 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201476 kb
Host smart-900fade5-fddf-4567-83da-d83c8f7e7140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032426693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2032426693
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1225759347
Short name T588
Test name
Test status
Simulation time 2069852795 ps
CPU time 5.55 seconds
Started Feb 21 03:00:25 PM PST 24
Finished Feb 21 03:00:31 PM PST 24
Peak memory 201372 kb
Host smart-0e1faa48-4701-49db-97a6-3121b8a90a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225759347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1225759347
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2722875982
Short name T111
Test name
Test status
Simulation time 2509754877 ps
CPU time 6.54 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201420 kb
Host smart-7f0929ac-c0ac-4a9b-90f8-f6df13ff0a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722875982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2722875982
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.1826396015
Short name T575
Test name
Test status
Simulation time 2145748789 ps
CPU time 1.48 seconds
Started Feb 21 03:00:36 PM PST 24
Finished Feb 21 03:00:38 PM PST 24
Peak memory 201368 kb
Host smart-ea18f051-b874-419e-9cdb-f06978fef946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826396015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1826396015
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.2136337913
Short name T654
Test name
Test status
Simulation time 6318423828 ps
CPU time 17.05 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:39 PM PST 24
Peak memory 201428 kb
Host smart-9bd14469-4613-4ba2-b5d1-966e909db28c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136337913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.2136337913
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.175556749
Short name T728
Test name
Test status
Simulation time 38051661360 ps
CPU time 46.2 seconds
Started Feb 21 03:00:39 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 209980 kb
Host smart-9c15d401-2299-4738-8261-8cecad09baa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175556749 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.175556749
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3986447542
Short name T361
Test name
Test status
Simulation time 1191476690599 ps
CPU time 73.15 seconds
Started Feb 21 03:00:36 PM PST 24
Finished Feb 21 03:01:50 PM PST 24
Peak memory 201424 kb
Host smart-3b88161e-bff0-4778-a6bd-34160e537d20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986447542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3986447542
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.1599171476
Short name T583
Test name
Test status
Simulation time 2011260538 ps
CPU time 6.27 seconds
Started Feb 21 03:00:27 PM PST 24
Finished Feb 21 03:00:33 PM PST 24
Peak memory 201432 kb
Host smart-56f0ce74-b65d-49be-9620-5544d5be8dee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599171476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.1599171476
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2660461126
Short name T782
Test name
Test status
Simulation time 3249907952 ps
CPU time 2.77 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:25 PM PST 24
Peak memory 201536 kb
Host smart-b1d3232f-15ba-4d27-a127-54c40d16f8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660461126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2
660461126
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.776353655
Short name T150
Test name
Test status
Simulation time 3293454283 ps
CPU time 3.61 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201448 kb
Host smart-1e065371-dc4f-4ef1-8a20-76fc3cf32dd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776353655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctr
l_edge_detect.776353655
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2494110137
Short name T210
Test name
Test status
Simulation time 2614167192 ps
CPU time 7.65 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:28 PM PST 24
Peak memory 201468 kb
Host smart-617b2b53-6cc2-4a41-af11-ac2d7972cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494110137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.2494110137
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3260378098
Short name T630
Test name
Test status
Simulation time 2463868593 ps
CPU time 4.14 seconds
Started Feb 21 03:00:20 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 201428 kb
Host smart-40fffcae-ce67-4e33-a2e7-2e6575edcb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260378098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.3260378098
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.2504310979
Short name T392
Test name
Test status
Simulation time 2054630419 ps
CPU time 3.38 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201396 kb
Host smart-2884182a-c5f6-46e3-a57f-baca70eb074e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504310979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.2504310979
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.3153647737
Short name T460
Test name
Test status
Simulation time 2520403167 ps
CPU time 3.77 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:24 PM PST 24
Peak memory 201440 kb
Host smart-22eaf9ee-af07-4f23-8348-0237fd44a2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153647737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.3153647737
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.1159293917
Short name T502
Test name
Test status
Simulation time 2137998527 ps
CPU time 1.9 seconds
Started Feb 21 03:00:35 PM PST 24
Finished Feb 21 03:00:38 PM PST 24
Peak memory 201276 kb
Host smart-85775ace-745c-4c04-9431-346542e94fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159293917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.1159293917
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.1880131810
Short name T391
Test name
Test status
Simulation time 14113257233 ps
CPU time 36.37 seconds
Started Feb 21 03:00:43 PM PST 24
Finished Feb 21 03:01:20 PM PST 24
Peak memory 201436 kb
Host smart-9dadf7b5-0425-4618-8bfe-ec033800eb0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880131810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.1880131810
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1642430724
Short name T192
Test name
Test status
Simulation time 114647109578 ps
CPU time 164.94 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:03:08 PM PST 24
Peak memory 210020 kb
Host smart-26d325be-57ad-43cc-9e1a-6bfc8119fcbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642430724 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.1642430724
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1651525106
Short name T56
Test name
Test status
Simulation time 10047845945 ps
CPU time 6.72 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:27 PM PST 24
Peak memory 201436 kb
Host smart-5976a386-e3c0-49cc-a10e-fc2901851c42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651525106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.1651525106
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.318023318
Short name T140
Test name
Test status
Simulation time 2014699657 ps
CPU time 6.14 seconds
Started Feb 21 03:00:36 PM PST 24
Finished Feb 21 03:00:43 PM PST 24
Peak memory 201376 kb
Host smart-25724755-0ba3-4f4d-b530-65f87881c31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318023318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_tes
t.318023318
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2101029718
Short name T48
Test name
Test status
Simulation time 3463743513 ps
CPU time 3.06 seconds
Started Feb 21 03:00:36 PM PST 24
Finished Feb 21 03:00:40 PM PST 24
Peak memory 201504 kb
Host smart-8d4cde46-acee-452c-a6cd-ae39545a9911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101029718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2
101029718
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2542662697
Short name T317
Test name
Test status
Simulation time 168183720675 ps
CPU time 81.26 seconds
Started Feb 21 03:00:25 PM PST 24
Finished Feb 21 03:01:46 PM PST 24
Peak memory 201652 kb
Host smart-948d4116-c804-4c04-aa8d-258b7f473a4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542662697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2542662697
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.765846678
Short name T447
Test name
Test status
Simulation time 104960100364 ps
CPU time 289.94 seconds
Started Feb 21 03:00:26 PM PST 24
Finished Feb 21 03:05:16 PM PST 24
Peak memory 201632 kb
Host smart-47c0f441-b383-43bb-aef9-1e57e484f429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765846678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_wi
th_pre_cond.765846678
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3784306636
Short name T508
Test name
Test status
Simulation time 4128623118 ps
CPU time 10.51 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:30 PM PST 24
Peak memory 201424 kb
Host smart-d3ac6924-f11b-459a-a179-13b0ecb58e0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784306636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.3784306636
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.509357356
Short name T773
Test name
Test status
Simulation time 3908735401 ps
CPU time 5.42 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:29 PM PST 24
Peak memory 201428 kb
Host smart-ffebfe3f-c3ce-43a6-8f9a-6290e489ef4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509357356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctr
l_edge_detect.509357356
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3387952131
Short name T589
Test name
Test status
Simulation time 2636888249 ps
CPU time 2.13 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:25 PM PST 24
Peak memory 201456 kb
Host smart-20827c09-2f9c-4749-8120-88718fa91aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387952131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.3387952131
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3510214898
Short name T409
Test name
Test status
Simulation time 2493626704 ps
CPU time 1.92 seconds
Started Feb 21 03:00:36 PM PST 24
Finished Feb 21 03:00:39 PM PST 24
Peak memory 201428 kb
Host smart-d4b6c64a-fad5-4175-8709-a9dd5c7b2461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510214898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3510214898
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3874084374
Short name T236
Test name
Test status
Simulation time 2153964366 ps
CPU time 6.45 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:29 PM PST 24
Peak memory 201452 kb
Host smart-5194b9b5-cd20-4a6e-b1b7-c557006e0860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874084374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3874084374
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2051327572
Short name T656
Test name
Test status
Simulation time 2516630704 ps
CPU time 3.94 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:28 PM PST 24
Peak memory 201416 kb
Host smart-6f3735cb-053e-4689-b615-1535a1076ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051327572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2051327572
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.1209303157
Short name T562
Test name
Test status
Simulation time 2114824139 ps
CPU time 5.52 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:28 PM PST 24
Peak memory 201364 kb
Host smart-a552e079-c6ba-4aa1-9415-9d601468e071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209303157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1209303157
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1584667773
Short name T116
Test name
Test status
Simulation time 45914337210 ps
CPU time 114 seconds
Started Feb 21 03:00:24 PM PST 24
Finished Feb 21 03:02:18 PM PST 24
Peak memory 217964 kb
Host smart-a7432c4c-3c65-4ea3-9667-00df9a47f1ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584667773 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1584667773
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1854300324
Short name T7
Test name
Test status
Simulation time 2626128087 ps
CPU time 5.32 seconds
Started Feb 21 03:00:26 PM PST 24
Finished Feb 21 03:00:31 PM PST 24
Peak memory 201440 kb
Host smart-15b641ff-c98f-4961-8d66-4fecdfe88569
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854300324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1854300324
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.940563213
Short name T643
Test name
Test status
Simulation time 2021931785 ps
CPU time 3.37 seconds
Started Feb 21 03:00:26 PM PST 24
Finished Feb 21 03:00:30 PM PST 24
Peak memory 201424 kb
Host smart-952cb1e9-53c7-4f3e-97b9-a7b36f1ffd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940563213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_tes
t.940563213
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3929018746
Short name T611
Test name
Test status
Simulation time 3461287180 ps
CPU time 3.09 seconds
Started Feb 21 03:00:30 PM PST 24
Finished Feb 21 03:00:35 PM PST 24
Peak memory 201488 kb
Host smart-65737375-3ee7-4453-bb05-d9799b7d98df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929018746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.3
929018746
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1926028274
Short name T240
Test name
Test status
Simulation time 118039718708 ps
CPU time 79.45 seconds
Started Feb 21 03:00:43 PM PST 24
Finished Feb 21 03:02:03 PM PST 24
Peak memory 201680 kb
Host smart-af953040-fdde-486c-9c0c-ddf1f512f956
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926028274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.1926028274
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1118753276
Short name T321
Test name
Test status
Simulation time 38611102085 ps
CPU time 7.67 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:00:39 PM PST 24
Peak memory 201640 kb
Host smart-c5470192-7b07-480e-b1dc-a9b53138856c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118753276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.1118753276
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2932769887
Short name T408
Test name
Test status
Simulation time 5663937606 ps
CPU time 15.01 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:44 PM PST 24
Peak memory 201252 kb
Host smart-e46b6eaf-7ca2-433a-884c-15512096fa50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932769887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.2932769887
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.569640266
Short name T161
Test name
Test status
Simulation time 4405082882 ps
CPU time 2.35 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:00:34 PM PST 24
Peak memory 201420 kb
Host smart-9aefc4fa-b130-48e7-9d71-260adf5047b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569640266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctr
l_edge_detect.569640266
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3097683631
Short name T767
Test name
Test status
Simulation time 2614442334 ps
CPU time 7.22 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:37 PM PST 24
Peak memory 201476 kb
Host smart-f101aa2e-0504-47d4-9b21-729a37568bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097683631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3097683631
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3632853894
Short name T671
Test name
Test status
Simulation time 2473633391 ps
CPU time 6.97 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:36 PM PST 24
Peak memory 201448 kb
Host smart-191f86ba-f534-4547-b6bb-c6959fc875a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632853894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.3632853894
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2563944204
Short name T516
Test name
Test status
Simulation time 2221458342 ps
CPU time 6.6 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:36 PM PST 24
Peak memory 201472 kb
Host smart-582def7b-c10c-4b0d-a43b-35c9b778dbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563944204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.2563944204
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1609574641
Short name T476
Test name
Test status
Simulation time 2508598836 ps
CPU time 6.42 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:29 PM PST 24
Peak memory 201428 kb
Host smart-e78043ff-5e9c-4f4e-b540-8ca85fa1e4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609574641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.1609574641
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.2540086446
Short name T623
Test name
Test status
Simulation time 2120538623 ps
CPU time 3.34 seconds
Started Feb 21 03:00:39 PM PST 24
Finished Feb 21 03:00:43 PM PST 24
Peak memory 201372 kb
Host smart-8edac7bd-b0b5-4a3f-a745-fc6437930221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540086446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2540086446
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.1163768313
Short name T600
Test name
Test status
Simulation time 7697234220 ps
CPU time 5.85 seconds
Started Feb 21 03:00:30 PM PST 24
Finished Feb 21 03:00:37 PM PST 24
Peak memory 201720 kb
Host smart-139d1b74-048b-4941-b7d0-3627290bf45f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163768313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.1163768313
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.603092477
Short name T289
Test name
Test status
Simulation time 204600960242 ps
CPU time 127.9 seconds
Started Feb 21 03:00:30 PM PST 24
Finished Feb 21 03:02:39 PM PST 24
Peak memory 218264 kb
Host smart-b3fbd3b5-39a2-4e58-ab27-e20413a6a1f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603092477 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.603092477
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.1425525431
Short name T739
Test name
Test status
Simulation time 2028729443 ps
CPU time 1.98 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:00:32 PM PST 24
Peak memory 201448 kb
Host smart-96e8f042-f4b0-4e00-9495-468e2c18c99c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425525431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.1425525431
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3164724802
Short name T561
Test name
Test status
Simulation time 3130034524 ps
CPU time 2.47 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:31 PM PST 24
Peak memory 201532 kb
Host smart-a70b6b5d-330f-41ad-bbe9-2565433d5daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164724802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.3
164724802
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.488260613
Short name T328
Test name
Test status
Simulation time 108178352391 ps
CPU time 113.9 seconds
Started Feb 21 03:00:43 PM PST 24
Finished Feb 21 03:02:37 PM PST 24
Peak memory 201636 kb
Host smart-50bae511-9a9a-426c-8da3-88e87728621d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488260613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_combo_detect.488260613
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1868490649
Short name T156
Test name
Test status
Simulation time 57859926541 ps
CPU time 135.38 seconds
Started Feb 21 03:00:35 PM PST 24
Finished Feb 21 03:02:52 PM PST 24
Peak memory 201620 kb
Host smart-2c8e22d5-7251-444b-ba1d-2f478bedf842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868490649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.1868490649
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2091086033
Short name T528
Test name
Test status
Simulation time 356885403241 ps
CPU time 880.9 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:15:10 PM PST 24
Peak memory 201424 kb
Host smart-6fc68cfc-8c20-4011-ba53-70b809d6c324
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091086033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.2091086033
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.3199241404
Short name T747
Test name
Test status
Simulation time 5820628011 ps
CPU time 9.59 seconds
Started Feb 21 03:00:33 PM PST 24
Finished Feb 21 03:00:43 PM PST 24
Peak memory 201428 kb
Host smart-6965d20b-e32a-4f17-978e-a437ee9bd522
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199241404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.3199241404
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1236186199
Short name T755
Test name
Test status
Simulation time 2734349740 ps
CPU time 1.21 seconds
Started Feb 21 03:00:26 PM PST 24
Finished Feb 21 03:00:27 PM PST 24
Peak memory 201392 kb
Host smart-1708550d-b18e-4b32-b70d-3b61649c4ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236186199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1236186199
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.4067618300
Short name T283
Test name
Test status
Simulation time 2461571826 ps
CPU time 7.66 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:31 PM PST 24
Peak memory 201420 kb
Host smart-7262d67d-55fc-4ca7-b178-e677a78dedd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067618300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.4067618300
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.1722595706
Short name T620
Test name
Test status
Simulation time 2226729215 ps
CPU time 1.98 seconds
Started Feb 21 03:00:42 PM PST 24
Finished Feb 21 03:00:44 PM PST 24
Peak memory 201460 kb
Host smart-f7353c4b-1277-4f82-bef8-9e1a362eecee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722595706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.1722595706
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3973587710
Short name T581
Test name
Test status
Simulation time 2513059865 ps
CPU time 7.13 seconds
Started Feb 21 03:00:48 PM PST 24
Finished Feb 21 03:00:56 PM PST 24
Peak memory 201448 kb
Host smart-7e1605d5-e6ff-4735-9f6f-e54a8d78abd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973587710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3973587710
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.664623218
Short name T112
Test name
Test status
Simulation time 2124940779 ps
CPU time 2.73 seconds
Started Feb 21 03:00:35 PM PST 24
Finished Feb 21 03:00:39 PM PST 24
Peak memory 201348 kb
Host smart-9adbf219-f9d5-4898-9e33-34f461d16767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664623218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.664623218
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.2697373129
Short name T622
Test name
Test status
Simulation time 6518913139 ps
CPU time 4.82 seconds
Started Feb 21 03:00:35 PM PST 24
Finished Feb 21 03:00:41 PM PST 24
Peak memory 201376 kb
Host smart-2ae8ca63-6ac2-4f76-80fd-2697a391a2f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697373129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.2697373129
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2222823376
Short name T31
Test name
Test status
Simulation time 3045986218 ps
CPU time 5.77 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:00:37 PM PST 24
Peak memory 201432 kb
Host smart-33f1fb41-1260-4107-876a-0470eb0cd0a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222823376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.2222823376
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.954602061
Short name T466
Test name
Test status
Simulation time 2009383816 ps
CPU time 6.05 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:00:36 PM PST 24
Peak memory 201388 kb
Host smart-9586cb2f-f1cf-43fd-b65d-fa14877cfd87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954602061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_tes
t.954602061
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2721258815
Short name T103
Test name
Test status
Simulation time 3760315847 ps
CPU time 2.52 seconds
Started Feb 21 03:01:01 PM PST 24
Finished Feb 21 03:01:04 PM PST 24
Peak memory 201484 kb
Host smart-1236740e-d1d8-4ba9-83bc-2c2774e49245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721258815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
721258815
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1255065177
Short name T200
Test name
Test status
Simulation time 113668114104 ps
CPU time 304.33 seconds
Started Feb 21 03:00:40 PM PST 24
Finished Feb 21 03:05:44 PM PST 24
Peak memory 201628 kb
Host smart-30c8834d-7dff-4922-a4ad-c529619426fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255065177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.1255065177
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2426474102
Short name T535
Test name
Test status
Simulation time 3325821562 ps
CPU time 1.5 seconds
Started Feb 21 03:00:35 PM PST 24
Finished Feb 21 03:00:38 PM PST 24
Peak memory 201344 kb
Host smart-79e0c712-44c8-45d7-ac86-44668f79989f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426474102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.2426474102
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.1069464039
Short name T463
Test name
Test status
Simulation time 2534872437 ps
CPU time 1.16 seconds
Started Feb 21 03:00:41 PM PST 24
Finished Feb 21 03:00:42 PM PST 24
Peak memory 201424 kb
Host smart-e364355d-e38c-4f36-9ea8-391c3678b893
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069464039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.1069464039
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2841611833
Short name T690
Test name
Test status
Simulation time 2616508427 ps
CPU time 3.88 seconds
Started Feb 21 03:00:36 PM PST 24
Finished Feb 21 03:00:40 PM PST 24
Peak memory 201428 kb
Host smart-82332caf-0591-487f-8b45-609295db802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841611833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.2841611833
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.551433452
Short name T547
Test name
Test status
Simulation time 2456189564 ps
CPU time 7.56 seconds
Started Feb 21 03:00:36 PM PST 24
Finished Feb 21 03:00:44 PM PST 24
Peak memory 201360 kb
Host smart-fc787384-13e6-41a6-936f-a0e1e6242551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551433452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.551433452
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.2947426555
Short name T381
Test name
Test status
Simulation time 2277931278 ps
CPU time 2.03 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201460 kb
Host smart-2ae6bf87-f33e-47ce-b7f7-24ba18bf0499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947426555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.2947426555
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1255036930
Short name T53
Test name
Test status
Simulation time 2509912537 ps
CPU time 7.95 seconds
Started Feb 21 03:00:22 PM PST 24
Finished Feb 21 03:00:30 PM PST 24
Peak memory 201432 kb
Host smart-6ad63be8-a33d-46a5-b87b-c079dc8b3e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255036930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.1255036930
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.4198016254
Short name T197
Test name
Test status
Simulation time 2116919009 ps
CPU time 3.4 seconds
Started Feb 21 03:00:35 PM PST 24
Finished Feb 21 03:00:39 PM PST 24
Peak memory 201332 kb
Host smart-9183f15a-e971-4c3a-afbc-9a19738fc13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198016254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.4198016254
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.4003447779
Short name T279
Test name
Test status
Simulation time 46010369000 ps
CPU time 104.75 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 210276 kb
Host smart-a997a879-16ba-4a17-be4b-e7caf2335bec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003447779 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.4003447779
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2506535178
Short name T461
Test name
Test status
Simulation time 4472051961 ps
CPU time 1.71 seconds
Started Feb 21 03:00:51 PM PST 24
Finished Feb 21 03:00:54 PM PST 24
Peak memory 201432 kb
Host smart-7534ad71-6b53-42c9-a7d0-7bfbe0b95e19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506535178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.2506535178
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.1219436358
Short name T454
Test name
Test status
Simulation time 2010083075 ps
CPU time 5.82 seconds
Started Feb 21 03:00:57 PM PST 24
Finished Feb 21 03:01:03 PM PST 24
Peak memory 201436 kb
Host smart-8834dcd8-ce83-4ad3-bbcb-7da8bcf083b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219436358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.1219436358
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3434845809
Short name T26
Test name
Test status
Simulation time 3800181184 ps
CPU time 3.4 seconds
Started Feb 21 03:00:47 PM PST 24
Finished Feb 21 03:00:51 PM PST 24
Peak memory 201480 kb
Host smart-c1c7679f-4d94-423b-82c3-68698b0a2574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434845809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3
434845809
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2996955016
Short name T232
Test name
Test status
Simulation time 57805195101 ps
CPU time 147.82 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:02:58 PM PST 24
Peak memory 201684 kb
Host smart-430b1d51-1cd0-4b77-a225-4f90a7f0a7d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996955016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.2996955016
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.527582398
Short name T89
Test name
Test status
Simulation time 221943933280 ps
CPU time 315.64 seconds
Started Feb 21 03:00:54 PM PST 24
Finished Feb 21 03:06:10 PM PST 24
Peak memory 201604 kb
Host smart-600eba3c-a90b-49cd-83e5-7e72da0cfe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527582398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_wi
th_pre_cond.527582398
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3494270561
Short name T713
Test name
Test status
Simulation time 3356098323 ps
CPU time 8.96 seconds
Started Feb 21 03:00:52 PM PST 24
Finished Feb 21 03:01:01 PM PST 24
Peak memory 201396 kb
Host smart-ad6c587c-c33f-41c2-a350-13080a157b1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494270561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.3494270561
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1442584847
Short name T208
Test name
Test status
Simulation time 3946364108 ps
CPU time 3.75 seconds
Started Feb 21 03:00:50 PM PST 24
Finished Feb 21 03:00:55 PM PST 24
Peak memory 201440 kb
Host smart-d061feaa-aa3d-4201-86c4-bea4d2996725
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442584847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.1442584847
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.156641515
Short name T406
Test name
Test status
Simulation time 2628668300 ps
CPU time 2.32 seconds
Started Feb 21 03:00:25 PM PST 24
Finished Feb 21 03:00:28 PM PST 24
Peak memory 201412 kb
Host smart-43940604-8496-4136-b654-eb1cf4ad0f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156641515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.156641515
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.99917248
Short name T759
Test name
Test status
Simulation time 2456296107 ps
CPU time 8.51 seconds
Started Feb 21 03:00:41 PM PST 24
Finished Feb 21 03:00:49 PM PST 24
Peak memory 201428 kb
Host smart-fc1c2a02-0961-4924-83ef-fc710139b091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99917248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.99917248
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2146082996
Short name T491
Test name
Test status
Simulation time 2226584083 ps
CPU time 6.91 seconds
Started Feb 21 03:00:30 PM PST 24
Finished Feb 21 03:00:39 PM PST 24
Peak memory 201640 kb
Host smart-1edc9252-467d-45c4-8d28-ed060233e424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146082996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2146082996
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1174714099
Short name T672
Test name
Test status
Simulation time 2532175505 ps
CPU time 2.13 seconds
Started Feb 21 03:00:40 PM PST 24
Finished Feb 21 03:00:42 PM PST 24
Peak memory 201496 kb
Host smart-7f2727c3-67e8-46f4-bc00-b6d87a177a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174714099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1174714099
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.3435181724
Short name T4
Test name
Test status
Simulation time 2127651706 ps
CPU time 1.98 seconds
Started Feb 21 03:00:45 PM PST 24
Finished Feb 21 03:00:47 PM PST 24
Peak memory 201376 kb
Host smart-7e54a746-89a8-48d6-997c-aa6d10036c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435181724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3435181724
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.2017250223
Short name T193
Test name
Test status
Simulation time 10334132854 ps
CPU time 6.91 seconds
Started Feb 21 03:00:55 PM PST 24
Finished Feb 21 03:01:02 PM PST 24
Peak memory 201412 kb
Host smart-162048cc-7a3b-401a-8de0-91a4441ff62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017250223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.2017250223
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2991794866
Short name T222
Test name
Test status
Simulation time 661873711915 ps
CPU time 39 seconds
Started Feb 21 03:00:29 PM PST 24
Finished Feb 21 03:01:09 PM PST 24
Peak memory 201840 kb
Host smart-28b7f659-212e-4c2b-8fb8-cdbd30b6dfc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991794866 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2991794866
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.3672643634
Short name T762
Test name
Test status
Simulation time 2019082684 ps
CPU time 3.39 seconds
Started Feb 21 03:01:00 PM PST 24
Finished Feb 21 03:01:04 PM PST 24
Peak memory 201424 kb
Host smart-d5639992-1551-4174-bc93-d3f76cf89d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672643634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.3672643634
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1355489659
Short name T51
Test name
Test status
Simulation time 271433475832 ps
CPU time 383.3 seconds
Started Feb 21 03:01:01 PM PST 24
Finished Feb 21 03:07:24 PM PST 24
Peak memory 201452 kb
Host smart-978449ae-ca4e-41c9-8f05-7d285cb22aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355489659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1
355489659
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.4057250204
Short name T330
Test name
Test status
Simulation time 56879403035 ps
CPU time 18.4 seconds
Started Feb 21 03:00:50 PM PST 24
Finished Feb 21 03:01:10 PM PST 24
Peak memory 201664 kb
Host smart-a2d022cd-02d8-4d16-ac0a-45ef4d3b32b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057250204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.4057250204
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2846952349
Short name T407
Test name
Test status
Simulation time 25342691093 ps
CPU time 34.56 seconds
Started Feb 21 03:00:49 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201636 kb
Host smart-82c8a88c-df12-4ce3-b589-dec84bd14ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846952349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.2846952349
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.496530274
Short name T731
Test name
Test status
Simulation time 3750990018 ps
CPU time 5.84 seconds
Started Feb 21 03:00:53 PM PST 24
Finished Feb 21 03:01:00 PM PST 24
Peak memory 201408 kb
Host smart-acb1b9f2-047b-4cb5-ab0a-5e932073eb7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496530274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_ec_pwr_on_rst.496530274
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2100439145
Short name T168
Test name
Test status
Simulation time 3107109469 ps
CPU time 3.16 seconds
Started Feb 21 03:00:56 PM PST 24
Finished Feb 21 03:00:59 PM PST 24
Peak memory 201412 kb
Host smart-138b0e3b-b3da-4cce-bdaa-39787d3497dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100439145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.2100439145
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1965693311
Short name T564
Test name
Test status
Simulation time 2635779348 ps
CPU time 2.42 seconds
Started Feb 21 03:01:00 PM PST 24
Finished Feb 21 03:01:03 PM PST 24
Peak memory 201404 kb
Host smart-8ee31a39-8315-40b7-961a-eea2d875eb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965693311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1965693311
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2448904084
Short name T173
Test name
Test status
Simulation time 2448769057 ps
CPU time 7.4 seconds
Started Feb 21 03:00:46 PM PST 24
Finished Feb 21 03:00:54 PM PST 24
Peak memory 201628 kb
Host smart-b0810b39-aac6-4a36-97b9-0aecc0f58c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448904084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2448904084
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3182431070
Short name T542
Test name
Test status
Simulation time 2277501907 ps
CPU time 2.31 seconds
Started Feb 21 03:00:50 PM PST 24
Finished Feb 21 03:00:53 PM PST 24
Peak memory 201460 kb
Host smart-7f83e998-8076-4eca-8d1a-cc82558b2bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182431070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.3182431070
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.4102146401
Short name T760
Test name
Test status
Simulation time 2537247542 ps
CPU time 2.32 seconds
Started Feb 21 03:00:50 PM PST 24
Finished Feb 21 03:00:53 PM PST 24
Peak memory 201392 kb
Host smart-84d9229f-ca2e-4db8-9bd0-908445dc5d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102146401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.4102146401
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.1945927912
Short name T585
Test name
Test status
Simulation time 2109094623 ps
CPU time 6.18 seconds
Started Feb 21 03:00:54 PM PST 24
Finished Feb 21 03:01:01 PM PST 24
Peak memory 201364 kb
Host smart-f29d0a13-5704-4db8-96c3-55f632cd995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945927912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.1945927912
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.4037586946
Short name T385
Test name
Test status
Simulation time 7370174342 ps
CPU time 3.22 seconds
Started Feb 21 03:01:04 PM PST 24
Finished Feb 21 03:01:07 PM PST 24
Peak memory 201424 kb
Host smart-577f5912-85b8-4e4f-a4c5-ac67b0247feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037586946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.4037586946
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1331528841
Short name T277
Test name
Test status
Simulation time 128532190915 ps
CPU time 158.5 seconds
Started Feb 21 03:00:55 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 210032 kb
Host smart-250374b0-112a-4315-bf61-ad220cd91522
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331528841 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.1331528841
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3605618853
Short name T288
Test name
Test status
Simulation time 3383016713 ps
CPU time 1.09 seconds
Started Feb 21 03:00:56 PM PST 24
Finished Feb 21 03:00:57 PM PST 24
Peak memory 201388 kb
Host smart-36408579-1fae-41fc-9d56-161ccf8d2a87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605618853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.3605618853
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.4289903782
Short name T364
Test name
Test status
Simulation time 2114792692 ps
CPU time 1.26 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201428 kb
Host smart-79374005-9faf-4688-a781-9ef8a3e91d6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289903782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.4289903782
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3046919134
Short name T462
Test name
Test status
Simulation time 3251715516 ps
CPU time 9.83 seconds
Started Feb 21 02:59:57 PM PST 24
Finished Feb 21 03:00:08 PM PST 24
Peak memory 201548 kb
Host smart-bd26bd47-0e74-4e8a-abd1-f9e5c0ef29ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046919134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3046919134
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1116423198
Short name T234
Test name
Test status
Simulation time 42812849802 ps
CPU time 52.39 seconds
Started Feb 21 02:59:48 PM PST 24
Finished Feb 21 03:00:41 PM PST 24
Peak memory 201620 kb
Host smart-87668086-c9fb-452a-9318-a507bd2aa425
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116423198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.1116423198
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2949689547
Short name T779
Test name
Test status
Simulation time 2406652615 ps
CPU time 2.25 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:00:13 PM PST 24
Peak memory 201368 kb
Host smart-fa564903-8bc3-4f18-8153-aca556b31f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949689547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.2949689547
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1275977025
Short name T531
Test name
Test status
Simulation time 2531178213 ps
CPU time 2.45 seconds
Started Feb 21 02:59:47 PM PST 24
Finished Feb 21 02:59:49 PM PST 24
Peak memory 201648 kb
Host smart-b171ec21-a269-4809-bd60-4c09ce09d590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275977025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1275977025
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.979864745
Short name T202
Test name
Test status
Simulation time 2791489566 ps
CPU time 2.32 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:22 PM PST 24
Peak memory 201436 kb
Host smart-0fe596e3-9388-4b87-880c-7c5939e77353
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979864745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_ec_pwr_on_rst.979864745
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.540306988
Short name T180
Test name
Test status
Simulation time 2589647808 ps
CPU time 1.77 seconds
Started Feb 21 02:59:44 PM PST 24
Finished Feb 21 02:59:46 PM PST 24
Peak memory 201408 kb
Host smart-b73d6317-86b9-4882-a28a-061e24d6c787
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540306988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_edge_detect.540306988
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3788532384
Short name T373
Test name
Test status
Simulation time 2621571485 ps
CPU time 4.39 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:54 PM PST 24
Peak memory 201432 kb
Host smart-f0c8988e-2165-4d57-850c-660f5313715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788532384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.3788532384
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.2676596995
Short name T468
Test name
Test status
Simulation time 2475203887 ps
CPU time 7.53 seconds
Started Feb 21 02:59:46 PM PST 24
Finished Feb 21 02:59:54 PM PST 24
Peak memory 201628 kb
Host smart-dd77e8da-13e7-40b5-9720-52c9498e227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676596995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.2676596995
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.457440474
Short name T405
Test name
Test status
Simulation time 2085586257 ps
CPU time 3.02 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:00:03 PM PST 24
Peak memory 201360 kb
Host smart-aff376dc-c5d0-4aff-8adb-a6f5ec105fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457440474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.457440474
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.787325069
Short name T285
Test name
Test status
Simulation time 2535638677 ps
CPU time 2.4 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:51 PM PST 24
Peak memory 201428 kb
Host smart-cb1c7632-b253-4b95-af51-79b5fd0bf526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787325069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.787325069
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.4053046327
Short name T266
Test name
Test status
Simulation time 22055696813 ps
CPU time 16.05 seconds
Started Feb 21 03:00:03 PM PST 24
Finished Feb 21 03:00:20 PM PST 24
Peak memory 221068 kb
Host smart-4ffdeb76-87ee-479e-b88d-19d14a7736e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053046327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.4053046327
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2962278829
Short name T680
Test name
Test status
Simulation time 2107409843 ps
CPU time 6.33 seconds
Started Feb 21 02:59:43 PM PST 24
Finished Feb 21 02:59:50 PM PST 24
Peak memory 201348 kb
Host smart-29541a96-8d87-46be-bee1-bd1dad2df69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962278829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2962278829
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.853658841
Short name T607
Test name
Test status
Simulation time 8056270297 ps
CPU time 4.38 seconds
Started Feb 21 02:59:53 PM PST 24
Finished Feb 21 02:59:59 PM PST 24
Peak memory 201424 kb
Host smart-627747a4-0b51-40c1-a6bb-734ec4a27b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853658841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_str
ess_all.853658841
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2602720649
Short name T128
Test name
Test status
Simulation time 4372323619 ps
CPU time 1.25 seconds
Started Feb 21 02:59:46 PM PST 24
Finished Feb 21 02:59:47 PM PST 24
Peak memory 201424 kb
Host smart-ae706213-f670-41af-9312-53c4f2ffa984
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602720649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2602720649
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.759179988
Short name T106
Test name
Test status
Simulation time 2013660871 ps
CPU time 5.79 seconds
Started Feb 21 03:00:56 PM PST 24
Finished Feb 21 03:01:02 PM PST 24
Peak memory 201424 kb
Host smart-805314fe-71bb-4dca-b7b0-3b408b5692a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759179988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_tes
t.759179988
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2165461360
Short name T541
Test name
Test status
Simulation time 3612291357 ps
CPU time 5.77 seconds
Started Feb 21 03:00:49 PM PST 24
Finished Feb 21 03:00:56 PM PST 24
Peak memory 201484 kb
Host smart-ea695337-a2de-473b-88c2-2af403608519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165461360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.2
165461360
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.1985204597
Short name T332
Test name
Test status
Simulation time 98056434016 ps
CPU time 269.13 seconds
Started Feb 21 03:00:55 PM PST 24
Finished Feb 21 03:05:24 PM PST 24
Peak memory 201604 kb
Host smart-d8480a74-e8d7-4356-9ddf-07de31f6c4d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985204597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.1985204597
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2784851437
Short name T154
Test name
Test status
Simulation time 27279717679 ps
CPU time 5.75 seconds
Started Feb 21 03:00:52 PM PST 24
Finished Feb 21 03:00:58 PM PST 24
Peak memory 201616 kb
Host smart-008b5aef-df2f-4014-a45c-d988b2a75a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784851437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.2784851437
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.103976548
Short name T707
Test name
Test status
Simulation time 3457952622 ps
CPU time 9.27 seconds
Started Feb 21 03:00:47 PM PST 24
Finished Feb 21 03:00:57 PM PST 24
Peak memory 201428 kb
Host smart-a4a76274-d63a-4b59-a246-b02b1a1753f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103976548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ec_pwr_on_rst.103976548
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3793787583
Short name T11
Test name
Test status
Simulation time 4208704927 ps
CPU time 7.21 seconds
Started Feb 21 03:00:57 PM PST 24
Finished Feb 21 03:01:05 PM PST 24
Peak memory 201416 kb
Host smart-bbedfa67-9e09-4e24-bbd1-ef0193d01199
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793787583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.3793787583
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.195902646
Short name T432
Test name
Test status
Simulation time 2612195909 ps
CPU time 6.52 seconds
Started Feb 21 03:00:54 PM PST 24
Finished Feb 21 03:01:02 PM PST 24
Peak memory 201428 kb
Host smart-3fea711c-8bf8-46d9-bae5-559e5706005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195902646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.195902646
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3054637183
Short name T641
Test name
Test status
Simulation time 2499408073 ps
CPU time 2.39 seconds
Started Feb 21 03:00:50 PM PST 24
Finished Feb 21 03:00:53 PM PST 24
Peak memory 201432 kb
Host smart-87a1ffd2-1cd2-4075-8929-b34b88b57539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054637183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3054637183
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.2851122493
Short name T54
Test name
Test status
Simulation time 2166798215 ps
CPU time 6.31 seconds
Started Feb 21 03:00:57 PM PST 24
Finished Feb 21 03:01:04 PM PST 24
Peak memory 201400 kb
Host smart-b1f36082-ab99-4e7d-9de6-bae58e798c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851122493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.2851122493
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1281378412
Short name T758
Test name
Test status
Simulation time 2508543027 ps
CPU time 7.45 seconds
Started Feb 21 03:00:52 PM PST 24
Finished Feb 21 03:01:01 PM PST 24
Peak memory 201496 kb
Host smart-b7f77fba-b1e6-4058-be95-cd94cb6c351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281378412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1281378412
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.289681965
Short name T442
Test name
Test status
Simulation time 2114380887 ps
CPU time 5.81 seconds
Started Feb 21 03:00:53 PM PST 24
Finished Feb 21 03:01:00 PM PST 24
Peak memory 201360 kb
Host smart-6cfc3898-09cb-4e3c-81fd-26bb4ec8ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289681965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.289681965
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.3759677695
Short name T375
Test name
Test status
Simulation time 9212667200 ps
CPU time 6.91 seconds
Started Feb 21 03:00:55 PM PST 24
Finished Feb 21 03:01:02 PM PST 24
Peak memory 201444 kb
Host smart-7cdc3ad6-d69e-4f6b-ade8-6d37331bc337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759677695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.3759677695
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1472789372
Short name T276
Test name
Test status
Simulation time 61934975890 ps
CPU time 144.28 seconds
Started Feb 21 03:00:47 PM PST 24
Finished Feb 21 03:03:12 PM PST 24
Peak memory 210088 kb
Host smart-8e7a7d76-065f-4dc7-898b-40a0b205539a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472789372 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1472789372
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.30741587
Short name T735
Test name
Test status
Simulation time 2732854848 ps
CPU time 3.71 seconds
Started Feb 21 03:00:53 PM PST 24
Finished Feb 21 03:00:58 PM PST 24
Peak memory 201488 kb
Host smart-bdfe1c14-ac73-4ab5-bba4-b0a7ef419813
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30741587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_ultra_low_pwr.30741587
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.1901115511
Short name T573
Test name
Test status
Simulation time 2130253411 ps
CPU time 0.96 seconds
Started Feb 21 03:00:57 PM PST 24
Finished Feb 21 03:00:58 PM PST 24
Peak memory 201448 kb
Host smart-c837ee8a-9843-45c6-81ee-2c14b9e682bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901115511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.1901115511
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.171238128
Short name T50
Test name
Test status
Simulation time 3736326568 ps
CPU time 6.2 seconds
Started Feb 21 03:01:02 PM PST 24
Finished Feb 21 03:01:08 PM PST 24
Peak memory 201488 kb
Host smart-8022f832-18c4-4bf0-a6e5-dfd9e28d7544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171238128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.171238128
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.773876977
Short name T576
Test name
Test status
Simulation time 74626547070 ps
CPU time 60.98 seconds
Started Feb 21 03:00:56 PM PST 24
Finished Feb 21 03:01:57 PM PST 24
Peak memory 201592 kb
Host smart-c8cdcda1-8d7a-4eee-8d82-085038037d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773876977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_wi
th_pre_cond.773876977
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.215384240
Short name T382
Test name
Test status
Simulation time 2466187525 ps
CPU time 3.79 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:17 PM PST 24
Peak memory 201404 kb
Host smart-f93c3c5b-74ec-4fc7-b9a9-d2b798378c6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215384240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_ec_pwr_on_rst.215384240
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2900011691
Short name T503
Test name
Test status
Simulation time 4051022248 ps
CPU time 3.87 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:18 PM PST 24
Peak memory 201424 kb
Host smart-030b43aa-43fa-4cf4-bb9e-c53c95a58ec2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900011691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.2900011691
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.266074762
Short name T207
Test name
Test status
Simulation time 2642324977 ps
CPU time 2.19 seconds
Started Feb 21 03:00:59 PM PST 24
Finished Feb 21 03:01:02 PM PST 24
Peak memory 201492 kb
Host smart-e3cce4e8-84d3-4d9f-94bc-a8e3e1180eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266074762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.266074762
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1092819475
Short name T280
Test name
Test status
Simulation time 2461320283 ps
CPU time 3.14 seconds
Started Feb 21 03:00:49 PM PST 24
Finished Feb 21 03:00:53 PM PST 24
Peak memory 201656 kb
Host smart-2e3e7d0e-8711-4055-8354-b1160e5f3534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092819475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1092819475
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.3949425085
Short name T453
Test name
Test status
Simulation time 2170708063 ps
CPU time 1.13 seconds
Started Feb 21 03:00:56 PM PST 24
Finished Feb 21 03:00:57 PM PST 24
Peak memory 201332 kb
Host smart-d7b8a5d9-29c0-4577-b458-4cc416c65dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949425085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3949425085
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.941809926
Short name T765
Test name
Test status
Simulation time 2532527779 ps
CPU time 2.54 seconds
Started Feb 21 03:00:51 PM PST 24
Finished Feb 21 03:00:54 PM PST 24
Peak memory 201432 kb
Host smart-4462b6f4-0eb4-43c4-bdf5-90ee70ed3d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941809926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.941809926
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.1640205369
Short name T511
Test name
Test status
Simulation time 2111349863 ps
CPU time 6.28 seconds
Started Feb 21 03:00:50 PM PST 24
Finished Feb 21 03:00:58 PM PST 24
Peak memory 201384 kb
Host smart-3e168057-7524-49e1-93bb-d86c82ae385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640205369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.1640205369
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.1975323257
Short name T123
Test name
Test status
Simulation time 55275470091 ps
CPU time 135.68 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:03:27 PM PST 24
Peak memory 201592 kb
Host smart-cbbab522-3a57-4d6b-9a4e-b98896dbc403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975323257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.1975323257
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3426025330
Short name T32
Test name
Test status
Simulation time 23508550932 ps
CPU time 60.5 seconds
Started Feb 21 03:00:56 PM PST 24
Finished Feb 21 03:01:57 PM PST 24
Peak memory 210864 kb
Host smart-36f8ea96-985b-4a62-b040-1ac94c630aca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426025330 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.3426025330
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1039818203
Short name T138
Test name
Test status
Simulation time 8433696430 ps
CPU time 8.46 seconds
Started Feb 21 03:01:10 PM PST 24
Finished Feb 21 03:01:19 PM PST 24
Peak memory 201416 kb
Host smart-43d4b232-318d-414b-b9b0-3954820c25b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039818203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.1039818203
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.2094347633
Short name T246
Test name
Test status
Simulation time 2011824931 ps
CPU time 6.43 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:20 PM PST 24
Peak memory 201448 kb
Host smart-808d7fd1-ea6d-443f-b6a7-faffac8f9bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094347633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.2094347633
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1769815791
Short name T742
Test name
Test status
Simulation time 3657679673 ps
CPU time 2.94 seconds
Started Feb 21 03:01:03 PM PST 24
Finished Feb 21 03:01:06 PM PST 24
Peak memory 201512 kb
Host smart-104b582e-2bb3-4c2b-953c-2a33be18ca4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769815791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.1
769815791
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.154649898
Short name T231
Test name
Test status
Simulation time 151517852020 ps
CPU time 381.69 seconds
Started Feb 21 03:01:09 PM PST 24
Finished Feb 21 03:07:31 PM PST 24
Peak memory 201676 kb
Host smart-461f622c-b48a-4c86-a612-81742abb1433
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154649898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_combo_detect.154649898
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1460176443
Short name T506
Test name
Test status
Simulation time 71843121660 ps
CPU time 49.6 seconds
Started Feb 21 03:01:01 PM PST 24
Finished Feb 21 03:01:51 PM PST 24
Peak memory 201704 kb
Host smart-69f3e8b3-9183-4c01-b240-75b501ecc728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460176443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.1460176443
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1806718061
Short name T691
Test name
Test status
Simulation time 4631674285 ps
CPU time 12.63 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201412 kb
Host smart-758454c7-2c23-49d7-b77b-af3b50cf9153
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806718061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.1806718061
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1837199782
Short name T566
Test name
Test status
Simulation time 2577706526 ps
CPU time 7.08 seconds
Started Feb 21 03:00:48 PM PST 24
Finished Feb 21 03:00:56 PM PST 24
Peak memory 201656 kb
Host smart-0154942a-d5a3-49af-b89e-bbf0dadf2d8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837199782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.1837199782
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1410160675
Short name T487
Test name
Test status
Simulation time 2608922994 ps
CPU time 7.9 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:21 PM PST 24
Peak memory 201404 kb
Host smart-4878357e-47d9-499f-9d7a-3b57af355754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410160675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.1410160675
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3931916714
Short name T766
Test name
Test status
Simulation time 2467117641 ps
CPU time 2.43 seconds
Started Feb 21 03:01:10 PM PST 24
Finished Feb 21 03:01:13 PM PST 24
Peak memory 201412 kb
Host smart-8a900aa1-2194-4127-b782-c99f7b92720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931916714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3931916714
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1857624296
Short name T780
Test name
Test status
Simulation time 2249361783 ps
CPU time 6.34 seconds
Started Feb 21 03:00:56 PM PST 24
Finished Feb 21 03:01:03 PM PST 24
Peak memory 201408 kb
Host smart-9eb0ea9d-5743-4cb5-97c6-a08c0f543496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857624296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1857624296
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1401904294
Short name T653
Test name
Test status
Simulation time 2513555078 ps
CPU time 4.04 seconds
Started Feb 21 03:01:14 PM PST 24
Finished Feb 21 03:01:19 PM PST 24
Peak memory 201448 kb
Host smart-2e31a21d-5920-418c-8cb3-73f146fe50f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401904294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.1401904294
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.2616858163
Short name T710
Test name
Test status
Simulation time 2135747561 ps
CPU time 1.89 seconds
Started Feb 21 03:00:51 PM PST 24
Finished Feb 21 03:00:53 PM PST 24
Peak memory 201364 kb
Host smart-1b63e626-ad25-43e4-a106-5fbcfb617cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616858163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2616858163
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.3001593170
Short name T497
Test name
Test status
Simulation time 8654130850 ps
CPU time 9.75 seconds
Started Feb 21 03:00:52 PM PST 24
Finished Feb 21 03:01:02 PM PST 24
Peak memory 201376 kb
Host smart-a561989b-ba82-4267-b790-31616f5be5db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001593170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.3001593170
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.627598781
Short name T122
Test name
Test status
Simulation time 5111530994 ps
CPU time 2.4 seconds
Started Feb 21 03:00:51 PM PST 24
Finished Feb 21 03:00:54 PM PST 24
Peak memory 201496 kb
Host smart-9846d4c2-5711-42d9-abb1-ef10637ac646
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627598781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_ultra_low_pwr.627598781
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.1957027295
Short name T757
Test name
Test status
Simulation time 2022625048 ps
CPU time 2.49 seconds
Started Feb 21 03:01:05 PM PST 24
Finished Feb 21 03:01:08 PM PST 24
Peak memory 201444 kb
Host smart-e9087939-fe76-4444-b499-b978bb4ddd7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957027295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.1957027295
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2453505255
Short name T560
Test name
Test status
Simulation time 3605333117 ps
CPU time 2.61 seconds
Started Feb 21 03:01:03 PM PST 24
Finished Feb 21 03:01:06 PM PST 24
Peak memory 201512 kb
Host smart-d67142f0-6976-4e0f-828b-826ea73961bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453505255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.2
453505255
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.2896769619
Short name T539
Test name
Test status
Simulation time 136553844797 ps
CPU time 374.45 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:07:26 PM PST 24
Peak memory 201648 kb
Host smart-793e1aca-f02b-4263-bfa6-83964e10bcc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896769619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.2896769619
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.4024352660
Short name T520
Test name
Test status
Simulation time 35937618320 ps
CPU time 23.04 seconds
Started Feb 21 03:01:01 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201676 kb
Host smart-13372b23-9799-4cfe-a57a-961ae68dddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024352660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.4024352660
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2688612347
Short name T523
Test name
Test status
Simulation time 3214578291 ps
CPU time 3.01 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:16 PM PST 24
Peak memory 201428 kb
Host smart-344d5c2f-0a66-4b4f-be48-3e0bb2074f01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688612347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.2688612347
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.365099617
Short name T749
Test name
Test status
Simulation time 3880427562 ps
CPU time 2.51 seconds
Started Feb 21 03:01:10 PM PST 24
Finished Feb 21 03:01:13 PM PST 24
Peak memory 201312 kb
Host smart-9856a853-8bbb-4104-8627-cee460b4c146
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365099617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctr
l_edge_detect.365099617
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3519597243
Short name T383
Test name
Test status
Simulation time 2617090375 ps
CPU time 4.07 seconds
Started Feb 21 03:01:15 PM PST 24
Finished Feb 21 03:01:19 PM PST 24
Peak memory 201444 kb
Host smart-f2ba0a7a-3fda-454e-a9d7-00264f65a9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519597243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3519597243
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2734048398
Short name T552
Test name
Test status
Simulation time 2456883257 ps
CPU time 2.42 seconds
Started Feb 21 03:01:01 PM PST 24
Finished Feb 21 03:01:03 PM PST 24
Peak memory 201412 kb
Host smart-61b01c33-8f59-42ab-8549-0f4a73fe7ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734048398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2734048398
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3069211167
Short name T700
Test name
Test status
Simulation time 2147413213 ps
CPU time 1.44 seconds
Started Feb 21 03:00:58 PM PST 24
Finished Feb 21 03:01:00 PM PST 24
Peak memory 201556 kb
Host smart-910778ee-525b-4635-911a-f7537ea82ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069211167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3069211167
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3452625750
Short name T650
Test name
Test status
Simulation time 2512421379 ps
CPU time 5.66 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:18 PM PST 24
Peak memory 201408 kb
Host smart-d709025b-5c3c-4e42-8177-48b365754d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452625750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.3452625750
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.2643684132
Short name T399
Test name
Test status
Simulation time 2122844837 ps
CPU time 3.41 seconds
Started Feb 21 03:01:00 PM PST 24
Finished Feb 21 03:01:04 PM PST 24
Peak memory 201324 kb
Host smart-ebbd4175-f195-4e1b-a53c-118a55e264d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643684132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.2643684132
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.763329739
Short name T295
Test name
Test status
Simulation time 12673448663 ps
CPU time 5.89 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:19 PM PST 24
Peak memory 201492 kb
Host smart-ef50337c-31b8-4767-95d7-0df0b7134bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763329739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_st
ress_all.763329739
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2340611039
Short name T82
Test name
Test status
Simulation time 3960508004 ps
CPU time 7.51 seconds
Started Feb 21 03:00:59 PM PST 24
Finished Feb 21 03:01:07 PM PST 24
Peak memory 201424 kb
Host smart-f73aa477-d7f7-4188-9d1b-535287c0a128
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340611039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.2340611039
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.516504942
Short name T635
Test name
Test status
Simulation time 2013760561 ps
CPU time 5.3 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:01:16 PM PST 24
Peak memory 201464 kb
Host smart-22123a7a-3dcd-4621-87bd-586dc6bc0f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516504942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_tes
t.516504942
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1602135257
Short name T329
Test name
Test status
Simulation time 151584940075 ps
CPU time 82.16 seconds
Started Feb 21 03:01:09 PM PST 24
Finished Feb 21 03:02:32 PM PST 24
Peak memory 201612 kb
Host smart-51ef851b-eef7-4188-8b32-a3835fe46dc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602135257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.1602135257
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1589489946
Short name T457
Test name
Test status
Simulation time 3875736404 ps
CPU time 2.98 seconds
Started Feb 21 03:00:55 PM PST 24
Finished Feb 21 03:00:58 PM PST 24
Peak memory 201444 kb
Host smart-8825fec5-ca89-4dc8-935e-ae32e1eb9a62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589489946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.1589489946
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1629376601
Short name T189
Test name
Test status
Simulation time 5552484009 ps
CPU time 2.16 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:16 PM PST 24
Peak memory 201448 kb
Host smart-1c225f33-6375-457d-939f-ebd50f5e33a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629376601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1629376601
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3089712328
Short name T642
Test name
Test status
Simulation time 2613011170 ps
CPU time 7.75 seconds
Started Feb 21 03:01:14 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201452 kb
Host smart-39f0ef83-97ef-42e0-85a0-3e2a7563fd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089712328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.3089712328
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.83125912
Short name T587
Test name
Test status
Simulation time 2479023403 ps
CPU time 1.76 seconds
Started Feb 21 03:00:58 PM PST 24
Finished Feb 21 03:01:01 PM PST 24
Peak memory 201416 kb
Host smart-e4e857c1-76d5-431b-92ad-8d2e8b40cc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83125912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.83125912
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.2244823731
Short name T424
Test name
Test status
Simulation time 2145880421 ps
CPU time 6.37 seconds
Started Feb 21 03:01:03 PM PST 24
Finished Feb 21 03:01:09 PM PST 24
Peak memory 201364 kb
Host smart-3d347bed-488c-480a-93c1-9bcd4381afc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244823731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2244823731
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.821975997
Short name T418
Test name
Test status
Simulation time 2536754388 ps
CPU time 2.04 seconds
Started Feb 21 03:00:57 PM PST 24
Finished Feb 21 03:00:59 PM PST 24
Peak memory 201380 kb
Host smart-31920219-f6fe-457d-b6eb-55b7b4874ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821975997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.821975997
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.2156991437
Short name T470
Test name
Test status
Simulation time 2107386819 ps
CPU time 6.01 seconds
Started Feb 21 03:01:14 PM PST 24
Finished Feb 21 03:01:21 PM PST 24
Peak memory 201344 kb
Host smart-2d09e156-4ed6-46c7-9974-a9c9304cb8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156991437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.2156991437
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.2485031609
Short name T326
Test name
Test status
Simulation time 124191316594 ps
CPU time 80.81 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:02:35 PM PST 24
Peak memory 201560 kb
Host smart-caae0e65-ca0c-42bd-ac31-5fd98dd0f122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485031609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.2485031609
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2267905374
Short name T660
Test name
Test status
Simulation time 7839317480 ps
CPU time 4.63 seconds
Started Feb 21 03:00:59 PM PST 24
Finished Feb 21 03:01:04 PM PST 24
Peak memory 201492 kb
Host smart-1cee847f-e9c3-4425-96b8-58a47e1aeacf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267905374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2267905374
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.2740819444
Short name T784
Test name
Test status
Simulation time 2019036404 ps
CPU time 3.41 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:17 PM PST 24
Peak memory 201440 kb
Host smart-4ad3d2a2-aa8c-4caa-ac43-dc0d994385d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740819444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.2740819444
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2922809924
Short name T271
Test name
Test status
Simulation time 3166909303 ps
CPU time 8.91 seconds
Started Feb 21 03:01:14 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201536 kb
Host smart-9aa86832-3620-43d2-85ea-4c7a248361f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922809924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.2
922809924
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1435441627
Short name T676
Test name
Test status
Simulation time 23089705575 ps
CPU time 32.57 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:01:45 PM PST 24
Peak memory 201688 kb
Host smart-f8b70aad-801e-4b69-98b1-279f323f411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435441627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.1435441627
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2781226068
Short name T449
Test name
Test status
Simulation time 3339921665 ps
CPU time 9.25 seconds
Started Feb 21 03:01:06 PM PST 24
Finished Feb 21 03:01:15 PM PST 24
Peak memory 201424 kb
Host smart-33e3d08f-382a-4cf0-96c0-3ff58c6a06a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781226068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.2781226068
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.3991026915
Short name T191
Test name
Test status
Simulation time 2783386742 ps
CPU time 7.42 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:20 PM PST 24
Peak memory 201416 kb
Host smart-b1111917-6e7e-455b-8bd7-904b4c6ec7a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991026915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.3991026915
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1201434209
Short name T751
Test name
Test status
Simulation time 2611660294 ps
CPU time 7.85 seconds
Started Feb 21 03:01:23 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201460 kb
Host smart-8816ba17-9c14-466c-8185-7fa214f4be91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201434209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.1201434209
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2041336301
Short name T465
Test name
Test status
Simulation time 2471384319 ps
CPU time 7.64 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:22 PM PST 24
Peak memory 201428 kb
Host smart-7005ba6d-7f5f-4044-a41e-583bd670ba5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041336301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.2041336301
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.2399968104
Short name T469
Test name
Test status
Simulation time 2144926477 ps
CPU time 3.55 seconds
Started Feb 21 03:01:10 PM PST 24
Finished Feb 21 03:01:14 PM PST 24
Peak memory 201380 kb
Host smart-955aeb5d-ea9e-480e-9e3c-20e3333c0126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399968104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.2399968104
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2952963638
Short name T284
Test name
Test status
Simulation time 2517491643 ps
CPU time 3.91 seconds
Started Feb 21 03:01:09 PM PST 24
Finished Feb 21 03:01:13 PM PST 24
Peak memory 201392 kb
Host smart-c5edba54-8ba8-4ba4-a393-d011fe0150c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952963638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2952963638
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.4105891048
Short name T522
Test name
Test status
Simulation time 2125904706 ps
CPU time 1.93 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:01:13 PM PST 24
Peak memory 201368 kb
Host smart-c7e0e4d8-3a1a-4347-9cd8-b306671d4c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105891048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.4105891048
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.1294639415
Short name T441
Test name
Test status
Simulation time 6876181220 ps
CPU time 5.79 seconds
Started Feb 21 03:01:10 PM PST 24
Finished Feb 21 03:01:17 PM PST 24
Peak memory 201408 kb
Host smart-8eb86f95-8d91-4680-ba48-58080a37e789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294639415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.1294639415
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3911780240
Short name T287
Test name
Test status
Simulation time 4443172575 ps
CPU time 3.53 seconds
Started Feb 21 03:01:10 PM PST 24
Finished Feb 21 03:01:13 PM PST 24
Peak memory 201408 kb
Host smart-3d5d3b8b-9f5a-4448-b82c-b0dc65f50f14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911780240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.3911780240
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.1236256143
Short name T188
Test name
Test status
Simulation time 2014224744 ps
CPU time 5.38 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:19 PM PST 24
Peak memory 201436 kb
Host smart-45a352e5-667e-4941-815b-ea5878ab3521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236256143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.1236256143
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3797134508
Short name T586
Test name
Test status
Simulation time 3152402076 ps
CPU time 8.24 seconds
Started Feb 21 03:01:07 PM PST 24
Finished Feb 21 03:01:16 PM PST 24
Peak memory 201540 kb
Host smart-5736e82b-ae3e-427e-82cf-c0b29e6a7fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797134508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3
797134508
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.110951966
Short name T96
Test name
Test status
Simulation time 92225420194 ps
CPU time 52.62 seconds
Started Feb 21 03:01:23 PM PST 24
Finished Feb 21 03:02:16 PM PST 24
Peak memory 201576 kb
Host smart-2ff919ed-2f97-4d1d-8d41-da97fb990966
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110951966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.110951966
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.1176114314
Short name T229
Test name
Test status
Simulation time 101267527882 ps
CPU time 34.03 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:01:45 PM PST 24
Peak memory 201620 kb
Host smart-07278076-6a48-47f0-9b3d-d618568cbfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176114314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.1176114314
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1788487926
Short name T686
Test name
Test status
Simulation time 3275793845 ps
CPU time 9.21 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201444 kb
Host smart-5ca78123-0f69-45c7-bdb4-741101bd9f2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788487926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.1788487926
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.942799736
Short name T216
Test name
Test status
Simulation time 4540601736 ps
CPU time 2.36 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:01:13 PM PST 24
Peak memory 201444 kb
Host smart-988719fd-a0b8-4ed6-92be-6117efc02472
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942799736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctr
l_edge_detect.942799736
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3238178743
Short name T108
Test name
Test status
Simulation time 2610776493 ps
CPU time 7.24 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:21 PM PST 24
Peak memory 201444 kb
Host smart-b60dc1b2-e8bf-434b-9583-369bdf9b1f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238178743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.3238178743
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.769207421
Short name T438
Test name
Test status
Simulation time 2474657335 ps
CPU time 6.76 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:21 PM PST 24
Peak memory 201428 kb
Host smart-a973d586-d870-4e5b-b675-b0f64a2ebf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769207421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.769207421
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2088103132
Short name T296
Test name
Test status
Simulation time 2127592983 ps
CPU time 6.46 seconds
Started Feb 21 03:01:05 PM PST 24
Finished Feb 21 03:01:12 PM PST 24
Peak memory 201388 kb
Host smart-dc4b7a52-4029-4c4a-8267-f7f77d98f066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088103132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2088103132
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.1658106082
Short name T29
Test name
Test status
Simulation time 2540982565 ps
CPU time 2.35 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:01:14 PM PST 24
Peak memory 201472 kb
Host smart-e820a02d-772d-4f10-abcf-b9f80135a775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658106082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.1658106082
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.71544646
Short name T172
Test name
Test status
Simulation time 2109648174 ps
CPU time 6.23 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:19 PM PST 24
Peak memory 201356 kb
Host smart-6f780f4d-0dc0-477b-b987-358ebeb2e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71544646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.71544646
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2975149574
Short name T696
Test name
Test status
Simulation time 207086413722 ps
CPU time 127.39 seconds
Started Feb 21 03:01:23 PM PST 24
Finished Feb 21 03:03:30 PM PST 24
Peak memory 209988 kb
Host smart-3cc1ddf3-da24-4b69-aca0-91059dfbd1c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975149574 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2975149574
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1555341902
Short name T157
Test name
Test status
Simulation time 4629563892 ps
CPU time 2.09 seconds
Started Feb 21 03:01:23 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201428 kb
Host smart-67ee3c21-7a6a-4f26-ba4d-df591ff62def
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555341902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.1555341902
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.1995485132
Short name T52
Test name
Test status
Simulation time 2024142624 ps
CPU time 1.95 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201424 kb
Host smart-dbac3f34-2510-4ff6-81e4-32e0c9963cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995485132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.1995485132
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2535242705
Short name T621
Test name
Test status
Simulation time 3433605084 ps
CPU time 2.89 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201452 kb
Host smart-610db510-698c-4a83-b5b1-5ddd8b7d0f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535242705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2
535242705
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1996796989
Short name T41
Test name
Test status
Simulation time 24327708148 ps
CPU time 63.02 seconds
Started Feb 21 03:01:18 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 201708 kb
Host smart-54245f71-161d-4bd7-8deb-468e018b1b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996796989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.1996796989
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.880937170
Short name T132
Test name
Test status
Simulation time 3484722901 ps
CPU time 9.8 seconds
Started Feb 21 03:01:10 PM PST 24
Finished Feb 21 03:01:21 PM PST 24
Peak memory 201416 kb
Host smart-c5c3d4f8-b4e5-4a75-ae3a-6cb8cc24694f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880937170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_ec_pwr_on_rst.880937170
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3794486438
Short name T167
Test name
Test status
Simulation time 3608269556 ps
CPU time 10.53 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:33 PM PST 24
Peak memory 201404 kb
Host smart-29fa3e20-da50-46d2-a854-da22dc130edc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794486438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.3794486438
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.4123750931
Short name T648
Test name
Test status
Simulation time 2616928253 ps
CPU time 3.47 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:01:14 PM PST 24
Peak memory 201468 kb
Host smart-d206ce90-f766-46ba-bc1b-d8b517fe3bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123750931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.4123750931
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.1606758744
Short name T580
Test name
Test status
Simulation time 2456693131 ps
CPU time 3.97 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:18 PM PST 24
Peak memory 201452 kb
Host smart-7bafc09e-4bed-4c7b-8ee8-a2b8fc5f848a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606758744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.1606758744
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2780085248
Short name T370
Test name
Test status
Simulation time 2247312067 ps
CPU time 3.5 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:17 PM PST 24
Peak memory 201448 kb
Host smart-b8f0c08b-db72-4fe0-9a08-d4b0ccf9e1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780085248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.2780085248
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.185897043
Short name T205
Test name
Test status
Simulation time 2521638787 ps
CPU time 3.18 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:01:15 PM PST 24
Peak memory 201468 kb
Host smart-15e68007-f76b-4849-a448-fc98a4411e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185897043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.185897043
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.607828413
Short name T30
Test name
Test status
Simulation time 2115145089 ps
CPU time 6.36 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:21 PM PST 24
Peak memory 201360 kb
Host smart-bf2fd652-4adb-4122-9469-abbec47ae887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607828413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.607828413
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.1691932109
Short name T214
Test name
Test status
Simulation time 177824110304 ps
CPU time 81.15 seconds
Started Feb 21 03:01:15 PM PST 24
Finished Feb 21 03:02:36 PM PST 24
Peak memory 201632 kb
Host smart-1e6c5f04-7942-4ef2-b643-3ee8919b9feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691932109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.1691932109
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.18512571
Short name T74
Test name
Test status
Simulation time 39296964779 ps
CPU time 24.74 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:37 PM PST 24
Peak memory 209972 kb
Host smart-2e4a7209-1093-402a-b745-82b2f28be056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18512571 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.18512571
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2227096623
Short name T129
Test name
Test status
Simulation time 3624267394 ps
CPU time 3.36 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201492 kb
Host smart-520e31a2-c2f9-46bb-9d92-ee2ad5d3c526
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227096623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.2227096623
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.4099134284
Short name T492
Test name
Test status
Simulation time 2098985440 ps
CPU time 0.86 seconds
Started Feb 21 03:01:33 PM PST 24
Finished Feb 21 03:01:34 PM PST 24
Peak memory 201396 kb
Host smart-67824be5-f792-49c8-8bb3-57da5f7f2622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099134284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.4099134284
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3608848519
Short name T420
Test name
Test status
Simulation time 3294429472 ps
CPU time 2.93 seconds
Started Feb 21 03:01:14 PM PST 24
Finished Feb 21 03:01:18 PM PST 24
Peak memory 201520 kb
Host smart-60c08f80-17fd-4bf2-8629-178e9db7ac0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608848519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3
608848519
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.1498387122
Short name T72
Test name
Test status
Simulation time 84416348835 ps
CPU time 214.31 seconds
Started Feb 21 03:01:15 PM PST 24
Finished Feb 21 03:04:50 PM PST 24
Peak memory 201676 kb
Host smart-06f6b8ef-ac87-49a9-9de1-7b0ececdbc48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498387122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.1498387122
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1404559468
Short name T184
Test name
Test status
Simulation time 3274482537 ps
CPU time 1.88 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:15 PM PST 24
Peak memory 201428 kb
Host smart-3d511842-ea13-4258-b662-e1426b4869bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404559468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.1404559468
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.1790408123
Short name T565
Test name
Test status
Simulation time 2988920748 ps
CPU time 2.01 seconds
Started Feb 21 03:01:14 PM PST 24
Finished Feb 21 03:01:17 PM PST 24
Peak memory 201476 kb
Host smart-8f1093e8-749e-4265-bedb-f6992a3ce5f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790408123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.1790408123
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2317716692
Short name T605
Test name
Test status
Simulation time 2623912857 ps
CPU time 3.37 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:16 PM PST 24
Peak memory 201472 kb
Host smart-a32082d7-70c3-44f3-8192-0f766c287055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317716692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.2317716692
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1123445656
Short name T62
Test name
Test status
Simulation time 2473850627 ps
CPU time 3.72 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201496 kb
Host smart-316b608f-3ba8-4a23-8d3b-9906cc9eb64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123445656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1123445656
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3539656562
Short name T772
Test name
Test status
Simulation time 2227456524 ps
CPU time 1.33 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201404 kb
Host smart-f892cbc9-8616-4b6d-a537-a824690d541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539656562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3539656562
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3570930012
Short name T679
Test name
Test status
Simulation time 2527633301 ps
CPU time 2.23 seconds
Started Feb 21 03:01:11 PM PST 24
Finished Feb 21 03:01:14 PM PST 24
Peak memory 201432 kb
Host smart-4c4325b2-fa1a-41f7-acd6-4197e5be91aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570930012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.3570930012
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.1545006455
Short name T384
Test name
Test status
Simulation time 2112304812 ps
CPU time 5.97 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:27 PM PST 24
Peak memory 201340 kb
Host smart-5aed2c48-c347-44db-bf1f-4d00b00898e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545006455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1545006455
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.1099445930
Short name T764
Test name
Test status
Simulation time 196286492770 ps
CPU time 261.27 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:05:42 PM PST 24
Peak memory 201640 kb
Host smart-81a326db-1a71-427b-926f-bf4570da18dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099445930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.1099445930
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3694548012
Short name T685
Test name
Test status
Simulation time 7940677306 ps
CPU time 2.5 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201492 kb
Host smart-37e33729-f94a-473c-a3f4-b9da2c514453
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694548012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.3694548012
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3439837186
Short name T421
Test name
Test status
Simulation time 2013327983 ps
CPU time 5.82 seconds
Started Feb 21 03:01:28 PM PST 24
Finished Feb 21 03:01:34 PM PST 24
Peak memory 200692 kb
Host smart-6a163fdc-2fa1-454c-be88-7a1f974e89ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439837186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3439837186
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2927586397
Short name T456
Test name
Test status
Simulation time 3163394202 ps
CPU time 9.09 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:22 PM PST 24
Peak memory 201504 kb
Host smart-a8e2f62f-4b45-44a1-914c-4502ac91046f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927586397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.2
927586397
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.3312891968
Short name T1
Test name
Test status
Simulation time 175317862561 ps
CPU time 379.91 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:07:43 PM PST 24
Peak memory 201556 kb
Host smart-6c2bc755-e933-44cb-9bb3-ad919daaf51a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312891968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.3312891968
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3016797293
Short name T426
Test name
Test status
Simulation time 24583384990 ps
CPU time 67.98 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 201640 kb
Host smart-38a7b247-b0ea-400c-b55c-db15d3d9f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016797293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.3016797293
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.4000931909
Short name T743
Test name
Test status
Simulation time 3170168256 ps
CPU time 4.43 seconds
Started Feb 21 03:01:12 PM PST 24
Finished Feb 21 03:01:17 PM PST 24
Peak memory 201436 kb
Host smart-b4710e5f-7a5f-4cae-9070-099a7f7030c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000931909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.4000931909
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.4062883428
Short name T18
Test name
Test status
Simulation time 3068288167 ps
CPU time 1.55 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:22 PM PST 24
Peak memory 201404 kb
Host smart-a54f5d5c-48ed-4bbb-a3b7-f7d173b467bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062883428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.4062883428
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1277911687
Short name T398
Test name
Test status
Simulation time 2618639313 ps
CPU time 4.2 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201500 kb
Host smart-a2c9e097-a001-4fe6-befa-2b5e284b6965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277911687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1277911687
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3158765999
Short name T667
Test name
Test status
Simulation time 2593396143 ps
CPU time 0.97 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201380 kb
Host smart-6ac4e838-d049-4cdd-be24-5de06987db93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158765999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3158765999
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3744848059
Short name T664
Test name
Test status
Simulation time 2248208783 ps
CPU time 3.51 seconds
Started Feb 21 03:01:14 PM PST 24
Finished Feb 21 03:01:19 PM PST 24
Peak memory 201460 kb
Host smart-c1822440-49df-4db6-ac07-81b9d657854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744848059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.3744848059
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.814791916
Short name T435
Test name
Test status
Simulation time 2526694443 ps
CPU time 2.43 seconds
Started Feb 21 03:01:15 PM PST 24
Finished Feb 21 03:01:18 PM PST 24
Peak memory 201412 kb
Host smart-31feb077-27f5-45bc-8b02-9f698d3752b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814791916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.814791916
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.3813541302
Short name T572
Test name
Test status
Simulation time 2110499854 ps
CPU time 5.96 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201344 kb
Host smart-43d902f9-1c1c-418a-8dca-881fa9e8b13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813541302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3813541302
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.2834517061
Short name T584
Test name
Test status
Simulation time 12996628041 ps
CPU time 3.42 seconds
Started Feb 21 03:01:30 PM PST 24
Finished Feb 21 03:01:34 PM PST 24
Peak memory 201436 kb
Host smart-1c11028f-75a1-44f9-bff9-572ca8f2ea29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834517061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.2834517061
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.4251755978
Short name T597
Test name
Test status
Simulation time 3377547765 ps
CPU time 6.23 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201468 kb
Host smart-6934e955-da23-4fd5-bb79-a90345605a43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251755978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.4251755978
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.3466455531
Short name T763
Test name
Test status
Simulation time 2030308569 ps
CPU time 1.9 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:00:14 PM PST 24
Peak memory 201480 kb
Host smart-0ff1a9e7-beaf-469c-af6c-3d0749a797a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466455531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.3466455531
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3602822408
Short name T754
Test name
Test status
Simulation time 3245586586 ps
CPU time 9.21 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:00:28 PM PST 24
Peak memory 201496 kb
Host smart-969a95b7-4891-41c2-9a5c-01c73c7ef926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602822408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.3602822408
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.1590623903
Short name T8
Test name
Test status
Simulation time 206727092620 ps
CPU time 282.46 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:05:02 PM PST 24
Peak memory 201556 kb
Host smart-b3500a8e-624f-4282-ae58-bc2131bd4be8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590623903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.1590623903
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2451096299
Short name T377
Test name
Test status
Simulation time 2407267789 ps
CPU time 6.7 seconds
Started Feb 21 02:59:55 PM PST 24
Finished Feb 21 03:00:03 PM PST 24
Peak memory 201476 kb
Host smart-d41b810b-4aee-4510-a567-a5b28fb8cec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451096299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2451096299
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1923865079
Short name T596
Test name
Test status
Simulation time 2338084206 ps
CPU time 2.1 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:26 PM PST 24
Peak memory 201416 kb
Host smart-fafb79a1-53cc-4c9b-8d89-e4d911499542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923865079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1923865079
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.4039450354
Short name T489
Test name
Test status
Simulation time 64624807234 ps
CPU time 31.17 seconds
Started Feb 21 02:59:57 PM PST 24
Finished Feb 21 03:00:30 PM PST 24
Peak memory 201624 kb
Host smart-21363bae-62d4-4506-bdcf-f1a1346847f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039450354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.4039450354
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1908702167
Short name T682
Test name
Test status
Simulation time 3309809250 ps
CPU time 2.66 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:15 PM PST 24
Peak memory 201408 kb
Host smart-daeeb9d7-6640-48dd-a7e0-990dab20d846
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908702167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.1908702167
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1780359447
Short name T269
Test name
Test status
Simulation time 2635912701 ps
CPU time 2.18 seconds
Started Feb 21 03:00:09 PM PST 24
Finished Feb 21 03:00:12 PM PST 24
Peak memory 201360 kb
Host smart-94b7797b-2a4d-481a-90bd-147bc9b6823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780359447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.1780359447
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3966598655
Short name T25
Test name
Test status
Simulation time 2482371920 ps
CPU time 2.86 seconds
Started Feb 21 02:59:44 PM PST 24
Finished Feb 21 02:59:47 PM PST 24
Peak memory 201432 kb
Host smart-c943682b-2f38-40e4-9765-8e8340f5eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966598655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.3966598655
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3097902322
Short name T501
Test name
Test status
Simulation time 2233974008 ps
CPU time 6.08 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:55 PM PST 24
Peak memory 201392 kb
Host smart-442a665f-2c23-47e9-8f21-36973574cc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097902322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3097902322
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1295001967
Short name T512
Test name
Test status
Simulation time 2518531010 ps
CPU time 3.79 seconds
Started Feb 21 02:59:54 PM PST 24
Finished Feb 21 02:59:59 PM PST 24
Peak memory 201452 kb
Host smart-ae224b00-1329-4aa3-aa1d-a3df8e63e776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295001967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1295001967
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.643694821
Short name T250
Test name
Test status
Simulation time 22072463228 ps
CPU time 15.31 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:00:27 PM PST 24
Peak memory 221316 kb
Host smart-219c2a62-4400-4d40-8a11-1d236f639d55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643694821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.643694821
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.4270872529
Short name T5
Test name
Test status
Simulation time 2136905860 ps
CPU time 1.92 seconds
Started Feb 21 02:59:54 PM PST 24
Finished Feb 21 02:59:57 PM PST 24
Peak memory 201248 kb
Host smart-89daf970-474f-41ee-a8fb-14e5d0eebcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270872529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.4270872529
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.3285851004
Short name T549
Test name
Test status
Simulation time 9239442974 ps
CPU time 13.44 seconds
Started Feb 21 03:00:07 PM PST 24
Finished Feb 21 03:00:20 PM PST 24
Peak memory 201412 kb
Host smart-95637de8-1d74-4e8d-a715-2db47cad64b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285851004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.3285851004
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2206734329
Short name T97
Test name
Test status
Simulation time 879621615255 ps
CPU time 106.17 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:02:06 PM PST 24
Peak memory 213744 kb
Host smart-aaf05255-1ccd-452c-a099-7ff8aabfb9e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206734329 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.2206734329
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2269665244
Short name T113
Test name
Test status
Simulation time 192764985276 ps
CPU time 13.42 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:33 PM PST 24
Peak memory 201408 kb
Host smart-0b19b9c8-7bb9-40d5-9b13-1d31697de163
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269665244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.2269665244
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.1970538190
Short name T396
Test name
Test status
Simulation time 2013425916 ps
CPU time 6.02 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:27 PM PST 24
Peak memory 201424 kb
Host smart-f18578aa-871d-4212-8338-978a80f63c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970538190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.1970538190
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2205116495
Short name T730
Test name
Test status
Simulation time 3172732959 ps
CPU time 2.2 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:22 PM PST 24
Peak memory 201484 kb
Host smart-b7402fcf-0aba-4f03-ad9f-1867053cd1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205116495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.2
205116495
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.2502253480
Short name T20
Test name
Test status
Simulation time 134740341322 ps
CPU time 333.16 seconds
Started Feb 21 03:01:17 PM PST 24
Finished Feb 21 03:06:51 PM PST 24
Peak memory 201604 kb
Host smart-9052fdac-bdb3-423b-8455-514a4a753e25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502253480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.2502253480
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3180152310
Short name T70
Test name
Test status
Simulation time 22609193648 ps
CPU time 10.87 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:33 PM PST 24
Peak memory 201640 kb
Host smart-ef26866c-29db-4a70-8953-eaa8f35b6098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180152310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.3180152310
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1429254052
Short name T294
Test name
Test status
Simulation time 4021463938 ps
CPU time 5.71 seconds
Started Feb 21 03:01:14 PM PST 24
Finished Feb 21 03:01:21 PM PST 24
Peak memory 201444 kb
Host smart-ecfd93bf-116a-4ba8-a785-23ae5344a555
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429254052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.1429254052
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.2175711848
Short name T159
Test name
Test status
Simulation time 2848629403 ps
CPU time 7.97 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:29 PM PST 24
Peak memory 201428 kb
Host smart-3492e57c-96af-4428-8813-f11e7adf3c28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175711848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.2175711848
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1258481852
Short name T176
Test name
Test status
Simulation time 2612676728 ps
CPU time 6.68 seconds
Started Feb 21 03:01:30 PM PST 24
Finished Feb 21 03:01:37 PM PST 24
Peak memory 201372 kb
Host smart-8a1581e2-a225-4b5e-a21a-26b16861c456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258481852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1258481852
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2637629162
Short name T534
Test name
Test status
Simulation time 2443050291 ps
CPU time 7.51 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:22 PM PST 24
Peak memory 201412 kb
Host smart-a183a0bd-8118-45ec-a15d-af35f305aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637629162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2637629162
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3781772222
Short name T783
Test name
Test status
Simulation time 2229062343 ps
CPU time 2.19 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201432 kb
Host smart-9a665eaf-cbd1-48df-9883-f2c92452b08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781772222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.3781772222
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3497920387
Short name T558
Test name
Test status
Simulation time 2516607858 ps
CPU time 3.8 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201432 kb
Host smart-ed766f12-7c95-49f3-9288-7cc50262642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497920387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.3497920387
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.2349083227
Short name T736
Test name
Test status
Simulation time 2111262547 ps
CPU time 6.1 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201396 kb
Host smart-cf2f4045-073f-4460-8a0f-3674b4915b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349083227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.2349083227
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.1699828519
Short name T151
Test name
Test status
Simulation time 8358253448 ps
CPU time 11.48 seconds
Started Feb 21 03:01:30 PM PST 24
Finished Feb 21 03:01:42 PM PST 24
Peak memory 201376 kb
Host smart-72916e77-6e8d-4f0e-a70e-68d6844a2164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699828519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.1699828519
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2253353025
Short name T507
Test name
Test status
Simulation time 66819009606 ps
CPU time 93.18 seconds
Started Feb 21 03:01:15 PM PST 24
Finished Feb 21 03:02:48 PM PST 24
Peak memory 211504 kb
Host smart-01d326b7-0883-4912-bf87-ad50013a33f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253353025 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.2253353025
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3570435936
Short name T59
Test name
Test status
Simulation time 4072039209 ps
CPU time 5.65 seconds
Started Feb 21 03:01:30 PM PST 24
Finished Feb 21 03:01:36 PM PST 24
Peak memory 201404 kb
Host smart-44ec3674-73ce-4da8-b9e2-655396c9d920
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570435936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.3570435936
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.1364805212
Short name T155
Test name
Test status
Simulation time 2012626210 ps
CPU time 5.61 seconds
Started Feb 21 03:01:23 PM PST 24
Finished Feb 21 03:01:29 PM PST 24
Peak memory 201440 kb
Host smart-a3855cec-575b-4cd7-9c1e-23cbc821b6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364805212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.1364805212
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.2485575607
Short name T704
Test name
Test status
Simulation time 3069144233 ps
CPU time 8.25 seconds
Started Feb 21 03:01:19 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201532 kb
Host smart-9e95d090-a542-4334-8fa4-a69138ed02e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485575607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.2
485575607
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.3096618515
Short name T242
Test name
Test status
Simulation time 70049302747 ps
CPU time 192.55 seconds
Started Feb 21 03:01:16 PM PST 24
Finished Feb 21 03:04:30 PM PST 24
Peak memory 201596 kb
Host smart-141ea61c-0a84-4d1c-885a-2d144732a187
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096618515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.3096618515
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3342023961
Short name T734
Test name
Test status
Simulation time 1247539976577 ps
CPU time 1614.61 seconds
Started Feb 21 03:01:16 PM PST 24
Finished Feb 21 03:28:12 PM PST 24
Peak memory 201348 kb
Host smart-f308225b-a267-4cda-98fa-46b1c88664a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342023961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.3342023961
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.2299963475
Short name T614
Test name
Test status
Simulation time 3157727623 ps
CPU time 2.25 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:16 PM PST 24
Peak memory 201656 kb
Host smart-6feceaea-ef4d-416a-bfc0-e2befbb894ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299963475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.2299963475
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.556114609
Short name T142
Test name
Test status
Simulation time 2608922122 ps
CPU time 6.84 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:27 PM PST 24
Peak memory 201432 kb
Host smart-a89be2e4-a1c8-4975-b532-42bf559f17f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556114609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.556114609
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.304126086
Short name T448
Test name
Test status
Simulation time 2485440589 ps
CPU time 2.59 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201436 kb
Host smart-090fbbb8-2400-46f0-937a-c996e32836fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304126086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.304126086
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2490499137
Short name T374
Test name
Test status
Simulation time 2019444451 ps
CPU time 5.49 seconds
Started Feb 21 03:01:16 PM PST 24
Finished Feb 21 03:01:22 PM PST 24
Peak memory 201364 kb
Host smart-edf95786-44c7-4bfa-8c1e-768caa0c4ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490499137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2490499137
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.4081741982
Short name T699
Test name
Test status
Simulation time 2533692613 ps
CPU time 2.48 seconds
Started Feb 21 03:01:17 PM PST 24
Finished Feb 21 03:01:20 PM PST 24
Peak memory 201404 kb
Host smart-4d5847d5-41b8-4515-a670-e6e1821b49ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081741982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.4081741982
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1769736024
Short name T714
Test name
Test status
Simulation time 2116570176 ps
CPU time 3.48 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201372 kb
Host smart-d4eeedcc-be19-46df-b6e6-050c8aeb4762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769736024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1769736024
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.3730802234
Short name T467
Test name
Test status
Simulation time 7237122168 ps
CPU time 10.5 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201432 kb
Host smart-0e75e866-9759-4333-ab26-38c5a8ba8cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730802234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.3730802234
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2478539642
Short name T22
Test name
Test status
Simulation time 78538494138 ps
CPU time 106.4 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:03:08 PM PST 24
Peak memory 210028 kb
Host smart-a0868143-32c8-4940-a8ab-ce931967b951
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478539642 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2478539642
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.336111444
Short name T143
Test name
Test status
Simulation time 2050509312 ps
CPU time 1.42 seconds
Started Feb 21 03:01:13 PM PST 24
Finished Feb 21 03:01:15 PM PST 24
Peak memory 201448 kb
Host smart-7c005ba2-0139-41e4-ba4c-85d60b57c9b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336111444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_tes
t.336111444
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2282025111
Short name T649
Test name
Test status
Simulation time 3513001879 ps
CPU time 2.76 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201488 kb
Host smart-6e0d29f4-ef4a-4a41-b508-d2d722aa8326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282025111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.2
282025111
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.3013309156
Short name T331
Test name
Test status
Simulation time 108602488060 ps
CPU time 145.22 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:03:48 PM PST 24
Peak memory 201668 kb
Host smart-9175d1f7-8787-4808-b3bc-3a7a3359c311
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013309156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.3013309156
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3018215373
Short name T493
Test name
Test status
Simulation time 4432347195 ps
CPU time 13.07 seconds
Started Feb 21 03:01:19 PM PST 24
Finished Feb 21 03:01:33 PM PST 24
Peak memory 201424 kb
Host smart-928c137d-a9b2-4110-9db3-e0ed1845acd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018215373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.3018215373
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3434059813
Short name T538
Test name
Test status
Simulation time 2733154768 ps
CPU time 2.12 seconds
Started Feb 21 03:01:17 PM PST 24
Finished Feb 21 03:01:20 PM PST 24
Peak memory 201468 kb
Host smart-10ca19f0-b06d-45c0-abea-d02599635ed7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434059813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.3434059813
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2223012814
Short name T563
Test name
Test status
Simulation time 2638408191 ps
CPU time 2.38 seconds
Started Feb 21 03:01:19 PM PST 24
Finished Feb 21 03:01:22 PM PST 24
Peak memory 201448 kb
Host smart-af952862-05b6-4972-a39f-1ea85f3baa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223012814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.2223012814
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4014791070
Short name T61
Test name
Test status
Simulation time 2489726192 ps
CPU time 2.57 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201368 kb
Host smart-70324e16-88fc-426b-b806-ee717102d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014791070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.4014791070
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3694516556
Short name T479
Test name
Test status
Simulation time 2343217781 ps
CPU time 0.98 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201420 kb
Host smart-3b4595d8-1ab0-49c2-83ea-ba403b3c5c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694516556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3694516556
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3966801365
Short name T393
Test name
Test status
Simulation time 2531266996 ps
CPU time 2.48 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:22 PM PST 24
Peak memory 201416 kb
Host smart-84e3f5f1-a8d3-4038-85b6-217932555250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966801365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.3966801365
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.1205041668
Short name T548
Test name
Test status
Simulation time 2117370659 ps
CPU time 2.83 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201328 kb
Host smart-0ee64ff5-a52a-4ef8-89f5-7a1912844ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205041668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1205041668
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.4221126182
Short name T359
Test name
Test status
Simulation time 49143322134 ps
CPU time 57.01 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:02:17 PM PST 24
Peak memory 201580 kb
Host smart-4b6a0109-2156-4cc0-9847-dc6514a23a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221126182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.4221126182
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3308677036
Short name T215
Test name
Test status
Simulation time 35971721447 ps
CPU time 24.09 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:46 PM PST 24
Peak memory 218144 kb
Host smart-53bce831-5bdb-4cf0-98e4-b848bdc757c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308677036 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.3308677036
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.747024371
Short name T403
Test name
Test status
Simulation time 2073006477 ps
CPU time 1.15 seconds
Started Feb 21 03:01:26 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201432 kb
Host smart-16a50536-8f75-496b-af62-ac44416ce017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747024371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_tes
t.747024371
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.4171250470
Short name T47
Test name
Test status
Simulation time 3687388507 ps
CPU time 10.1 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201440 kb
Host smart-dd800306-c811-4e92-a839-cfd54c46f1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171250470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.4
171250470
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.2205342269
Short name T775
Test name
Test status
Simulation time 140848297172 ps
CPU time 66.16 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:02:27 PM PST 24
Peak memory 201652 kb
Host smart-8c62b95e-451b-46d8-a301-5df94243a95d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205342269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.2205342269
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2546058449
Short name T574
Test name
Test status
Simulation time 157909549696 ps
CPU time 401.18 seconds
Started Feb 21 03:01:19 PM PST 24
Finished Feb 21 03:08:01 PM PST 24
Peak memory 201588 kb
Host smart-ea2b7796-29f2-4bb7-9f37-97a23bcfb5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546058449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.2546058449
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3017551396
Short name T434
Test name
Test status
Simulation time 3516977287 ps
CPU time 5.45 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201396 kb
Host smart-96171c22-524c-4b00-85dc-2682f41ffb85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017551396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.3017551396
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.679659661
Short name T114
Test name
Test status
Simulation time 2610140868 ps
CPU time 6.47 seconds
Started Feb 21 03:01:19 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201412 kb
Host smart-cf182f5e-4ead-4b2b-bdd5-e596cb1159ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679659661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.679659661
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1874803774
Short name T659
Test name
Test status
Simulation time 2453075166 ps
CPU time 7.03 seconds
Started Feb 21 03:01:15 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201436 kb
Host smart-ddeb5b5c-89c8-4591-90e3-a8ba2da74493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874803774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.1874803774
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2650062469
Short name T402
Test name
Test status
Simulation time 2107412959 ps
CPU time 3.46 seconds
Started Feb 21 03:01:27 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201252 kb
Host smart-f2d33ff2-564f-4aaa-a06c-f5b9cf8eaf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650062469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.2650062469
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1045666393
Short name T410
Test name
Test status
Simulation time 2517069107 ps
CPU time 4.06 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201392 kb
Host smart-5b22f748-107b-40b3-8db8-0ed702e65165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045666393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1045666393
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.90678621
Short name T141
Test name
Test status
Simulation time 2123507344 ps
CPU time 3.05 seconds
Started Feb 21 03:01:19 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201348 kb
Host smart-e73187b7-e309-4f38-91f3-786967b3af7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90678621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.90678621
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3391005728
Short name T66
Test name
Test status
Simulation time 10639141525 ps
CPU time 26.11 seconds
Started Feb 21 03:01:18 PM PST 24
Finished Feb 21 03:01:45 PM PST 24
Peak memory 201428 kb
Host smart-9324f17c-611a-4d85-b213-eb503f979ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391005728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3391005728
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1264602775
Short name T218
Test name
Test status
Simulation time 40569481653 ps
CPU time 18.16 seconds
Started Feb 21 03:01:18 PM PST 24
Finished Feb 21 03:01:36 PM PST 24
Peak memory 209972 kb
Host smart-3f329a4e-3dac-49d3-9d86-e6655f8cb998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264602775 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.1264602775
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.487371339
Short name T125
Test name
Test status
Simulation time 7085749089 ps
CPU time 7.63 seconds
Started Feb 21 03:01:18 PM PST 24
Finished Feb 21 03:01:27 PM PST 24
Peak memory 201408 kb
Host smart-963798b1-cdbc-4fae-9598-7ade2805f21e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487371339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_ultra_low_pwr.487371339
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.85274586
Short name T206
Test name
Test status
Simulation time 2014127848 ps
CPU time 5.86 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:29 PM PST 24
Peak memory 201468 kb
Host smart-d0e7da74-ba58-43fe-a643-8ad7b923a05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85274586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test
.85274586
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2945686744
Short name T481
Test name
Test status
Simulation time 171583679332 ps
CPU time 168.77 seconds
Started Feb 21 03:01:33 PM PST 24
Finished Feb 21 03:04:22 PM PST 24
Peak memory 201488 kb
Host smart-499cd5b4-5c6b-4625-9737-4c6a367fb48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945686744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.2
945686744
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.3821287322
Short name T88
Test name
Test status
Simulation time 63805156588 ps
CPU time 12.53 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:35 PM PST 24
Peak memory 201696 kb
Host smart-67573b85-d54f-4bef-8d7c-16ac4cb5d24b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821287322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.3821287322
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3321745868
Short name T494
Test name
Test status
Simulation time 67112762498 ps
CPU time 9.89 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:30 PM PST 24
Peak memory 201616 kb
Host smart-43c01dba-c04f-480b-b261-70bee2176f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321745868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.3321745868
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.469444001
Short name T666
Test name
Test status
Simulation time 894891773328 ps
CPU time 478.36 seconds
Started Feb 21 03:01:26 PM PST 24
Finished Feb 21 03:09:25 PM PST 24
Peak memory 201412 kb
Host smart-354ac9f8-52fb-49c1-b539-15af4d9f15d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469444001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_ec_pwr_on_rst.469444001
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.4227679727
Short name T203
Test name
Test status
Simulation time 3456395168 ps
CPU time 7.19 seconds
Started Feb 21 03:01:17 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201400 kb
Host smart-d66cfddf-cafa-425d-81bb-7a78268712a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227679727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.4227679727
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1726325124
Short name T270
Test name
Test status
Simulation time 2608708782 ps
CPU time 7.44 seconds
Started Feb 21 03:01:29 PM PST 24
Finished Feb 21 03:01:37 PM PST 24
Peak memory 201468 kb
Host smart-de45c3ee-169f-473e-9e0a-ffe20b762fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726325124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1726325124
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1196448646
Short name T183
Test name
Test status
Simulation time 2460063245 ps
CPU time 7.78 seconds
Started Feb 21 03:01:26 PM PST 24
Finished Feb 21 03:01:34 PM PST 24
Peak memory 201412 kb
Host smart-ab09f7ed-a6f3-422f-966c-694f7ea6ee6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196448646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1196448646
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.35428102
Short name T397
Test name
Test status
Simulation time 2072154644 ps
CPU time 1.99 seconds
Started Feb 21 03:01:27 PM PST 24
Finished Feb 21 03:01:29 PM PST 24
Peak memory 201360 kb
Host smart-d606b461-81cd-4f68-b618-7bef31a03889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35428102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.35428102
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.356850561
Short name T510
Test name
Test status
Simulation time 2515201396 ps
CPU time 4.05 seconds
Started Feb 21 03:01:27 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201428 kb
Host smart-1045afab-1a35-48f2-80ed-826d093eef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356850561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.356850561
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.3116540629
Short name T366
Test name
Test status
Simulation time 2121298725 ps
CPU time 3.12 seconds
Started Feb 21 03:01:26 PM PST 24
Finished Feb 21 03:01:30 PM PST 24
Peak memory 201348 kb
Host smart-d2535743-70b4-4118-9037-27d25fbf1224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116540629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3116540629
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.1634591473
Short name T278
Test name
Test status
Simulation time 136155269129 ps
CPU time 357.55 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:07:18 PM PST 24
Peak memory 201584 kb
Host smart-d2e18053-ee30-47bb-914e-36eeb928909c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634591473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.1634591473
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.994662994
Short name T9
Test name
Test status
Simulation time 58445276688 ps
CPU time 128.68 seconds
Started Feb 21 03:01:16 PM PST 24
Finished Feb 21 03:03:26 PM PST 24
Peak memory 213704 kb
Host smart-197239c0-1e07-40b7-9563-5f8265ceeef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994662994 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.994662994
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1226077145
Short name T23
Test name
Test status
Simulation time 5506861588 ps
CPU time 1.59 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201428 kb
Host smart-8a0ef2ba-bb5e-46a1-a733-ec4add74d066
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226077145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.1226077145
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.2866685010
Short name T174
Test name
Test status
Simulation time 2021436224 ps
CPU time 3 seconds
Started Feb 21 03:01:25 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201448 kb
Host smart-77be0e43-8757-4327-be04-603033594a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866685010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.2866685010
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.620153962
Short name T272
Test name
Test status
Simulation time 3944774429 ps
CPU time 6.29 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201508 kb
Host smart-6b6c2217-bfcc-4e9d-8849-42fd5552ac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620153962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.620153962
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.2527867407
Short name T325
Test name
Test status
Simulation time 82043135096 ps
CPU time 14.96 seconds
Started Feb 21 03:01:15 PM PST 24
Finished Feb 21 03:01:30 PM PST 24
Peak memory 201628 kb
Host smart-3b2cdf70-94ba-4e6b-afc0-1f0e6bcde5f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527867407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.2527867407
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.1368310113
Short name T615
Test name
Test status
Simulation time 3405076454 ps
CPU time 8.66 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201388 kb
Host smart-054a9b5f-fddd-481a-b8ec-d6f010eede13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368310113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.1368310113
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3229228337
Short name T644
Test name
Test status
Simulation time 2625865831 ps
CPU time 2.5 seconds
Started Feb 21 03:01:23 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201456 kb
Host smart-9d7c2631-25f6-4d50-b453-c1dd97ae8862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229228337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3229228337
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.157630919
Short name T452
Test name
Test status
Simulation time 2472533897 ps
CPU time 7.85 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201428 kb
Host smart-7aaa18c6-f07c-422e-9267-4355812dac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157630919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.157630919
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2110579957
Short name T451
Test name
Test status
Simulation time 2147788416 ps
CPU time 6.01 seconds
Started Feb 21 03:01:16 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201384 kb
Host smart-fad788e5-92b4-499a-b781-2b06bcb987ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110579957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2110579957
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.105512759
Short name T550
Test name
Test status
Simulation time 2513563197 ps
CPU time 7 seconds
Started Feb 21 03:01:20 PM PST 24
Finished Feb 21 03:01:27 PM PST 24
Peak memory 201428 kb
Host smart-cca91af3-daaf-4744-b486-5ba43c07ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105512759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.105512759
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.3797134808
Short name T367
Test name
Test status
Simulation time 2111741103 ps
CPU time 6.47 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201364 kb
Host smart-3f16a9a8-8ffd-42c1-8ef0-fe7365df58b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797134808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.3797134808
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.2595223449
Short name T163
Test name
Test status
Simulation time 98287162605 ps
CPU time 219.97 seconds
Started Feb 21 03:01:19 PM PST 24
Finished Feb 21 03:04:59 PM PST 24
Peak memory 201596 kb
Host smart-50bddaf0-fa90-4496-819e-49bacb786e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595223449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.2595223449
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3064997230
Short name T219
Test name
Test status
Simulation time 35682881007 ps
CPU time 40.17 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:02:03 PM PST 24
Peak memory 210020 kb
Host smart-7b7e3a98-2b6e-4cd3-830d-d8442e5a4f9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064997230 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.3064997230
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.256497934
Short name T753
Test name
Test status
Simulation time 2015755687 ps
CPU time 6.29 seconds
Started Feb 21 03:01:26 PM PST 24
Finished Feb 21 03:01:33 PM PST 24
Peak memory 201448 kb
Host smart-4216d6a5-47de-495a-a26c-7ad59bf39766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256497934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_tes
t.256497934
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.802416580
Short name T745
Test name
Test status
Simulation time 3399387589 ps
CPU time 2.76 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201472 kb
Host smart-c8b9c6de-b9bd-4ff5-ab7c-2ddedc987915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802416580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.802416580
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.3753623312
Short name T235
Test name
Test status
Simulation time 126795220785 ps
CPU time 50.68 seconds
Started Feb 21 03:01:25 PM PST 24
Finished Feb 21 03:02:17 PM PST 24
Peak memory 201608 kb
Host smart-3b52e08b-c6f0-4b70-af38-8faddb1b7492
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753623312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.3753623312
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2014956084
Short name T778
Test name
Test status
Simulation time 4161922780 ps
CPU time 11.04 seconds
Started Feb 21 03:01:30 PM PST 24
Finished Feb 21 03:01:41 PM PST 24
Peak memory 201416 kb
Host smart-afe25e87-fe72-4261-a6eb-858292a370b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014956084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.2014956084
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.1431010560
Short name T697
Test name
Test status
Simulation time 4333825972 ps
CPU time 8.03 seconds
Started Feb 21 03:01:18 PM PST 24
Finished Feb 21 03:01:27 PM PST 24
Peak memory 201460 kb
Host smart-b85564ca-962b-49b6-826a-1e38008bdd07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431010560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.1431010560
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2838194110
Short name T722
Test name
Test status
Simulation time 2616482967 ps
CPU time 4.32 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:26 PM PST 24
Peak memory 201480 kb
Host smart-9a9a2f47-cda2-43c5-90b8-3872944f87ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838194110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.2838194110
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2870423165
Short name T153
Test name
Test status
Simulation time 2473734555 ps
CPU time 2.49 seconds
Started Feb 21 03:01:45 PM PST 24
Finished Feb 21 03:01:48 PM PST 24
Peak memory 201420 kb
Host smart-1919c822-5af9-413a-b679-df6d68afbf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870423165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.2870423165
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2249240978
Short name T595
Test name
Test status
Simulation time 2183476085 ps
CPU time 2.53 seconds
Started Feb 21 03:01:45 PM PST 24
Finished Feb 21 03:01:48 PM PST 24
Peak memory 201444 kb
Host smart-cf64dbdc-91e8-4937-95a8-8c388b918708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249240978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2249240978
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2303850917
Short name T425
Test name
Test status
Simulation time 2508421298 ps
CPU time 6.8 seconds
Started Feb 21 03:01:23 PM PST 24
Finished Feb 21 03:01:30 PM PST 24
Peak memory 201432 kb
Host smart-e18ec6d6-b0d4-4b01-93f6-faa94e4474cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303850917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2303850917
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.2230257802
Short name T446
Test name
Test status
Simulation time 2111669552 ps
CPU time 6.13 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201360 kb
Host smart-15c48764-7f99-4508-b358-231b712b15b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230257802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2230257802
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.1106712549
Short name T737
Test name
Test status
Simulation time 8801412124 ps
CPU time 1.69 seconds
Started Feb 21 03:01:26 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201428 kb
Host smart-6e7f73e2-85c2-4a16-8b11-52c7722c5bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106712549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.1106712549
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1462981007
Short name T485
Test name
Test status
Simulation time 9001751477 ps
CPU time 2.28 seconds
Started Feb 21 03:01:25 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201452 kb
Host smart-12afbccd-a7d4-4380-905c-0d2586f3851e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462981007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.1462981007
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.3058777886
Short name T636
Test name
Test status
Simulation time 2018120117 ps
CPU time 3.33 seconds
Started Feb 21 03:01:19 PM PST 24
Finished Feb 21 03:01:23 PM PST 24
Peak memory 201444 kb
Host smart-cd06e43d-77cd-468e-9375-2b7466cf7d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058777886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.3058777886
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2790784977
Short name T708
Test name
Test status
Simulation time 3563789134 ps
CPU time 1.96 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201504 kb
Host smart-cb7f3915-a232-4934-ae5f-fee4792d950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790784977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.2
790784977
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.3057106828
Short name T185
Test name
Test status
Simulation time 30250406570 ps
CPU time 71.38 seconds
Started Feb 21 03:01:26 PM PST 24
Finished Feb 21 03:02:38 PM PST 24
Peak memory 201608 kb
Host smart-03f6e06b-4ff7-4eaf-b904-1be27aae1534
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057106828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.3057106828
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3335751307
Short name T703
Test name
Test status
Simulation time 3256680772 ps
CPU time 2.86 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201492 kb
Host smart-5289883f-cd75-4b7c-9a6a-6d02b87d51bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335751307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.3335751307
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1783131394
Short name T781
Test name
Test status
Simulation time 2524852538 ps
CPU time 2.26 seconds
Started Feb 21 03:01:30 PM PST 24
Finished Feb 21 03:01:32 PM PST 24
Peak memory 201416 kb
Host smart-e497d881-0621-494d-aa0f-6da0eb048442
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783131394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.1783131394
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.379604120
Short name T640
Test name
Test status
Simulation time 2635730674 ps
CPU time 2.19 seconds
Started Feb 21 03:01:25 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201432 kb
Host smart-f3892064-fd6f-42b1-bdb5-0e96d03d1d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379604120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.379604120
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1259165658
Short name T386
Test name
Test status
Simulation time 2458458112 ps
CPU time 6.38 seconds
Started Feb 21 03:01:40 PM PST 24
Finished Feb 21 03:01:47 PM PST 24
Peak memory 201432 kb
Host smart-708c14a0-2624-4c6d-b56f-c5b2696d67e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259165658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.1259165658
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.75762807
Short name T175
Test name
Test status
Simulation time 2052273439 ps
CPU time 1.92 seconds
Started Feb 21 03:01:46 PM PST 24
Finished Feb 21 03:01:48 PM PST 24
Peak memory 201368 kb
Host smart-28523762-7200-495c-83cd-7d2ab5187d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75762807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.75762807
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4222432806
Short name T400
Test name
Test status
Simulation time 2507678484 ps
CPU time 7.01 seconds
Started Feb 21 03:01:29 PM PST 24
Finished Feb 21 03:01:36 PM PST 24
Peak memory 201368 kb
Host smart-f03a501f-8c4a-4e93-8481-5936ad08ed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222432806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.4222432806
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.483251742
Short name T604
Test name
Test status
Simulation time 2121730935 ps
CPU time 3.36 seconds
Started Feb 21 03:01:27 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201368 kb
Host smart-cbf92e36-e8ee-43ea-b031-487b3ea2e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483251742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.483251742
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.294876285
Short name T101
Test name
Test status
Simulation time 16489775637 ps
CPU time 9.96 seconds
Started Feb 21 03:01:45 PM PST 24
Finished Feb 21 03:01:55 PM PST 24
Peak memory 201464 kb
Host smart-0424eb41-5ae6-4fc3-abc5-d97e4c32bc83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294876285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_st
ress_all.294876285
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4289346381
Short name T6
Test name
Test status
Simulation time 205375643743 ps
CPU time 32.05 seconds
Started Feb 21 03:01:23 PM PST 24
Finished Feb 21 03:01:55 PM PST 24
Peak memory 217640 kb
Host smart-e4d6c922-5926-45a9-a7a3-e106f290d5e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289346381 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.4289346381
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3110466624
Short name T120
Test name
Test status
Simulation time 13368941579 ps
CPU time 2.36 seconds
Started Feb 21 03:01:27 PM PST 24
Finished Feb 21 03:01:29 PM PST 24
Peak memory 201324 kb
Host smart-588a8764-f79f-4054-a297-dd5b8e117e65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110466624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.3110466624
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.1509162043
Short name T198
Test name
Test status
Simulation time 2014102167 ps
CPU time 6.13 seconds
Started Feb 21 03:01:39 PM PST 24
Finished Feb 21 03:01:46 PM PST 24
Peak memory 201448 kb
Host smart-43bad3a5-87db-4d12-baf0-e2603e897efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509162043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.1509162043
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.867137170
Short name T530
Test name
Test status
Simulation time 3233085254 ps
CPU time 2.64 seconds
Started Feb 21 03:01:27 PM PST 24
Finished Feb 21 03:01:30 PM PST 24
Peak memory 201536 kb
Host smart-b8120a07-4655-4923-955a-d94b166b1b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867137170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.867137170
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3690493940
Short name T655
Test name
Test status
Simulation time 100565774097 ps
CPU time 132.04 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:03:34 PM PST 24
Peak memory 201664 kb
Host smart-8ae50245-5fc4-4d6e-a4e8-98865be3f877
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690493940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.3690493940
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2258238119
Short name T771
Test name
Test status
Simulation time 4522345983 ps
CPU time 1.33 seconds
Started Feb 21 03:01:25 PM PST 24
Finished Feb 21 03:01:27 PM PST 24
Peak memory 201416 kb
Host smart-6ec66ced-3b14-4a37-b82c-686fed70c666
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258238119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.2258238119
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.2730974773
Short name T221
Test name
Test status
Simulation time 3826215480 ps
CPU time 1.67 seconds
Started Feb 21 03:01:27 PM PST 24
Finished Feb 21 03:01:29 PM PST 24
Peak memory 201436 kb
Host smart-36421169-a889-4c19-b00d-4fab8540e8da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730974773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.2730974773
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3738686336
Short name T668
Test name
Test status
Simulation time 2634795131 ps
CPU time 2.41 seconds
Started Feb 21 03:01:27 PM PST 24
Finished Feb 21 03:01:29 PM PST 24
Peak memory 201460 kb
Host smart-e11e481f-45a9-4cf1-a7be-5730eb48748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738686336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3738686336
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3459385435
Short name T28
Test name
Test status
Simulation time 2441984946 ps
CPU time 8.23 seconds
Started Feb 21 03:01:30 PM PST 24
Finished Feb 21 03:01:38 PM PST 24
Peak memory 201420 kb
Host smart-b3082a4e-2ca0-4149-a76d-ddc0c5db7e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459385435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3459385435
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.504991499
Short name T631
Test name
Test status
Simulation time 2216640004 ps
CPU time 2.1 seconds
Started Feb 21 03:01:26 PM PST 24
Finished Feb 21 03:01:28 PM PST 24
Peak memory 201460 kb
Host smart-5a738368-1e0e-40c7-9808-201e8d03c5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504991499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.504991499
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2937230057
Short name T692
Test name
Test status
Simulation time 2509732887 ps
CPU time 7.44 seconds
Started Feb 21 03:01:26 PM PST 24
Finished Feb 21 03:01:33 PM PST 24
Peak memory 201432 kb
Host smart-3c2bd758-fd83-4237-9537-dc186c4ec27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937230057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.2937230057
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.1564874376
Short name T628
Test name
Test status
Simulation time 2115078266 ps
CPU time 3.2 seconds
Started Feb 21 03:01:29 PM PST 24
Finished Feb 21 03:01:32 PM PST 24
Peak memory 201372 kb
Host smart-5a69c7b3-9888-4da1-98b6-8b744830e9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564874376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.1564874376
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.4097635415
Short name T165
Test name
Test status
Simulation time 15136131626 ps
CPU time 6.47 seconds
Started Feb 21 03:01:29 PM PST 24
Finished Feb 21 03:01:36 PM PST 24
Peak memory 201416 kb
Host smart-7d0e292d-16fa-4bb4-ad26-9f5866f15666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097635415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.4097635415
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3455026407
Short name T137
Test name
Test status
Simulation time 2215754420670 ps
CPU time 666.67 seconds
Started Feb 21 03:01:25 PM PST 24
Finished Feb 21 03:12:32 PM PST 24
Peak memory 201456 kb
Host smart-c4af4c56-464d-4a20-ab6c-b2cc57f4b2f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455026407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.3455026407
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.191274781
Short name T712
Test name
Test status
Simulation time 2016511577 ps
CPU time 5.46 seconds
Started Feb 21 03:01:40 PM PST 24
Finished Feb 21 03:01:46 PM PST 24
Peak memory 200772 kb
Host smart-d6e2f61c-16b5-4c0b-8f91-eec9692ddd2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191274781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_tes
t.191274781
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3229967663
Short name T110
Test name
Test status
Simulation time 3536660596 ps
CPU time 5.01 seconds
Started Feb 21 03:01:48 PM PST 24
Finished Feb 21 03:01:53 PM PST 24
Peak memory 201448 kb
Host smart-e91bc8bc-5552-422e-b3b3-9bc5b89567fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229967663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.3
229967663
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.173616312
Short name T160
Test name
Test status
Simulation time 168686359812 ps
CPU time 110.95 seconds
Started Feb 21 03:01:46 PM PST 24
Finished Feb 21 03:03:38 PM PST 24
Peak memory 201528 kb
Host smart-b93ca7dd-9560-46a2-a1ee-73da168d61d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173616312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_combo_detect.173616312
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2865398914
Short name T428
Test name
Test status
Simulation time 3345821917 ps
CPU time 8.84 seconds
Started Feb 21 03:01:22 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201424 kb
Host smart-22eed235-4993-46c7-9e15-bdaa68f29746
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865398914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.2865398914
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2242899652
Short name T637
Test name
Test status
Simulation time 3612491874 ps
CPU time 8.63 seconds
Started Feb 21 03:01:35 PM PST 24
Finished Feb 21 03:01:44 PM PST 24
Peak memory 201424 kb
Host smart-76fcd2d0-5159-4576-9cc8-49b271d86081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242899652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.2242899652
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1286319621
Short name T115
Test name
Test status
Simulation time 2626515209 ps
CPU time 2.54 seconds
Started Feb 21 03:01:30 PM PST 24
Finished Feb 21 03:01:33 PM PST 24
Peak memory 201452 kb
Host smart-90ac8746-c622-4f00-8a6c-328e3d996c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286319621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.1286319621
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3767266093
Short name T756
Test name
Test status
Simulation time 2497828580 ps
CPU time 2.3 seconds
Started Feb 21 03:01:21 PM PST 24
Finished Feb 21 03:01:24 PM PST 24
Peak memory 201428 kb
Host smart-e8660048-7e1c-4d3b-b179-72817ce2fc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767266093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3767266093
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.2272541942
Short name T546
Test name
Test status
Simulation time 2226751090 ps
CPU time 5.57 seconds
Started Feb 21 03:01:27 PM PST 24
Finished Feb 21 03:01:33 PM PST 24
Peak memory 201460 kb
Host smart-be274935-783f-432c-ac91-54de5ae99a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272541942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.2272541942
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2652956266
Short name T689
Test name
Test status
Simulation time 2520307291 ps
CPU time 5.04 seconds
Started Feb 21 03:01:25 PM PST 24
Finished Feb 21 03:01:30 PM PST 24
Peak memory 201460 kb
Host smart-06c40c4a-2a8d-4e44-891b-3b793708374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652956266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2652956266
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.1090597154
Short name T618
Test name
Test status
Simulation time 2133784558 ps
CPU time 1.93 seconds
Started Feb 21 03:01:29 PM PST 24
Finished Feb 21 03:01:31 PM PST 24
Peak memory 201280 kb
Host smart-a68f83a0-8c8e-41ee-88c4-7a704c86f4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090597154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.1090597154
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.2529703399
Short name T293
Test name
Test status
Simulation time 6917495893 ps
CPU time 18.8 seconds
Started Feb 21 03:01:37 PM PST 24
Finished Feb 21 03:01:57 PM PST 24
Peak memory 201428 kb
Host smart-373a534a-df54-4cce-af16-ed48a9698bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529703399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.2529703399
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.398387505
Short name T275
Test name
Test status
Simulation time 28702082996 ps
CPU time 78.37 seconds
Started Feb 21 03:01:44 PM PST 24
Finished Feb 21 03:03:04 PM PST 24
Peak memory 209992 kb
Host smart-c24ccb8d-f60e-4561-9e5b-681942301603
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398387505 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.398387505
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.365165380
Short name T709
Test name
Test status
Simulation time 6160373119 ps
CPU time 2.12 seconds
Started Feb 21 03:01:50 PM PST 24
Finished Feb 21 03:01:53 PM PST 24
Peak memory 201404 kb
Host smart-8bb26a68-eb63-4532-8b00-a012537b079a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365165380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ultra_low_pwr.365165380
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.662618381
Short name T571
Test name
Test status
Simulation time 2034094445 ps
CPU time 2.08 seconds
Started Feb 21 02:59:46 PM PST 24
Finished Feb 21 02:59:49 PM PST 24
Peak memory 201616 kb
Host smart-b4730b62-dfe9-43fa-8f1b-49bb713d355d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662618381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test
.662618381
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3042973704
Short name T603
Test name
Test status
Simulation time 3332092422 ps
CPU time 9.55 seconds
Started Feb 21 03:00:13 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201476 kb
Host smart-e989a9cb-fc5a-4d88-bb19-118954ccdf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042973704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.3042973704
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.329983979
Short name T327
Test name
Test status
Simulation time 99767881719 ps
CPU time 125.74 seconds
Started Feb 21 02:59:48 PM PST 24
Finished Feb 21 03:01:55 PM PST 24
Peak memory 201576 kb
Host smart-fa1cb212-67ef-4096-b0f1-470ed7a173eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329983979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_combo_detect.329983979
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1091663725
Short name T536
Test name
Test status
Simulation time 3357571614 ps
CPU time 9.78 seconds
Started Feb 21 02:59:52 PM PST 24
Finished Feb 21 03:00:02 PM PST 24
Peak memory 201404 kb
Host smart-0196a6f2-c99a-4024-b69a-8fc2e73a28d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091663725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.1091663725
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.38568915
Short name T559
Test name
Test status
Simulation time 2569466251 ps
CPU time 2.07 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:10 PM PST 24
Peak memory 201400 kb
Host smart-37f357d3-c4d9-4241-bd78-3f0f0e131579
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38568915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_
edge_detect.38568915
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2691324515
Short name T365
Test name
Test status
Simulation time 2610507522 ps
CPU time 7.51 seconds
Started Feb 21 03:00:10 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201408 kb
Host smart-61383934-f413-4f1d-ac05-3507ff825581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691324515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.2691324515
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1361026807
Short name T199
Test name
Test status
Simulation time 2434349998 ps
CPU time 6.63 seconds
Started Feb 21 03:00:26 PM PST 24
Finished Feb 21 03:00:33 PM PST 24
Peak memory 201436 kb
Host smart-de762009-dffc-40b1-836c-e2cd73fb0df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361026807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1361026807
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1462613322
Short name T524
Test name
Test status
Simulation time 2279268082 ps
CPU time 1.16 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:30 PM PST 24
Peak memory 201436 kb
Host smart-0bbf0623-5cd0-42fd-9199-0c1ce952552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462613322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.1462613322
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1424755288
Short name T223
Test name
Test status
Simulation time 2521749453 ps
CPU time 3.49 seconds
Started Feb 21 03:00:28 PM PST 24
Finished Feb 21 03:00:33 PM PST 24
Peak memory 201440 kb
Host smart-f7179770-64d0-4484-8b2b-5f8af0db8e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424755288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1424755288
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.393920090
Short name T663
Test name
Test status
Simulation time 2127548754 ps
CPU time 1.9 seconds
Started Feb 21 03:00:26 PM PST 24
Finished Feb 21 03:00:28 PM PST 24
Peak memory 201376 kb
Host smart-d47d81c8-ee63-4956-8bd0-08233ff27127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393920090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.393920090
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.317101573
Short name T553
Test name
Test status
Simulation time 15139360444 ps
CPU time 40.02 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:57 PM PST 24
Peak memory 201412 kb
Host smart-f712c101-a427-40d5-8eb0-b0054bdc9aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317101573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_str
ess_all.317101573
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2870982401
Short name T517
Test name
Test status
Simulation time 5792151238 ps
CPU time 8.36 seconds
Started Feb 21 03:00:09 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201620 kb
Host smart-29fc4a8d-e13e-4f28-b8f9-da2d0426a482
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870982401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.2870982401
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1541269550
Short name T519
Test name
Test status
Simulation time 28085479600 ps
CPU time 39 seconds
Started Feb 21 03:01:41 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 201636 kb
Host smart-da47f386-9fd8-42a5-a094-85e192f97e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541269550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.1541269550
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3437734213
Short name T201
Test name
Test status
Simulation time 74186674135 ps
CPU time 72.49 seconds
Started Feb 21 03:01:38 PM PST 24
Finished Feb 21 03:02:51 PM PST 24
Peak memory 201688 kb
Host smart-ce6d968c-4586-41b4-91b4-e2f58d8f4540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437734213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.3437734213
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.212940739
Short name T705
Test name
Test status
Simulation time 20836545800 ps
CPU time 26.3 seconds
Started Feb 21 03:01:38 PM PST 24
Finished Feb 21 03:02:05 PM PST 24
Peak memory 201608 kb
Host smart-e5a0304d-2c60-4c50-944c-159f37301360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212940739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_wi
th_pre_cond.212940739
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2371558320
Short name T504
Test name
Test status
Simulation time 27330915415 ps
CPU time 71.6 seconds
Started Feb 21 03:01:34 PM PST 24
Finished Feb 21 03:02:46 PM PST 24
Peak memory 201488 kb
Host smart-bbe6d469-a8ea-4e03-8941-15b31ffb52d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371558320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.2371558320
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1242894647
Short name T675
Test name
Test status
Simulation time 77518087492 ps
CPU time 50.24 seconds
Started Feb 21 03:01:39 PM PST 24
Finished Feb 21 03:02:29 PM PST 24
Peak memory 201708 kb
Host smart-5c94281f-6235-46a4-ab7a-460fdd81de64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242894647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.1242894647
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2468179662
Short name T404
Test name
Test status
Simulation time 26084457148 ps
CPU time 72.77 seconds
Started Feb 21 03:01:48 PM PST 24
Finished Feb 21 03:03:02 PM PST 24
Peak memory 201656 kb
Host smart-50e6b811-ec2b-4309-b981-164cd233cdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468179662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.2468179662
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.745773930
Short name T436
Test name
Test status
Simulation time 74297228755 ps
CPU time 199.96 seconds
Started Feb 21 03:01:36 PM PST 24
Finished Feb 21 03:04:56 PM PST 24
Peak memory 201624 kb
Host smart-23bc714b-900c-4e90-a280-d8923b03cf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745773930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_wi
th_pre_cond.745773930
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.206545020
Short name T582
Test name
Test status
Simulation time 2011346927 ps
CPU time 6.26 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:18 PM PST 24
Peak memory 201448 kb
Host smart-deeb2a85-3c13-4e08-9260-11891bab120e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206545020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test
.206545020
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.289813472
Short name T273
Test name
Test status
Simulation time 3462059965 ps
CPU time 9.92 seconds
Started Feb 21 02:59:55 PM PST 24
Finished Feb 21 03:00:07 PM PST 24
Peak memory 201548 kb
Host smart-9fea7f42-9004-4b89-8e03-f8969632cca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289813472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.289813472
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1459539838
Short name T297
Test name
Test status
Simulation time 78728393605 ps
CPU time 110.54 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:02:02 PM PST 24
Peak memory 201584 kb
Host smart-dbbc48d3-3709-4350-8562-435897d3b3d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459539838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.1459539838
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2212953297
Short name T718
Test name
Test status
Simulation time 2818006259 ps
CPU time 2.34 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:11 PM PST 24
Peak memory 201400 kb
Host smart-b6dfa3c6-675c-434b-8cc3-4208650e2a87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212953297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2212953297
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1661302093
Short name T209
Test name
Test status
Simulation time 4582973306 ps
CPU time 9.3 seconds
Started Feb 21 02:59:42 PM PST 24
Finished Feb 21 02:59:52 PM PST 24
Peak memory 201488 kb
Host smart-ab444fe9-6f9d-4e67-9f2e-449ac8e6aaf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661302093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1661302093
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1363018187
Short name T480
Test name
Test status
Simulation time 2638403708 ps
CPU time 2.01 seconds
Started Feb 21 02:59:57 PM PST 24
Finished Feb 21 03:00:00 PM PST 24
Peak memory 201388 kb
Host smart-7eef76d7-0edd-4fa6-a349-8bc18bfc337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363018187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.1363018187
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1001267864
Short name T627
Test name
Test status
Simulation time 2481700171 ps
CPU time 3.64 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:27 PM PST 24
Peak memory 201424 kb
Host smart-b6567038-c953-4a68-8e60-36b670921684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001267864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1001267864
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3145054663
Short name T372
Test name
Test status
Simulation time 2259433418 ps
CPU time 6.54 seconds
Started Feb 21 03:00:12 PM PST 24
Finished Feb 21 03:00:19 PM PST 24
Peak memory 201416 kb
Host smart-18e32f0d-2959-4e5f-895f-d4f265004e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145054663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3145054663
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3445753795
Short name T590
Test name
Test status
Simulation time 2554441716 ps
CPU time 1.41 seconds
Started Feb 21 03:00:23 PM PST 24
Finished Feb 21 03:00:25 PM PST 24
Peak memory 201428 kb
Host smart-0c639048-fbbc-4632-b08f-7eebe2fa0086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445753795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.3445753795
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.1547857417
Short name T458
Test name
Test status
Simulation time 2115355017 ps
CPU time 3.27 seconds
Started Feb 21 02:59:50 PM PST 24
Finished Feb 21 02:59:54 PM PST 24
Peak memory 201328 kb
Host smart-e292e907-ac4f-45e6-9f34-4dcc4b47eda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547857417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.1547857417
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1977131610
Short name T761
Test name
Test status
Simulation time 56816517532 ps
CPU time 37.52 seconds
Started Feb 21 03:00:09 PM PST 24
Finished Feb 21 03:00:47 PM PST 24
Peak memory 201536 kb
Host smart-9d0583b0-7d53-41f8-8a08-a5442ccccda7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977131610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1977131610
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1672548651
Short name T136
Test name
Test status
Simulation time 8797679305 ps
CPU time 9.24 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:58 PM PST 24
Peak memory 201324 kb
Host smart-528fc46b-d505-4a9e-9254-e4bc93b7497a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672548651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.1672548651
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4265064706
Short name T727
Test name
Test status
Simulation time 75689971919 ps
CPU time 50.39 seconds
Started Feb 21 03:01:41 PM PST 24
Finished Feb 21 03:02:32 PM PST 24
Peak memory 201660 kb
Host smart-4ecfeb7d-0c47-4058-9f2b-e3c1447d5717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265064706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.4265064706
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1690675338
Short name T652
Test name
Test status
Simulation time 24581513909 ps
CPU time 63.8 seconds
Started Feb 21 03:01:36 PM PST 24
Finished Feb 21 03:02:41 PM PST 24
Peak memory 201624 kb
Host smart-8d3e09b5-23e9-4545-bf00-193c648141a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690675338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.1690675338
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3620187627
Short name T693
Test name
Test status
Simulation time 66406496314 ps
CPU time 190.03 seconds
Started Feb 21 03:01:41 PM PST 24
Finished Feb 21 03:04:52 PM PST 24
Peak memory 201636 kb
Host smart-93505d28-381d-4352-94a1-d6b4a12f8537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620187627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3620187627
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1275927470
Short name T724
Test name
Test status
Simulation time 110557317159 ps
CPU time 278.73 seconds
Started Feb 21 03:01:37 PM PST 24
Finished Feb 21 03:06:17 PM PST 24
Peak memory 201608 kb
Host smart-1921d4df-400a-4fb6-8e68-4588c2b42016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275927470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.1275927470
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2915202020
Short name T608
Test name
Test status
Simulation time 24844557898 ps
CPU time 17.04 seconds
Started Feb 21 03:01:38 PM PST 24
Finished Feb 21 03:01:55 PM PST 24
Peak memory 201608 kb
Host smart-2a22f7f2-e794-4344-b1a0-c9fdeb9b970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915202020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.2915202020
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.634542471
Short name T593
Test name
Test status
Simulation time 2040220884 ps
CPU time 1.9 seconds
Started Feb 21 02:59:43 PM PST 24
Finished Feb 21 02:59:45 PM PST 24
Peak memory 201448 kb
Host smart-23eb4b90-1e29-478c-aa57-949f45f54057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634542471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test
.634542471
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2545218398
Short name T513
Test name
Test status
Simulation time 3866836183 ps
CPU time 10.76 seconds
Started Feb 21 02:59:47 PM PST 24
Finished Feb 21 02:59:58 PM PST 24
Peak memory 201488 kb
Host smart-881241e6-1b46-42e2-8fbc-5884617239c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545218398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.2545218398
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.4234740022
Short name T748
Test name
Test status
Simulation time 33193707474 ps
CPU time 46.01 seconds
Started Feb 21 02:59:58 PM PST 24
Finished Feb 21 03:00:45 PM PST 24
Peak memory 201596 kb
Host smart-cb7dd5c6-b2fa-4f5c-a3c8-821883aee504
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234740022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.4234740022
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1986469844
Short name T333
Test name
Test status
Simulation time 71166293321 ps
CPU time 108.83 seconds
Started Feb 21 03:00:11 PM PST 24
Finished Feb 21 03:02:01 PM PST 24
Peak memory 201688 kb
Host smart-a8060f25-3b04-4469-bc3f-bd7f7574d65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986469844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.1986469844
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.646439190
Short name T104
Test name
Test status
Simulation time 3160575300 ps
CPU time 8.58 seconds
Started Feb 21 02:59:56 PM PST 24
Finished Feb 21 03:00:06 PM PST 24
Peak memory 201124 kb
Host smart-79c5e89f-b9f4-4f24-a6e6-b709899e710e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646439190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ec_pwr_on_rst.646439190
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.4268743993
Short name T182
Test name
Test status
Simulation time 4285005671 ps
CPU time 6.02 seconds
Started Feb 21 02:59:50 PM PST 24
Finished Feb 21 02:59:56 PM PST 24
Peak memory 201388 kb
Host smart-b5baf625-abb1-4224-9822-fc5119187316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268743993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.4268743993
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1433103766
Short name T376
Test name
Test status
Simulation time 2623671039 ps
CPU time 2.48 seconds
Started Feb 21 02:59:41 PM PST 24
Finished Feb 21 02:59:44 PM PST 24
Peak memory 201436 kb
Host smart-11cb5848-c2b2-43f4-8b13-c393270fd9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433103766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.1433103766
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1497734323
Short name T532
Test name
Test status
Simulation time 2476612753 ps
CPU time 2.61 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:52 PM PST 24
Peak memory 201432 kb
Host smart-128b9ef4-6abb-4dca-a52c-ae4ff971d05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497734323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.1497734323
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1092399818
Short name T169
Test name
Test status
Simulation time 2134364603 ps
CPU time 5.93 seconds
Started Feb 21 02:59:44 PM PST 24
Finished Feb 21 02:59:50 PM PST 24
Peak memory 201316 kb
Host smart-1341d44a-b11a-4def-a69c-4204460f6654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092399818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1092399818
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2675375493
Short name T204
Test name
Test status
Simulation time 2513736306 ps
CPU time 6.93 seconds
Started Feb 21 02:59:55 PM PST 24
Finished Feb 21 03:00:03 PM PST 24
Peak memory 201476 kb
Host smart-cef91c04-8f69-400b-944c-cfbd2268ba3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675375493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2675375493
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.170177054
Short name T300
Test name
Test status
Simulation time 2129809171 ps
CPU time 1.96 seconds
Started Feb 21 02:59:57 PM PST 24
Finished Feb 21 03:00:00 PM PST 24
Peak memory 201324 kb
Host smart-56b3eab1-65c2-4f36-accb-837ff89b3c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170177054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.170177054
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.1626695976
Short name T323
Test name
Test status
Simulation time 103296433292 ps
CPU time 262.53 seconds
Started Feb 21 03:00:17 PM PST 24
Finished Feb 21 03:04:42 PM PST 24
Peak memory 201668 kb
Host smart-2451c7de-de11-41f0-bfe9-6441d3b88679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626695976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.1626695976
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2449942729
Short name T46
Test name
Test status
Simulation time 44007146732 ps
CPU time 107.53 seconds
Started Feb 21 03:01:41 PM PST 24
Finished Feb 21 03:03:29 PM PST 24
Peak memory 201628 kb
Host smart-3596590f-7254-42c9-888f-2380ba8e87c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449942729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2449942729
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.765185320
Short name T68
Test name
Test status
Simulation time 26345272127 ps
CPU time 20.87 seconds
Started Feb 21 03:01:37 PM PST 24
Finished Feb 21 03:01:58 PM PST 24
Peak memory 201656 kb
Host smart-bcffb87c-7bfd-4dc6-a272-ce475142350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765185320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_wi
th_pre_cond.765185320
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2486531619
Short name T228
Test name
Test status
Simulation time 57373483241 ps
CPU time 9.78 seconds
Started Feb 21 03:01:49 PM PST 24
Finished Feb 21 03:01:59 PM PST 24
Peak memory 201712 kb
Host smart-af9a6216-e475-451a-900c-1284642e272a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486531619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.2486531619
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2428687419
Short name T80
Test name
Test status
Simulation time 120790227110 ps
CPU time 159.48 seconds
Started Feb 21 03:01:36 PM PST 24
Finished Feb 21 03:04:15 PM PST 24
Peak memory 201656 kb
Host smart-f19429ec-da0a-4ac1-9f4a-c4d0dc726679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428687419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.2428687419
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1957141199
Short name T322
Test name
Test status
Simulation time 72584496305 ps
CPU time 45.08 seconds
Started Feb 21 03:01:40 PM PST 24
Finished Feb 21 03:02:26 PM PST 24
Peak memory 201672 kb
Host smart-1a6d3c9a-a49e-47da-ad6a-63cdfccc6896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957141199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.1957141199
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.858482472
Short name T556
Test name
Test status
Simulation time 27844234772 ps
CPU time 26.54 seconds
Started Feb 21 03:01:39 PM PST 24
Finished Feb 21 03:02:06 PM PST 24
Peak memory 201612 kb
Host smart-0c473b3c-3256-4a75-a2f0-2d85685fdcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858482472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_wi
th_pre_cond.858482472
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1743329694
Short name T577
Test name
Test status
Simulation time 57612692944 ps
CPU time 149.65 seconds
Started Feb 21 03:01:58 PM PST 24
Finished Feb 21 03:04:29 PM PST 24
Peak memory 201656 kb
Host smart-223dd845-c98e-486b-a1f4-147c49cb9f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743329694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.1743329694
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3407672798
Short name T579
Test name
Test status
Simulation time 29333085261 ps
CPU time 73.21 seconds
Started Feb 21 03:01:36 PM PST 24
Finished Feb 21 03:02:49 PM PST 24
Peak memory 201588 kb
Host smart-4d5f074b-51d1-4d9f-a484-0d9d18a50ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407672798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.3407672798
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.3924879834
Short name T545
Test name
Test status
Simulation time 2015771524 ps
CPU time 5.41 seconds
Started Feb 21 02:59:45 PM PST 24
Finished Feb 21 02:59:50 PM PST 24
Peak memory 201444 kb
Host smart-f819925b-fc0f-4b01-8ae7-58b7523e8744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924879834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.3924879834
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2078777634
Short name T658
Test name
Test status
Simulation time 3219231916 ps
CPU time 2.76 seconds
Started Feb 21 02:59:47 PM PST 24
Finished Feb 21 02:59:50 PM PST 24
Peak memory 201756 kb
Host smart-b944251e-1aa5-4d45-9268-b03495aa23dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078777634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2078777634
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.1833039963
Short name T237
Test name
Test status
Simulation time 110068488676 ps
CPU time 260.48 seconds
Started Feb 21 02:59:55 PM PST 24
Finished Feb 21 03:04:17 PM PST 24
Peak memory 201664 kb
Host smart-51f25946-32a3-4b41-a2f7-899e47c6b944
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833039963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.1833039963
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3907400574
Short name T42
Test name
Test status
Simulation time 25609630447 ps
CPU time 16.58 seconds
Started Feb 21 03:00:16 PM PST 24
Finished Feb 21 03:00:35 PM PST 24
Peak memory 201676 kb
Host smart-b6bc867d-3878-4f12-a0bf-7ed39b06d940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907400574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.3907400574
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.919609453
Short name T58
Test name
Test status
Simulation time 5207617972 ps
CPU time 14.64 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:00:23 PM PST 24
Peak memory 201432 kb
Host smart-2842a426-4bea-4bb5-a02e-bbbaf1123820
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919609453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ec_pwr_on_rst.919609453
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2434972191
Short name T217
Test name
Test status
Simulation time 4268655633 ps
CPU time 4.41 seconds
Started Feb 21 03:00:05 PM PST 24
Finished Feb 21 03:00:10 PM PST 24
Peak memory 201420 kb
Host smart-78c6bf62-8ead-4f8f-bb41-f5ec997038f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434972191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.2434972191
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1255000341
Short name T543
Test name
Test status
Simulation time 2626991618 ps
CPU time 2.26 seconds
Started Feb 21 03:00:15 PM PST 24
Finished Feb 21 03:00:18 PM PST 24
Peak memory 201420 kb
Host smart-a5209dc1-70bb-4d2a-9e23-0ed886e8ff8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255000341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1255000341
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1206822713
Short name T267
Test name
Test status
Simulation time 2451391417 ps
CPU time 4.6 seconds
Started Feb 21 02:59:41 PM PST 24
Finished Feb 21 02:59:46 PM PST 24
Peak memory 201428 kb
Host smart-f84b677f-6fa1-44c1-a81c-8f1b5165a5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206822713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1206822713
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3653990136
Short name T726
Test name
Test status
Simulation time 2061470285 ps
CPU time 1.8 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:21 PM PST 24
Peak memory 201332 kb
Host smart-ecb04a42-a071-45fc-bd69-5023963f104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653990136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3653990136
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1040486057
Short name T475
Test name
Test status
Simulation time 2509854149 ps
CPU time 6.79 seconds
Started Feb 21 02:59:48 PM PST 24
Finished Feb 21 02:59:56 PM PST 24
Peak memory 201428 kb
Host smart-b5b4afee-6622-4fe3-a076-b9148e0643b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040486057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1040486057
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.291566402
Short name T777
Test name
Test status
Simulation time 2112884428 ps
CPU time 6.48 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:56 PM PST 24
Peak memory 201320 kb
Host smart-e3e8d4ad-8edf-46e7-a947-02f50bf72381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291566402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.291566402
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.3867734706
Short name T568
Test name
Test status
Simulation time 57485607844 ps
CPU time 21 seconds
Started Feb 21 02:59:54 PM PST 24
Finished Feb 21 03:00:16 PM PST 24
Peak memory 201332 kb
Host smart-6d5c23b8-9a22-4541-bbf4-996bd3d13ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867734706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.3867734706
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3699704709
Short name T44
Test name
Test status
Simulation time 205931301218 ps
CPU time 132.25 seconds
Started Feb 21 03:01:38 PM PST 24
Finished Feb 21 03:03:51 PM PST 24
Peak memory 201684 kb
Host smart-6fac5558-acef-47ef-9dd6-57cf5528f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699704709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.3699704709
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.4143427552
Short name T657
Test name
Test status
Simulation time 24096507800 ps
CPU time 17.23 seconds
Started Feb 21 03:01:35 PM PST 24
Finished Feb 21 03:01:53 PM PST 24
Peak memory 201624 kb
Host smart-6c993b81-058e-48bf-b12b-0432f44eb2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143427552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.4143427552
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3791014191
Short name T719
Test name
Test status
Simulation time 56642777071 ps
CPU time 39.43 seconds
Started Feb 21 03:01:41 PM PST 24
Finished Feb 21 03:02:21 PM PST 24
Peak memory 201600 kb
Host smart-50f1322d-d58e-443c-9134-0eb5defd3f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791014191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.3791014191
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1339845501
Short name T715
Test name
Test status
Simulation time 71237613811 ps
CPU time 21.48 seconds
Started Feb 21 03:01:38 PM PST 24
Finished Feb 21 03:02:00 PM PST 24
Peak memory 201672 kb
Host smart-1c024349-8c9f-47dc-8785-e41a04afb71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339845501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.1339845501
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2078323608
Short name T346
Test name
Test status
Simulation time 153212434842 ps
CPU time 438.83 seconds
Started Feb 21 03:01:53 PM PST 24
Finished Feb 21 03:09:12 PM PST 24
Peak memory 201708 kb
Host smart-134d3652-735d-494b-94bb-5a6219d53c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078323608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.2078323608
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.29118784
Short name T687
Test name
Test status
Simulation time 81922017764 ps
CPU time 176.52 seconds
Started Feb 21 03:01:51 PM PST 24
Finished Feb 21 03:04:48 PM PST 24
Peak memory 201592 kb
Host smart-cd9a471a-2e21-4918-ac01-8289d5663898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29118784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_wit
h_pre_cond.29118784
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1739555852
Short name T49
Test name
Test status
Simulation time 28085263092 ps
CPU time 38.14 seconds
Started Feb 21 03:01:51 PM PST 24
Finished Feb 21 03:02:29 PM PST 24
Peak memory 201588 kb
Host smart-4f864143-7a20-4856-97ba-b6b7292f5f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739555852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.1739555852
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2200136090
Short name T509
Test name
Test status
Simulation time 28582342220 ps
CPU time 72.82 seconds
Started Feb 21 03:01:50 PM PST 24
Finished Feb 21 03:03:04 PM PST 24
Peak memory 201572 kb
Host smart-41b066f0-b0d0-4fcf-b9f0-4e3753f3be6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200136090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.2200136090
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.1224727108
Short name T711
Test name
Test status
Simulation time 2033875609 ps
CPU time 2.03 seconds
Started Feb 21 03:00:19 PM PST 24
Finished Feb 21 03:00:22 PM PST 24
Peak memory 201428 kb
Host smart-4e7e1bc3-ce7c-4e63-857e-f4d4ceaa0dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224727108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.1224727108
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3243296180
Short name T706
Test name
Test status
Simulation time 4004004098 ps
CPU time 1.92 seconds
Started Feb 21 02:59:48 PM PST 24
Finished Feb 21 02:59:51 PM PST 24
Peak memory 201500 kb
Host smart-966d5e9e-8f79-49c7-a4ea-271f95e03cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243296180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3243296180
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3649876309
Short name T12
Test name
Test status
Simulation time 36996224731 ps
CPU time 89.82 seconds
Started Feb 21 02:59:54 PM PST 24
Finished Feb 21 03:01:25 PM PST 24
Peak memory 201460 kb
Host smart-ce702a0e-37a5-4ffa-9afe-efa62f6fbed3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649876309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3649876309
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3892001153
Short name T744
Test name
Test status
Simulation time 96336400493 ps
CPU time 265.01 seconds
Started Feb 21 03:00:05 PM PST 24
Finished Feb 21 03:04:30 PM PST 24
Peak memory 201860 kb
Host smart-a4c3714d-765e-40f7-929f-8a7e92f7df0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892001153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.3892001153
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1234306962
Short name T135
Test name
Test status
Simulation time 3408290890 ps
CPU time 8.96 seconds
Started Feb 21 03:00:06 PM PST 24
Finished Feb 21 03:00:15 PM PST 24
Peak memory 201420 kb
Host smart-240a3e15-2a28-4f66-9813-032d04822eaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234306962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.1234306962
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.423235023
Short name T694
Test name
Test status
Simulation time 2620240283 ps
CPU time 4.23 seconds
Started Feb 21 02:59:44 PM PST 24
Finished Feb 21 02:59:49 PM PST 24
Peak memory 201440 kb
Host smart-8afef0d1-4e95-492b-96f9-5f9aa8b56bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423235023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.423235023
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1173178804
Short name T483
Test name
Test status
Simulation time 2477075114 ps
CPU time 7.2 seconds
Started Feb 21 03:00:00 PM PST 24
Finished Feb 21 03:00:07 PM PST 24
Peak memory 201428 kb
Host smart-dde958ce-d202-40e9-8696-477a0dbc2fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173178804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1173178804
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3939757758
Short name T472
Test name
Test status
Simulation time 2052874330 ps
CPU time 2.02 seconds
Started Feb 21 02:59:56 PM PST 24
Finished Feb 21 03:00:00 PM PST 24
Peak memory 201384 kb
Host smart-3b6e8fc0-627c-46ea-af8e-2770403f6f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939757758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.3939757758
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.874837405
Short name T64
Test name
Test status
Simulation time 2529662909 ps
CPU time 2.4 seconds
Started Feb 21 02:59:44 PM PST 24
Finished Feb 21 02:59:46 PM PST 24
Peak memory 201380 kb
Host smart-e9e53e1e-4efe-49e5-9c4e-b0d2fb3b42be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874837405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.874837405
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.3482606462
Short name T518
Test name
Test status
Simulation time 2143154550 ps
CPU time 1.71 seconds
Started Feb 21 02:59:49 PM PST 24
Finished Feb 21 02:59:51 PM PST 24
Peak memory 201372 kb
Host smart-f3d379c1-edaf-4330-a23f-42ef248fb330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482606462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3482606462
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.3538922790
Short name T740
Test name
Test status
Simulation time 109040109762 ps
CPU time 66.44 seconds
Started Feb 21 03:00:08 PM PST 24
Finished Feb 21 03:01:15 PM PST 24
Peak memory 201840 kb
Host smart-c6ea1485-890d-4065-8ebf-c13dc1b8ceb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538922790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.3538922790
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1564167049
Short name T220
Test name
Test status
Simulation time 225388265859 ps
CPU time 51.13 seconds
Started Feb 21 02:59:51 PM PST 24
Finished Feb 21 03:00:42 PM PST 24
Peak memory 210072 kb
Host smart-cbe92b87-519c-4f92-85af-afe1b56963e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564167049 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1564167049
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.420274841
Short name T525
Test name
Test status
Simulation time 25330294039 ps
CPU time 61.89 seconds
Started Feb 21 03:01:50 PM PST 24
Finished Feb 21 03:02:52 PM PST 24
Peak memory 201708 kb
Host smart-538e321b-bcaf-4cca-ad40-76a3dff796f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420274841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_wi
th_pre_cond.420274841
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1355826185
Short name T178
Test name
Test status
Simulation time 52332255385 ps
CPU time 41.22 seconds
Started Feb 21 03:01:50 PM PST 24
Finished Feb 21 03:02:32 PM PST 24
Peak memory 201604 kb
Host smart-92733449-57fc-4862-b77b-23169f3234ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355826185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.1355826185
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2341933784
Short name T612
Test name
Test status
Simulation time 36793048844 ps
CPU time 94.65 seconds
Started Feb 21 03:01:52 PM PST 24
Finished Feb 21 03:03:28 PM PST 24
Peak memory 201660 kb
Host smart-8be2a67c-a24d-4811-9814-a591fcf6222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341933784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.2341933784
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3821988837
Short name T238
Test name
Test status
Simulation time 32677219437 ps
CPU time 27.99 seconds
Started Feb 21 03:02:02 PM PST 24
Finished Feb 21 03:02:30 PM PST 24
Peak memory 201648 kb
Host smart-30aed453-3cd6-4999-9ad0-d16ed980dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821988837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.3821988837
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3538058117
Short name T570
Test name
Test status
Simulation time 31492419492 ps
CPU time 15.36 seconds
Started Feb 21 03:01:53 PM PST 24
Finished Feb 21 03:02:09 PM PST 24
Peak memory 201624 kb
Host smart-2f9be4fe-6778-4ca7-a19e-0a1b029691c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538058117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.3538058117
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3790927212
Short name T624
Test name
Test status
Simulation time 88269829764 ps
CPU time 229.94 seconds
Started Feb 21 03:01:53 PM PST 24
Finished Feb 21 03:05:43 PM PST 24
Peak memory 201704 kb
Host smart-a22d1430-9f77-4d63-9b68-79ed0bc468bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790927212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3790927212
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1765004250
Short name T343
Test name
Test status
Simulation time 73044574643 ps
CPU time 61.09 seconds
Started Feb 21 03:01:51 PM PST 24
Finished Feb 21 03:02:53 PM PST 24
Peak memory 201556 kb
Host smart-c8795a78-dc74-483f-bf7b-91fd8aa35bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765004250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.1765004250
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1350183124
Short name T415
Test name
Test status
Simulation time 35239906578 ps
CPU time 24.82 seconds
Started Feb 21 03:01:51 PM PST 24
Finished Feb 21 03:02:17 PM PST 24
Peak memory 201584 kb
Host smart-f96eec58-ca91-4d3c-947a-7cf7e66bfcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350183124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.1350183124
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1334823970
Short name T91
Test name
Test status
Simulation time 27831879367 ps
CPU time 67.5 seconds
Started Feb 21 03:01:51 PM PST 24
Finished Feb 21 03:02:59 PM PST 24
Peak memory 201684 kb
Host smart-53d907b6-35c7-40ac-9261-9563dbb3c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334823970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.1334823970
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.230076266
Short name T486
Test name
Test status
Simulation time 26611661649 ps
CPU time 18.64 seconds
Started Feb 21 03:01:54 PM PST 24
Finished Feb 21 03:02:13 PM PST 24
Peak memory 201680 kb
Host smart-f4451098-2f42-4e4c-98f7-2c5fb272da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230076266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_wi
th_pre_cond.230076266
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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