Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_ec_rst_ctl_cdc

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	88.73			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	2086541	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	2074	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2086541	0	0
T1	904145	1007	0	0
T2	766221	7962	0	0
T3	0	12341	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3637	0	0
T7	0	12941	0	0
T9	0	8514	0	0
T10	0	1671	0	0
T12	0	17691	0	0
T14	0	6101	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6773	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2074	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T12	0	11	0	0
T14	0	4	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1240201	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1078	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1240201	0	0
T8	60320	905	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	813	0	0
T14	0	1486	0	0
T17	0	364	0	0
T22	0	1935	0	0
T34	0	5277	0	0
T35	0	5252	0	0
T36	0	5265	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T56	0	3957	0	0
T58	0	997	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1078	0	0
T8	60320	2	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	2	0	0
T14	0	1	0	0
T17	0	2	0	0
T22	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T36	0	3	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T56	0	2	0	0
T58	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1249341	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1094	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1249341	0	0
T8	60320	901	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	785	0	0
T14	0	1475	0	0
T17	0	350	0	0
T22	0	1933	0	0
T34	0	5271	0	0
T35	0	5237	0	0
T36	0	5237	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T56	0	3953	0	0
T58	0	991	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1094	0	0
T8	60320	2	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	2	0	0
T14	0	1	0	0
T17	0	2	0	0
T22	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T36	0	3	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T56	0	2	0	0
T58	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1211637	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1056	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1211637	0	0
T8	60320	897	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	772	0	0
T14	0	1458	0	0
T17	0	333	0	0
T22	0	1931	0	0
T34	0	5265	0	0
T35	0	5207	0	0
T36	0	5215	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T56	0	3949	0	0
T58	0	979	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1056	0	0
T8	60320	2	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	2	0	0
T14	0	1	0	0
T17	0	2	0	0
T22	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T36	0	3	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T56	0	2	0	0
T58	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T13,T14
1	-	Covered	T8,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1234640	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1057	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1234640	0	0
T8	60320	905	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	813	0	0
T14	0	2985	0	0
T17	0	431	0	0
T22	0	3876	0	0
T34	0	3358	0	0
T35	0	3343	0	0
T36	0	3827	0	0
T37	0	2487	0	0
T38	0	1057	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1057	0	0
T8	60320	2	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	2	0	0
T14	0	2	0	0
T17	0	2	0	0
T22	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	6	0	0
T38	0	2	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T43,T44,T45
1	-	Covered	T8,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T8,T13,T14
1	0	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T8,T13,T14

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	602018	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	572	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	602018	0	0
T8	60320	514	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	450	0	0
T14	0	1461	0	0
T17	0	184	0	0
T22	0	1935	0	0
T34	0	1914	0	0
T35	0	1885	0	0
T36	0	1889	0	0
T37	0	1109	0	0
T38	0	600	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	572	0	0
T8	60320	1	0	0
T9	867942	0	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	0	0	0
T13	56518	1	0	0
T14	0	1	0	0
T17	0	1	0	0
T22	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T41	241424	0	0	0
T42	27208	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T21,T22,T56
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1179093	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1185	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1179093	0	0
T1	904145	970	0	0
T2	766221	4790	0	0
T3	0	19001	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	1393	0	0
T7	0	7107	0	0
T8	0	516	0	0
T9	0	5696	0	0
T10	0	746	0	0
T12	0	20276	0	0
T13	0	461	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1185	0	0
T1	904145	6	0	0
T2	766221	3	0	0
T3	0	11	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	2	0	0
T7	0	5	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	0	12	0	0
T13	0	1	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T39,T40

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T39,T40
1	1	Covered	T4,T39,T40

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T39,T40

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T39,T40
1	1	Covered	T4,T39,T40

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T39,T40
0	0	1	Covered	T4,T39,T40
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T39,T40
0	0	1	Covered	T4,T39,T40
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	3148345	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	3141	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	3148345	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T4	176434	26149	0	0
T5	346500	0	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T39	0	10540	0	0
T40	0	35776	0	0
T48	0	70777	0	0
T59	0	33165	0	0
T60	0	17756	0	0
T61	0	34208	0	0
T62	0	7942	0	0
T63	0	33696	0	0
T64	0	16501	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	3141	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T4	176434	20	0	0
T5	346500	0	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T39	0	20	0	0
T40	0	20	0	0
T48	0	40	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T26,T47

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T26,T47
1	1	Covered	T4,T26,T47

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T26,T47

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T26,T47
1	1	Covered	T4,T26,T47

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T26,T47
0	0	1	Covered	T4,T26,T47
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T26,T47
0	0	1	Covered	T4,T26,T47
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	5228115	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	5605	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5228115	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T4	176434	1403	0	0
T5	346500	0	0	0
T12	0	68040	0	0
T14	0	28564	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	9029	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T33	0	17476	0	0
T39	0	459	0	0
T40	0	1955	0	0
T41	0	32118	0	0
T47	0	33773	0	0
T65	0	8393	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5605	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T4	176434	1	0	0
T5	346500	0	0	0
T12	0	40	0	0
T14	0	17	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	20	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T33	0	20	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	20	0	0
T47	0	20	0	0
T65	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T26
1	1	Covered	T1,T4,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T26
1	1	Covered	T1,T4,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T26
0	0	1	Covered	T1,T4,T26
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T26
0	0	1	Covered	T1,T4,T26
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	6370732	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	6784	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	6370732	0	0
T1	904145	1156	0	0
T2	766221	8149	0	0
T3	0	12878	0	0
T4	176434	1409	0	0
T5	346500	0	0	0
T6	0	3996	0	0
T7	0	13264	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	9484	0	0
T27	50719	0	0	0
T28	482863	6916	0	0
T29	74995	0	0	0
T39	0	461	0	0
T47	0	33853	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	6784	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	1	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	20	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0
T39	0	1	0	0
T47	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T26,T47,T41

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T26,T47,T41
1	1	Covered	T26,T47,T41

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T26,T47,T41

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T26,T47,T41
1	1	Covered	T26,T47,T41

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T26,T47,T41
0	0	1	Covered	T26,T47,T41
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T26,T47,T41
0	0	1	Covered	T26,T47,T41
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	5142414	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	5463	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5142414	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	0	0	0
T8	60320	0	0	0
T12	0	68462	0	0
T14	0	28745	0	0
T18	0	14523	0	0
T21	0	8550	0	0
T26	68248	9247	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T33	0	17673	0	0
T41	0	32357	0	0
T47	245142	33813	0	0
T65	0	8599	0	0
T66	0	12833	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5463	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	0	0	0
T8	60320	0	0	0
T12	0	40	0	0
T14	0	17	0	0
T18	0	60	0	0
T21	0	60	0	0
T26	68248	20	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T33	0	20	0	0
T41	0	20	0	0
T47	245142	20	0	0
T65	0	20	0	0
T66	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T11,T14,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T11,T14,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T11,T14,T15
0	0	1	Covered	T11,T14,T15
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T11,T14,T15
0	0	1	Covered	T11,T14,T15
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1172718	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1042	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1172718	0	0
T11	118407	930	0	0
T12	143504	0	0	0
T13	56518	0	0	0
T14	813350	1489	0	0
T15	320376	1960	0	0
T16	280173	0	0	0
T17	0	215	0	0
T18	0	598	0	0
T19	0	1499	0	0
T20	0	477	0	0
T21	0	279	0	0
T22	0	1937	0	0
T23	0	1881	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1042	0	0
T11	118407	1	0	0
T12	143504	0	0	0
T13	56518	0	0	0
T14	813350	1	0	0
T15	320376	1	0	0
T16	280173	0	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	2087006	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	2093	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2087006	0	0
T1	904145	993	0	0
T2	766221	7952	0	0
T3	0	12277	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3599	0	0
T7	0	12923	0	0
T9	0	8461	0	0
T10	0	1667	0	0
T11	0	925	0	0
T12	0	17574	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6757	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2093	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	11	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T5,T48,T18

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T48,T18
1	1	Covered	T5,T48,T18

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T5,T48,T18

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T48,T18
1	1	Covered	T5,T48,T18

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T5,T48,T18
0	0	1	Covered	T5,T48,T18
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T5,T48,T18
0	0	1	Covered	T5,T48,T18
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1439073	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1319	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1439073	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T5	346500	7476	0	0
T6	311845	0	0	0
T18	0	619	0	0
T21	0	597	0	0
T22	0	5336	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T48	0	10989	0	0
T53	0	2248	0	0
T54	0	3900	0	0
T55	0	8607	0	0
T56	0	8409	0	0
T57	0	7916	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1319	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T5	346500	4	0	0
T6	311845	0	0	0
T18	0	3	0	0
T21	0	4	0	0
T22	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T48	0	6	0	0
T53	0	5	0	0
T54	0	5	0	0
T55	0	5	0	0
T56	0	5	0	0
T57	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T5,T48,T18

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T48,T18
1	1	Covered	T5,T48,T18

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T5,T48,T18

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T48,T18
1	1	Covered	T5,T48,T18

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T5,T48,T18
0	0	1	Covered	T5,T48,T18
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T5,T48,T18
0	0	1	Covered	T5,T48,T18
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1335161	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1196	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1335161	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T5	346500	5458	0	0
T6	311845	0	0	0
T18	0	599	0	0
T21	0	434	0	0
T22	0	5330	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T48	0	4974	0	0
T53	0	1366	0	0
T54	0	1452	0	0
T55	0	5242	0	0
T56	0	5433	0	0
T57	0	4444	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1196	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T5	346500	3	0	0
T6	311845	0	0	0
T18	0	3	0	0
T21	0	3	0	0
T22	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T48	0	3	0	0
T53	0	3	0	0
T54	0	2	0	0
T55	0	3	0	0
T56	0	3	0	0
T57	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	7646654	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	7301	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7646654	0	0
T2	766221	105627	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	123299	0	0
T8	60320	0	0	0
T9	867942	116556	0	0
T10	0	50026	0	0
T29	74995	0	0	0
T30	0	90917	0	0
T31	0	132212	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	113557	0	0
T68	0	81307	0	0
T69	0	85769	0	0
T70	0	119133	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7301	0	0
T2	766221	63	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	77	0	0
T8	60320	0	0	0
T9	867942	69	0	0
T10	0	58	0	0
T29	74995	0	0	0
T30	0	51	0	0
T31	0	79	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	68	0	0
T68	0	77	0	0
T69	0	51	0	0
T70	0	70	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	7579336	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	7340	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7579336	0	0
T2	766221	99600	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	131033	0	0
T8	60320	0	0	0
T9	867942	141302	0	0
T10	0	57551	0	0
T29	74995	0	0	0
T30	0	89761	0	0
T31	0	131854	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	113267	0	0
T68	0	71492	0	0
T69	0	85559	0	0
T70	0	107056	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7340	0	0
T2	766221	60	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	82	0	0
T8	60320	0	0	0
T9	867942	86	0	0
T10	0	66	0	0
T29	74995	0	0	0
T30	0	51	0	0
T31	0	79	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	68	0	0
T68	0	70	0	0
T69	0	51	0	0
T70	0	63	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	7312653	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	7170	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7312653	0	0
T2	766221	99330	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	103720	0	0
T8	60320	0	0	0
T9	867942	107431	0	0
T10	0	63754	0	0
T29	74995	0	0	0
T30	0	88761	0	0
T31	0	131496	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	95317	0	0
T68	0	62185	0	0
T69	0	85349	0	0
T70	0	105639	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7170	0	0
T2	766221	60	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	65	0	0
T8	60320	0	0	0
T9	867942	65	0	0
T10	0	74	0	0
T29	74995	0	0	0
T30	0	51	0	0
T31	0	79	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	58	0	0
T68	0	62	0	0
T69	0	51	0	0
T70	0	63	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	7432009	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	7293	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7432009	0	0
T2	766221	104876	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	135638	0	0
T8	60320	0	0	0
T9	867942	132981	0	0
T10	0	63446	0	0
T29	74995	0	0	0
T30	0	87680	0	0
T31	0	95461	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	93187	0	0
T68	0	84949	0	0
T69	0	85139	0	0
T70	0	115441	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7293	0	0
T2	766221	63	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	85	0	0
T8	60320	0	0	0
T9	867942	83	0	0
T10	0	74	0	0
T29	74995	0	0	0
T30	0	51	0	0
T31	0	57	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	57	0	0
T68	0	84	0	0
T69	0	51	0	0
T70	0	70	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1475707	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1326	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1475707	0	0
T2	766221	8152	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	13283	0	0
T8	60320	0	0	0
T9	867942	9520	0	0
T10	0	1747	0	0
T29	74995	0	0	0
T30	0	1434	0	0
T31	0	11028	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	4795	0	0
T68	0	5376	0	0
T69	0	1453	0	0
T70	0	7831	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1326	0	0
T2	766221	5	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	9	0	0
T8	60320	0	0	0
T9	867942	5	0	0
T10	0	2	0	0
T29	74995	0	0	0
T30	0	1	0	0
T31	0	7	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	3	0	0
T68	0	5	0	0
T69	0	1	0	0
T70	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1484219	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1353	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1484219	0	0
T2	766221	8102	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	13193	0	0
T8	60320	0	0	0
T9	867942	9236	0	0
T10	0	1727	0	0
T29	74995	0	0	0
T30	0	1379	0	0
T31	0	10958	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	4765	0	0
T68	0	5107	0	0
T69	0	1443	0	0
T70	0	7612	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1353	0	0
T2	766221	5	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	9	0	0
T8	60320	0	0	0
T9	867942	5	0	0
T10	0	2	0	0
T29	74995	0	0	0
T30	0	1	0	0
T31	0	7	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	3	0	0
T68	0	5	0	0
T69	0	1	0	0
T70	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1468061	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1334	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1468061	0	0
T2	766221	8052	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	13103	0	0
T8	60320	0	0	0
T9	867942	8960	0	0
T10	0	1707	0	0
T29	74995	0	0	0
T30	0	1330	0	0
T31	0	10888	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	4735	0	0
T68	0	4822	0	0
T69	0	1433	0	0
T70	0	7358	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1334	0	0
T2	766221	5	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	9	0	0
T8	60320	0	0	0
T9	867942	5	0	0
T10	0	2	0	0
T29	74995	0	0	0
T30	0	1	0	0
T31	0	7	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	3	0	0
T68	0	5	0	0
T69	0	1	0	0
T70	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T7,T9
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1495025	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1344	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1495025	0	0
T2	766221	8002	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	13013	0	0
T8	60320	0	0	0
T9	867942	8726	0	0
T10	0	1687	0	0
T29	74995	0	0	0
T30	0	1268	0	0
T31	0	10818	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	4705	0	0
T68	0	4580	0	0
T69	0	1423	0	0
T70	0	7070	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1344	0	0
T2	766221	5	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	9	0	0
T8	60320	0	0	0
T9	867942	5	0	0
T10	0	2	0	0
T29	74995	0	0	0
T30	0	1	0	0
T31	0	7	0	0
T39	76338	0	0	0
T40	242792	0	0	0
T47	245142	0	0	0
T67	0	3	0	0
T68	0	5	0	0
T69	0	1	0	0
T70	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	8336574	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	8049	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	8336574	0	0
T1	904145	1175	0	0
T2	766221	105723	0	0
T3	0	12942	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	4046	0	0
T7	0	123399	0	0
T9	0	117096	0	0
T10	0	50130	0	0
T12	0	19050	0	0
T14	0	4476	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6965	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	8049	0	0
T1	904145	7	0	0
T2	766221	63	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	77	0	0
T9	0	69	0	0
T10	0	58	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	8138867	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	7959	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	8138867	0	0
T1	904145	1161	0	0
T2	766221	99690	0	0
T3	0	12893	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	4006	0	0
T7	0	131143	0	0
T9	0	142038	0	0
T10	0	57671	0	0
T12	0	18965	0	0
T14	0	4445	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6949	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7959	0	0
T1	904145	7	0	0
T2	766221	60	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	82	0	0
T9	0	86	0	0
T10	0	66	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	7873928	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	7796	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7873928	0	0
T1	904145	1147	0	0
T2	766221	99420	0	0
T3	0	12840	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3977	0	0
T7	0	103796	0	0
T9	0	107945	0	0
T10	0	63890	0	0
T12	0	18843	0	0
T14	0	4416	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6933	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7796	0	0
T1	904145	7	0	0
T2	766221	60	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	65	0	0
T9	0	65	0	0
T10	0	74	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	7925786	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	7874	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7925786	0	0
T1	904145	1133	0	0
T2	766221	104972	0	0
T3	0	12795	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3941	0	0
T7	0	135754	0	0
T9	0	133733	0	0
T10	0	63582	0	0
T12	0	18726	0	0
T14	0	4383	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6917	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7874	0	0
T1	904145	7	0	0
T2	766221	63	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	85	0	0
T9	0	83	0	0
T10	0	74	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	2108576	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	2052	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2108576	0	0
T1	904145	1119	0	0
T2	766221	8132	0	0
T3	0	12740	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3910	0	0
T7	0	13247	0	0
T9	0	9412	0	0
T10	0	1739	0	0
T12	0	18625	0	0
T14	0	4365	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6901	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2052	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1990778	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1966	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1990778	0	0
T1	904145	1105	0	0
T2	766221	8082	0	0
T3	0	12694	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3864	0	0
T7	0	13157	0	0
T9	0	9138	0	0
T10	0	1719	0	0
T12	0	18490	0	0
T14	0	4329	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6885	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1966	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	2009613	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1972	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2009613	0	0
T1	904145	1091	0	0
T2	766221	8032	0	0
T3	0	12646	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3817	0	0
T7	0	13067	0	0
T9	0	8840	0	0
T10	0	1699	0	0
T12	0	18369	0	0
T14	0	4308	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6869	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1972	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1984759	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1951	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1984759	0	0
T1	904145	1077	0	0
T2	766221	7982	0	0
T3	0	12603	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3774	0	0
T7	0	12977	0	0
T9	0	8631	0	0
T10	0	1679	0	0
T12	0	18262	0	0
T14	0	4273	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6853	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1951	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	2074454	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	2042	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2074454	0	0
T1	904145	1063	0	0
T2	766221	8122	0	0
T3	0	12549	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3751	0	0
T7	0	13229	0	0
T9	0	9342	0	0
T10	0	1735	0	0
T12	0	18130	0	0
T14	0	4235	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6837	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2042	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	2005139	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1969	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2005139	0	0
T1	904145	1049	0	0
T2	766221	8072	0	0
T3	0	12500	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3717	0	0
T7	0	13139	0	0
T9	0	9078	0	0
T10	0	1715	0	0
T12	0	18025	0	0
T14	0	4211	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6821	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1969	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1985980	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1970	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1985980	0	0
T1	904145	1035	0	0
T2	766221	8022	0	0
T3	0	12433	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3699	0	0
T7	0	13049	0	0
T9	0	8798	0	0
T10	0	1695	0	0
T12	0	17910	0	0
T14	0	4189	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6805	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1970	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T28,T2
0	0	1	Covered	T1,T28,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1994743	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1980	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1994743	0	0
T1	904145	1021	0	0
T2	766221	7972	0	0
T3	0	12395	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	3669	0	0
T7	0	12959	0	0
T9	0	8561	0	0
T10	0	1675	0	0
T12	0	17795	0	0
T14	0	4150	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	6789	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1980	0	0
T1	904145	7	0	0
T2	766221	5	0	0
T3	0	7	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	5	0	0
T7	0	9	0	0
T9	0	5	0	0
T10	0	2	0	0
T12	0	11	0	0
T14	0	3	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	8	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1254870617	1105040	0	0
DstReqKnown_A	7397749	6586037	0	0
SrcAckBusyChk_A	1254870617	1126	0	0
SrcBusyKnown_A	1254870617	1252902916	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1105040	0	0
T1	904145	958	0	0
T2	766221	4783	0	0
T3	0	18903	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	1396	0	0
T7	0	7097	0	0
T9	0	5647	0	0
T10	0	744	0	0
T12	0	20134	0	0
T14	0	2950	0	0
T16	0	2843	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7397749	6586037	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1126	0	0
T1	904145	6	0	0
T2	766221	3	0	0
T3	0	11	0	0
T4	176434	0	0	0
T5	346500	0	0	0
T6	0	2	0	0
T7	0	5	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	0	12	0	0
T14	0	2	0	0
T16	0	7	0	0
T24	222367	0	0	0
T25	82845	0	0	0
T26	68248	0	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1252902916	0	0
T1	904145	902255	0	0
T2	766221	765303	0	0
T4	176434	176341	0	0
T5	346500	346414	0	0
T24	222367	222275	0	0
T25	82845	82793	0	0
T26	68248	68179	0	0
T27	50719	50627	0	0
T28	482863	482061	0	0
T29	74995	74934	0	0