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Module Instance : tb.dut.u_reg.u_key_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.76 100.00 88.73 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.61 100.00 94.44 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

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Module Instances:
tb.dut.u_reg.u_key_intr_status_cdc
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT11,T14,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT11,T14,T15
11CoveredT11,T14,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT11,T14,T15
10CoveredT11,T14,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT11,T14,T15
11CoveredT11,T14,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T5
10Not Covered
11CoveredT11,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T5
0 1 - Covered T11,T14,T15
0 0 1 Covered T11,T14,T15
0 0 0 Covered T1,T4,T5


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T5
0 1 - Covered T11,T14,T15
0 0 1 Covered T11,T14,T15
0 0 0 Covered T1,T4,T5


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1254870617 736955 0 0
DstReqKnown_A 7397749 6586037 0 0
SrcAckBusyChk_A 1254870617 704 0 0
SrcBusyKnown_A 1254870617 1252902916 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1254870617 736955 0 0
T11 118407 910 0 0
T12 143504 0 0 0
T13 56518 0 0 0
T14 813350 1467 0 0
T15 320376 5864 0 0
T16 280173 0 0 0
T17 0 196 0 0
T18 0 1471 0 0
T19 0 1494 0 0
T20 0 950 0 0
T21 0 269 0 0
T22 0 1934 0 0
T23 0 5629 0 0
T30 342723 0 0 0
T31 957516 0 0 0
T32 197091 0 0 0
T33 130868 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7397749 6586037 0 0
T1 20092 19652 0 0
T2 15963 15544 0 0
T4 496 96 0 0
T5 693 293 0 0
T24 449 49 0 0
T25 403 3 0 0
T26 505 105 0 0
T27 406 6 0 0
T28 20119 19686 0 0
T29 405 5 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1254870617 704 0 0
T11 118407 1 0 0
T12 143504 0 0 0
T13 56518 0 0 0
T14 813350 1 0 0
T15 320376 3 0 0
T16 280173 0 0 0
T17 0 1 0 0
T18 0 7 0 0
T19 0 1 0 0
T20 0 2 0 0
T21 0 2 0 0
T22 0 1 0 0
T23 0 3 0 0
T30 342723 0 0 0
T31 957516 0 0 0
T32 197091 0 0 0
T33 130868 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1254870617 1252902916 0 0
T1 904145 902255 0 0
T2 766221 765303 0 0
T4 176434 176341 0 0
T5 346500 346414 0 0
T24 222367 222275 0 0
T25 82845 82793 0 0
T26 68248 68179 0 0
T27 50719 50627 0 0
T28 482863 482061 0 0
T29 74995 74934 0 0

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