Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2192

1

T2

2

T3

40

T7

2

auto[1]

606

1

T2

13

T7

12

T8

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2181

1

T2

9

T3

27

T7

12

auto[1]

617

1

T2

6

T3

13

T7

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2197

1

T2

6

T3

40

T7

12

auto[1]

601

1

T2

9

T7

2

T8

10

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2109

1

T2

13

T3

34

T7

9

auto[1]

689

1

T2

2

T3

6

T7

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2487

1

T2

15

T3

34

T7

14

auto[1]

311

1

T3

6

T9

2

T52

7

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2553

1

T2

15

T3

40

T7

14

auto[1]

245

1

T66

7

T81

4

T242

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2517

1

T2

15

T3

28

T7

14

auto[1]

281

1

T3

12

T9

2

T111

12

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2503

1

T2

15

T3

40

T7

14

auto[1]

295

1

T9

1

T81

5

T202

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2628

1

T2

15

T3

33

T7

14

auto[1]

170

1

T3

7

T9

1

T111

6

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2040

1

T2

13

T3

34

T7

11

auto[1]

758

1

T2

2

T3

6

T7

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

827

1

T2

15

T7

14

T8

19

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

148

1

T60

12

T67

1

T202

24

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

38

1

T3

1

T257

2

T347

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T257

1

T348

6

T349

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

109

1

T81

5

T243

2

T115

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T350

5

T351

10

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

14

1

T9

1

T131

2

T352

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T353

2

T346

6

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

88

1

T3

4

T243

2

T354

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T3

4

T9

2

T111

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

31

1

T111

6

T242

3

T97

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T258

2

T355

2

T250

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T356

2

T351

2

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

90

1

T66

7

T115

6

T85

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T81

4

T131

3

T357

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

18

1

T96

3

T202

3

T358

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T242

1

T258

1

T359

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T360

5

T361

2

T362

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T136

1

T348

1

T342

12

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

24

1

T96

4

T85

1

T355

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T257

2

T357

3

T342

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T115

2

T363

2

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T244

3

T180

2

T345

8

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

95

1

T7

9

T111

6

T96

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

146

1

T3

4

T60

6

T96

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

71

1

T109

3

T66

7

T85

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

152

1

T8

12

T9

2

T111

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

96

1

T264

4

T261

4

T54

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

94

1

T18

6

T81

4

T84

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T7

3

T115

6

T355

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

79

1

T13

5

T60

6

T242

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

73

1

T2

7

T9

1

T297

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

80

1

T13

3

T260

7

T347

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

51

1

T297

2

T85

6

T341

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T208

5

T136

4

T253

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T333

2

T341

1

T246

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T2

2

T8

6

T264

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T254

1

T364

1

T365

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

98

1

T3

1

T10

2

T90

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

43

1

T2

6

T98

2

T355

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

78

1

T259

7

T260

5

T208

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T18

3

T264

2

T366

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T3

4

T18

8

T242

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T242

3

T354

2

T367

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

34

1

T16

3

T90

2

T43

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T90

2

T333

2

T334

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

80

1

T16

7

T18

4

T347

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T10

1

T368

4

T369

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T8

1

T67

1

T54

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T43

1

T81

5

T199

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T7

2

T261

1

T257

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T84

1

T370

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T371

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T118

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded