Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T26

8

T10

7

T34

10

auto[1]

1101

1

T26

12

T10

13

T34

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

523

1

T26

4

T10

5

T34

5

from_0to1

511

1

T26

4

T10

5

T34

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T26

12

T10

14

T34

10

auto[1]

1084

1

T26

8

T10

6

T34

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1039

1

T26

5

T10

11

T34

11

auto[1]

1129

1

T26

15

T10

9

T34

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T10

1

T34

1

T14

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T26

2

T65

1

T300

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T14

2

T79

1

T127

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T10

1

T79

1

T108

2

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T26

1

T10

1

T34

2

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T10

1

T14

1

T127

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T10

1

T14

2

T79

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T26

1

T10

1

T34

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T26

1

T10

1

T34

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T26

1

T10

2

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T34

1

T20

2

T22

3

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T127

1

T108

1

T300

3

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T65

1

T20

2

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T14

1

T127

1

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T26

1

T10

1

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T26

1

T34

2

T108

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1076

1

T26

10

T10

10

T34

9

auto[1]

1092

1

T26

10

T10

10

T34

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

544

1

T26

5

T10

6

T34

6

from_0to1

535

1

T26

5

T10

6

T34

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T26

9

T10

10

T34

9

auto[1]

1124

1

T26

11

T10

10

T34

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T26

11

T10

5

T34

14

auto[1]

1079

1

T26

9

T10

15

T34

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T10

1

T14

1

T65

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T26

1

T10

1

T34

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T34

3

T14

1

T127

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T26

2

T79

3

T127

2

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T26

1

T34

2

T79

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T10

1

T14

1

T65

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T34

2

T108

1

T300

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T26

1

T10

3

T79

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T26

1

T10

1

T34

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T26

1

T10

3

T127

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T34

1

T79

1

T65

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T79

1

T127

1

T300

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T26

2

T34

1

T127

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T34

1

T14

2

T108

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T14

1

T79

1

T127

3

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T26

1

T10

2

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T26

9

T10

9

T34

8

auto[1]

1128

1

T26

11

T10

11

T34

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T26

4

T10

5

T34

6

from_0to1

501

1

T26

5

T10

5

T34

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T26

11

T10

18

T34

9

auto[1]

1104

1

T26

9

T10

2

T34

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T26

12

T10

8

T34

8

auto[1]

1089

1

T26

8

T10

12

T34

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T26

1

T10

2

T14

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T10

2

T34

1

T14

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T34

1

T108

1

T300

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T26

1

T14

1

T79

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T26

2

T10

2

T34

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T14

1

T127

1

T65

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T127

1

T108

1

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T79

1

T127

1

T108

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T108

1

T65

3

T20

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T26

1

T10

1

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T26

1

T34

2

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T34

1

T79

1

T127

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T26

2

T10

1

T14

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T10

2

T127

1

T108

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T34

1

T79

1

T300

1

auto[1]

from_0to1

auto[1]

auto[1]

78

1

T26

1

T34

3

T14

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T26

13

T10

10

T34

14

auto[1]

1046

1

T26

7

T10

10

T34

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

542

1

T26

5

T10

4

T34

5

from_0to1

522

1

T26

5

T10

5

T34

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T26

8

T10

8

T34

11

auto[1]

1060

1

T26

12

T10

12

T34

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T26

10

T10

12

T34

6

auto[1]

1082

1

T26

10

T10

8

T34

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T34

1

T108

1

T300

2

auto[0]

from_1to0

auto[0]

auto[1]

85

1

T26

1

T10

1

T34

3

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T26

1

T65

1

T300

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T34

1

T14

2

T127

2

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T14

1

T79

2

T127

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T34

3

T14

1

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T26

2

T34

1

T14

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T10

2

T34

1

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T79

2

T65

2

T300

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T26

1

T10

1

T14

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T26

1

T10

2

T127

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T26

1

T14

2

T79

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T10

1

T300

1

T20

1

auto[1]

from_0to1

auto[0]

auto[1]

49

1

T26

1

T14

1

T300

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T26

1

T10

2

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T26

1

T14

1

T127

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T26

12

T10

11

T34

14

auto[1]

1039

1

T26

8

T10

9

T34

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T26

4

T10

5

T34

5

from_0to1

535

1

T26

4

T10

5

T34

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T26

9

T10

7

T34

6

auto[1]

1073

1

T26

11

T10

13

T34

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1070

1

T26

10

T10

12

T34

13

auto[1]

1098

1

T26

10

T10

8

T34

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T26

1

T34

1

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T26

1

T14

1

T79

3

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T26

1

T14

2

T127

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T10

1

T34

1

T127

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T26

1

T20

2

T22

3

auto[0]

from_0to1

auto[0]

auto[1]

77

1

T10

1

T14

1

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T10

1

T34

2

T14

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T26

1

T10

2

T34

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T34

1

T127

3

T20

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T10

1

T79

1

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T10

2

T34

1

T14

2

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T26

1

T10

1

T34

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T14

1

T127

1

T108

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T26

1

T79

2

T127

2

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T10

1

T14

3

T79

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T26

1

T22

2

T43

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T26

11

T10

9

T34

10

auto[1]

1082

1

T26

9

T10

11

T34

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

524

1

T26

6

T10

6

T34

5

from_0to1

520

1

T26

7

T10

5

T34

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T26

13

T10

8

T34

8

auto[1]

1082

1

T26

7

T10

12

T34

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T26

14

T10

10

T34

8

auto[1]

1062

1

T26

6

T10

10

T34

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T10

1

T79

1

T127

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T26

1

T34

2

T79

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T26

1

T10

1

T34

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T26

1

T14

1

T300

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T26

1

T79

1

T127

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T26

1

T10

1

T14

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T26

1

T34

2

T14

1

auto[0]

from_0to1

auto[1]

auto[1]

82

1

T10

2

T79

1

T300

2

auto[1]

from_1to0

auto[0]

auto[0]

81

1

T26

2

T14

1

T127

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T10

1

T79

1

T108

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T26

1

T34

2

T14

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T10

3

T127

1

T108

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T26

2

T10

2

T34

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T26

1

T14

1

T79

2

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T108

1

T65

1

T300

2

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T26

1

T34

2

T14

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T26

10

T10

9

T34

10

auto[1]

1104

1

T26

10

T10

11

T34

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

523

1

T26

5

T10

4

T34

5

from_0to1

503

1

T26

4

T10

4

T34

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T26

12

T10

8

T34

5

auto[1]

1086

1

T26

8

T10

12

T34

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T26

8

T10

9

T34

14

auto[1]

1070

1

T26

12

T10

11

T34

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T14

1

T79

2

T127

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T10

2

T34

1

T14

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T10

1

T34

3

T20

3

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T26

2

T14

1

T108

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T10

1

T127

2

T108

2

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T26

1

T79

1

T127

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T26

1

T34

1

T14

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T14

1

T20

2

T22

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T34

1

T79

2

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T26

2

T14

2

T79

1

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T127

1

T108

1

T300

2

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T26

1

T10

1

T108

4

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T26

1

T10

1

T14

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T26

1

T79

1

T127

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T10

1

T34

2

T14

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T10

1

T34

2

T14

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T26

10

T10

11

T34

7

auto[1]

1105

1

T26

10

T10

9

T34

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

525

1

T26

5

T10

4

T34

4

from_0to1

517

1

T26

5

T10

4

T34

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1076

1

T26

8

T10

12

T34

7

auto[1]

1092

1

T26

12

T10

8

T34

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114

1

T26

10

T10

9

T34

6

auto[1]

1054

1

T26

10

T10

11

T34

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T79

1

T108

1

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T26

1

T10

1

T108

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T34

2

T14

1

T300

3

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T26

2

T34

1

T300

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T26

1

T10

1

T14

2

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T26

1

T14

1

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T26

1

T10

1

T34

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T26

1

T10

1

T79

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T14

1

T79

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T10

1

T34

1

T127

3

auto[1]

from_1to0

auto[1]

auto[0]

90

1

T26

2

T14

1

T79

4

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T10

2

T14

1

T127

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T26

1

T14

1

T127

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T10

1

T34

1

T108

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T79

1

T108

1

T65

3

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T34

2

T79

2

T65

1