Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154546	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124547

1

T4

68

T5

9

T6

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143264	1			T4	53		T5	18		T6	42
values[0x0]	67659	1			T4	72		T1	5		T25	13
values[0x1]	68170	1			T4	69		T5	1		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

153757

1

T4

79

T5

10

T6

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	978	1			T2	2		T8	2		T9	16
valid_sources[0x01]	1457	1			T5	1		T2	3		T3	8
valid_sources[0x02]	1284	1			T2	3		T26	1		T8	4
valid_sources[0x03]	896	1			T2	2		T26	1		T7	1
valid_sources[0x04]	859	1			T2	2		T7	2		T32	2
valid_sources[0x05]	1027	1			T25	1		T7	1		T8	4
valid_sources[0x06]	973	1			T25	3		T2	2		T26	1
valid_sources[0x07]	934	1			T2	3		T8	2		T9	2
valid_sources[0x08]	960	1			T25	1		T2	7		T7	1
valid_sources[0x09]	791	1			T2	3		T7	1		T8	4
valid_sources[0x0a]	1848	1			T2	5		T26	1		T7	2
valid_sources[0x0b]	1195	1			T2	3		T26	1		T7	2
valid_sources[0x0c]	1199	1			T2	1		T3	15		T7	2
valid_sources[0x0d]	824	1			T2	2		T26	1		T3	26
valid_sources[0x0e]	1216	1			T2	2		T7	1		T8	5
valid_sources[0x0f]	1871	1			T2	1		T8	2		T10	2
valid_sources[0x10]	900	1			T7	3		T8	2		T10	2
valid_sources[0x11]	967	1			T2	6		T7	4		T8	1
valid_sources[0x12]	964	1			T2	6		T3	8		T7	2
valid_sources[0x13]	1038	1			T2	2		T26	1		T7	7
valid_sources[0x14]	1760	1			T2	2		T26	1		T3	3
valid_sources[0x15]	856	1			T2	4		T8	1		T9	12
valid_sources[0x16]	1273	1			T2	5		T26	1		T8	4
valid_sources[0x17]	715	1			T2	5		T3	10		T7	3
valid_sources[0x18]	1166	1			T2	3		T7	1		T8	5
valid_sources[0x19]	874	1			T2	1		T26	2		T32	4
valid_sources[0x1a]	1087	1			T2	1		T7	3		T8	2
valid_sources[0x1b]	877	1			T2	5		T7	3		T8	2
valid_sources[0x1c]	792	1			T2	3		T26	2		T7	4
valid_sources[0x1d]	1035	1			T5	1		T2	1		T8	2
valid_sources[0x1e]	1178	1			T2	1		T3	7		T7	2
valid_sources[0x1f]	717	1			T2	3		T26	2		T7	3
valid_sources[0x20]	1454	1			T2	3		T7	7		T8	6
valid_sources[0x21]	1120	1			T2	2		T26	1		T7	2
valid_sources[0x22]	848	1			T2	4		T7	5		T32	1
valid_sources[0x23]	1556	1			T25	3		T2	1		T26	2
valid_sources[0x24]	963	1			T2	2		T7	2		T8	3
valid_sources[0x25]	1146	1			T3	1		T7	1		T8	3
valid_sources[0x26]	1091	1			T2	4		T26	1		T3	8
valid_sources[0x27]	897	1			T2	3		T26	2		T7	1
valid_sources[0x28]	842	1			T2	1		T26	2		T7	3
valid_sources[0x29]	978	1			T2	1		T26	1		T3	7
valid_sources[0x2a]	2179	1			T25	2		T2	1		T3	19
valid_sources[0x2b]	1922	1			T5	1		T2	6		T3	1
valid_sources[0x2c]	976	1			T2	3		T7	2		T8	4
valid_sources[0x2d]	962	1			T25	2		T2	4		T26	2
valid_sources[0x2e]	1078	1			T25	1		T3	4		T7	3
valid_sources[0x2f]	980	1			T2	4		T3	23		T7	4
valid_sources[0x30]	975	1			T2	3		T8	2		T9	6
valid_sources[0x31]	972	1			T5	1		T2	1		T26	2
valid_sources[0x32]	902	1			T2	4		T7	5		T8	3
valid_sources[0x33]	922	1			T2	6		T7	2		T8	2
valid_sources[0x34]	783	1			T2	3		T7	2		T8	3
valid_sources[0x35]	900	1			T2	1		T26	2		T3	5
valid_sources[0x36]	914	1			T2	3		T3	3		T7	4
valid_sources[0x37]	1241	1			T2	1		T3	7		T7	3
valid_sources[0x38]	1151	1			T2	2		T8	4		T10	3
valid_sources[0x39]	1119	1			T2	2		T7	2		T8	1
valid_sources[0x3a]	861	1			T5	1		T2	2		T7	3
valid_sources[0x3b]	1008	1			T25	1		T2	1		T26	1
valid_sources[0x3c]	1058	1			T2	4		T7	2		T8	6
valid_sources[0x3d]	1061	1			T2	5		T7	2		T8	2
valid_sources[0x3e]	960	1			T2	2		T3	8		T7	3
valid_sources[0x3f]	801	1			T2	1		T26	1		T7	4
valid_sources[0x40]	1007	1			T2	3		T26	1		T7	2
valid_sources[0x41]	975	1			T2	4		T26	1		T3	1
valid_sources[0x42]	1093	1			T2	4		T26	1		T7	2
valid_sources[0x43]	1000	1			T2	4		T27	4		T7	3
valid_sources[0x44]	847	1			T25	1		T2	2		T26	1
valid_sources[0x45]	1160	1			T25	1		T2	1		T3	28
valid_sources[0x46]	1001	1			T3	6		T7	2		T8	1
valid_sources[0x47]	1105	1			T2	2		T7	2		T8	1
valid_sources[0x48]	1319	1			T2	2		T26	1		T3	10
valid_sources[0x49]	868	1			T2	8		T26	2		T7	4
valid_sources[0x4a]	1060	1			T26	2		T8	2		T10	2
valid_sources[0x4b]	1047	1			T2	2		T26	2		T3	26
valid_sources[0x4c]	968	1			T25	1		T2	3		T7	3
valid_sources[0x4d]	871	1			T2	4		T7	3		T8	2
valid_sources[0x4e]	875	1			T2	2		T3	8		T9	2
valid_sources[0x4f]	964	1			T2	4		T26	1		T3	13
valid_sources[0x50]	1114	1			T25	1		T2	3		T7	5
valid_sources[0x51]	806	1			T2	1		T7	3		T8	1
valid_sources[0x52]	931	1			T2	3		T7	2		T8	2
valid_sources[0x53]	793	1			T2	3		T26	1		T8	1
valid_sources[0x54]	981	1			T2	3		T7	1		T8	5
valid_sources[0x55]	922	1			T25	1		T2	2		T7	3
valid_sources[0x56]	826	1			T2	3		T7	1		T8	1
valid_sources[0x57]	1000	1			T5	1		T2	1		T3	25
valid_sources[0x58]	1714	1			T2	1		T26	2		T7	5
valid_sources[0x59]	2238	1			T2	4		T3	14		T7	1
valid_sources[0x5a]	819	1			T6	43		T2	4		T3	22
valid_sources[0x5b]	1173	1			T2	3		T3	2		T7	2
valid_sources[0x5c]	973	1			T2	1		T26	1		T7	1
valid_sources[0x5d]	997	1			T2	2		T7	2		T8	1
valid_sources[0x5e]	1666	1			T2	6		T7	2		T8	3
valid_sources[0x5f]	1004	1			T2	3		T7	6		T8	1
valid_sources[0x60]	1797	1			T2	4		T3	32		T7	2
valid_sources[0x61]	1804	1			T2	5		T3	1		T7	2
valid_sources[0x62]	742	1			T2	2		T26	1		T3	2
valid_sources[0x63]	1130	1			T2	6		T3	17		T7	3
valid_sources[0x64]	918	1			T5	1		T2	2		T26	1
valid_sources[0x65]	1548	1			T25	5		T7	3		T8	4
valid_sources[0x66]	826	1			T2	4		T7	4		T8	3
valid_sources[0x67]	1427	1			T2	2		T3	6		T7	4
valid_sources[0x68]	866	1			T2	3		T8	4		T9	4
valid_sources[0x69]	1471	1			T25	3		T2	1		T3	8
valid_sources[0x6a]	794	1			T2	2		T26	2		T7	5
valid_sources[0x6b]	686	1			T7	3		T8	1		T9	19
valid_sources[0x6c]	884	1			T2	3		T26	1		T7	4
valid_sources[0x6d]	1401	1			T2	4		T3	11		T7	2
valid_sources[0x6e]	1056	1			T2	3		T3	29		T7	6
valid_sources[0x6f]	779	1			T2	2		T26	1		T3	6
valid_sources[0x70]	1128	1			T2	3		T7	6		T8	1
valid_sources[0x71]	1925	1			T2	4		T7	2		T8	3
valid_sources[0x72]	1026	1			T2	5		T26	1		T28	15
valid_sources[0x73]	1054	1			T2	4		T7	2		T8	4
valid_sources[0x74]	1141	1			T26	1		T7	2		T8	3
valid_sources[0x75]	957	1			T2	4		T26	1		T3	1
valid_sources[0x76]	1850	1			T2	2		T7	4		T30	7
valid_sources[0x77]	907	1			T5	1		T1	17		T2	2
valid_sources[0x78]	1117	1			T2	2		T7	3		T10	2
valid_sources[0x79]	1142	1			T2	4		T7	4		T8	1
valid_sources[0x7a]	1310	1			T7	1		T8	6		T9	3
valid_sources[0x7b]	1041	1			T25	1		T2	4		T3	20
valid_sources[0x7c]	760	1			T2	2		T3	11		T7	1
valid_sources[0x7d]	1282	1			T2	1		T3	4		T7	2
valid_sources[0x7e]	1012	1			T5	1		T2	2		T26	1
valid_sources[0x7f]	1353	1			T2	2		T7	1		T8	5
valid_sources[0x80]	807	1			T2	2		T7	1		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66452

1

T4

32

T5

9

T6

19

values[0x0]

all_enables

biggest_size

34010

1

T4

20

T1

3

T25

8

values[0x1]

all_enables

biggest_size

24085

1

T4

16

T1

1

T25

4