Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T28,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T28,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T28,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T28,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T28,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T28,T10
0	1	Covered	T95,T125,T126
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T28,T10
0	1	Covered	T2,T28,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T28,T10
1	-	Covered	T2,T28,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T28,T10
DetectSt	168	Covered	T2,T28,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T28,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T28,T10
DebounceSt->IdleSt	163	Covered	T10,T61,T65
DetectSt->IdleSt	186	Covered	T95,T125,T126
DetectSt->StableSt	191	Covered	T2,T28,T10
IdleSt->DebounceSt	148	Covered	T2,T28,T10
StableSt->IdleSt	206	Covered	T2,T28,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T28,T10
0	1	Covered	T2,T28,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T28,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T28,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T28,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T61,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T28,T10
DetectSt	-	-	-	-	1	-	-	Covered	T95,T125,T126
DetectSt	-	-	-	-	0	1	-	Covered	T2,T28,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T28,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T28,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	269	0	0
CntIncr_A	9116158	19888	0	0
CntNoWrap_A	9116158	8448289	0	0
DetectStDropOut_A	9116158	3	0	0
DetectedOut_A	9116158	780	0	0
DetectedPulseOut_A	9116158	119	0	0
DisabledIdleSt_A	9116158	8422285	0	0
DisabledNoDetection_A	9116158	8424642	0	0
EnterDebounceSt_A	9116158	152	0	0
EnterDetectSt_A	9116158	122	0	0
EnterStableSt_A	9116158	119	0	0
PulseIsPulse_A	9116158	119	0	0
StayInStableSt	9116158	661	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9116158	6991	0	0
gen_low_level_sva.LowLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	119	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	269	0	0
T2	27744	4	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	7	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	4	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	2	0	0
T43	0	2	0	0
T61	0	3	0	0
T62	0	2	0	0
T64	0	2	0	0
T65	0	3	0	0
T105	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	19888	0	0
T2	27744	115	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	298	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	166	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	77	0	0
T43	0	52	0	0
T61	0	82	0	0
T62	0	28	0	0
T64	0	79	0	0
T65	0	58	0	0
T105	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448289	0	0
T1	215137	214736	0	0
T2	27744	25681	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	363	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	3	0	0
T95	3548	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T129	766	0	0	0
T130	550	0	0	0
T131	13540	0	0	0
T132	1280	0	0	0
T133	51926	0	0	0
T134	406	0	0	0
T135	1936	0	0	0
T136	15751	0	0	0
T137	566	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	780	0	0
T2	27744	6	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	20	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	9	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	6	0	0
T43	0	8	0	0
T61	0	5	0	0
T62	0	8	0	0
T64	0	6	0	0
T65	0	2	0	0
T105	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	119	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	2	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T105	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8422285	0	0
T1	215137	214736	0	0
T2	27744	25491	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	110	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8424642	0	0
T1	215137	214737	0	0
T2	27744	25504	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	110	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	152	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	4	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	2	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T105	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	122	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	2	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T105	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	119	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	2	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T105	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	119	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	2	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T105	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	661	0	0
T2	27744	4	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	17	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	7	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	5	0	0
T43	0	7	0	0
T61	0	4	0	0
T62	0	7	0	0
T64	0	5	0	0
T65	0	1	0	0
T105	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6991	0	0
T1	215137	1	0	0
T2	27744	17	0	0
T3	17023	28	0	0
T4	2290	11	0	0
T5	419	2	0	0
T6	444	4	0	0
T7	0	13	0	0
T25	492	7	0	0
T26	507	5	0	0
T27	405	0	0	0
T28	768	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	119	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	2	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T105	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T14,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T14,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T15,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T15
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T14,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T15,T41
0	1	Covered	T11,T103,T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T15,T41
0	1	Unreachable
1	0	Covered	T11,T15,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T14,T15
DetectSt	168	Covered	T11,T15,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T15,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T15,T41
DebounceSt->IdleSt	163	Covered	T11,T14,T39
DetectSt->IdleSt	186	Covered	T11,T103,T104
DetectSt->StableSt	191	Covered	T11,T15,T41
IdleSt->DebounceSt	148	Covered	T11,T14,T15
StableSt->IdleSt	206	Covered	T11,T15,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T14,T15
0	1	Covered	T11,T14,T15
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T15,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T14,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T15,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T14,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T14,T15
DetectSt	-	-	-	-	1	-	-	Covered	T11,T103,T104
DetectSt	-	-	-	-	0	1	-	Covered	T11,T15,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T15,T41
StableSt	-	-	-	-	-	-	0	Covered	T11,T15,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	202	0	0
CntIncr_A	9116158	56116	0	0
CntNoWrap_A	9116158	8448356	0	0
DetectStDropOut_A	9116158	14	0	0
DetectedOut_A	9116158	339171	0	0
DetectedPulseOut_A	9116158	68	0	0
DisabledIdleSt_A	9116158	6956500	0	0
DisabledNoDetection_A	9116158	6958914	0	0
EnterDebounceSt_A	9116158	120	0	0
EnterDetectSt_A	9116158	82	0	0
EnterStableSt_A	9116158	68	0	0
PulseIsPulse_A	9116158	68	0	0
StayInStableSt	9116158	339103	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9116158	6991	0	0
gen_low_level_sva.LowLevelEvent_A	9116158	8450973	0	0
gen_sticky_sva.StableStDropOut_A	9116158	477296	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	202	0	0
T11	1537	9	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	2	0	0
T15	0	4	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	6	0	0
T71	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	56116	0	0
T11	1537	485	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	162	0	0
T15	0	128	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	39	0	0
T40	0	44	0	0
T41	0	41	0	0
T42	0	85	0	0
T43	0	96	0	0
T44	0	66	0	0
T71	0	410	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448356	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	14	0	0
T11	1537	3	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T100	0	2	0	0
T103	0	2	0	0
T104	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	339171	0	0
T11	1537	293	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	0	719	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T41	0	136	0	0
T42	0	252	0	0
T43	0	39	0	0
T44	0	317	0	0
T45	0	32	0	0
T139	0	60	0	0
T140	0	48	0	0
T142	0	216	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	68	0	0
T11	1537	1	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6956500	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6958914	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	120	0	0
T11	1537	5	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	2	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T71	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	82	0	0
T11	1537	4	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	68	0	0
T11	1537	1	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	68	0	0
T11	1537	1	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	339103	0	0
T11	1537	292	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	0	717	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T41	0	135	0	0
T42	0	251	0	0
T43	0	38	0	0
T44	0	314	0	0
T45	0	31	0	0
T139	0	59	0	0
T140	0	47	0	0
T142	0	214	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6991	0	0
T1	215137	1	0	0
T2	27744	17	0	0
T3	17023	28	0	0
T4	2290	11	0	0
T5	419	2	0	0
T6	444	4	0	0
T7	0	13	0	0
T25	492	7	0	0
T26	507	5	0	0
T27	405	0	0	0
T28	768	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	477296	0	0
T11	1537	75	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	0	408	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T41	0	143	0	0
T42	0	50	0	0
T43	0	51	0	0
T44	0	759	0	0
T45	0	121	0	0
T139	0	397	0	0
T140	0	86	0	0
T142	0	143	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T14,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T14,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T14,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T15
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T14,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T14,T15
0	1	Covered	T11,T102,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T14,T15
0	1	Unreachable
1	0	Covered	T11,T14,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T14,T15
DetectSt	168	Covered	T11,T14,T15
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T14,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T14,T15
DebounceSt->IdleSt	163	Covered	T11,T41,T43
DetectSt->IdleSt	186	Covered	T11,T102,T87
DetectSt->StableSt	191	Covered	T11,T14,T15
IdleSt->DebounceSt	148	Covered	T11,T14,T15
StableSt->IdleSt	206	Covered	T11,T14,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T14,T15
0	1	Covered	T11,T14,T15
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T15
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T14,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T14,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T41,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T14,T15
DetectSt	-	-	-	-	1	-	-	Covered	T11,T102,T87
DetectSt	-	-	-	-	0	1	-	Covered	T11,T14,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T14,T15
StableSt	-	-	-	-	-	-	0	Covered	T11,T14,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	214	0	0
CntIncr_A	9116158	235854	0	0
CntNoWrap_A	9116158	8448344	0	0
DetectStDropOut_A	9116158	16	0	0
DetectedOut_A	9116158	862022	0	0
DetectedPulseOut_A	9116158	54	0	0
DisabledIdleSt_A	9116158	6956500	0	0
DisabledNoDetection_A	9116158	6958914	0	0
EnterDebounceSt_A	9116158	144	0	0
EnterDetectSt_A	9116158	70	0	0
EnterStableSt_A	9116158	54	0	0
PulseIsPulse_A	9116158	54	0	0
StayInStableSt	9116158	861968	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_sticky_sva.StableStDropOut_A	9116158	10661	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	214	0	0
T11	1537	11	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	2	0	0
T15	0	4	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	10	0	0
T71	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	235854	0	0
T11	1537	270	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	33	0	0
T15	0	178	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	47	0	0
T40	0	62	0	0
T41	0	114	0	0
T42	0	62	0	0
T43	0	16	0	0
T44	0	960	0	0
T71	0	265	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448344	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	16	0	0
T11	1537	3	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T87	0	3	0	0
T102	0	2	0	0
T143	0	1	0	0
T146	0	3	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	862022	0	0
T11	1537	94	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	66	0	0
T15	0	472	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	102	0	0
T40	0	4	0	0
T41	0	116	0	0
T42	0	86	0	0
T139	0	55	0	0
T140	0	83	0	0
T142	0	227	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T11	1537	2	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	1	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6956500	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6958914	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	144	0	0
T11	1537	6	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	1	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	10	0	0
T71	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	70	0	0
T11	1537	5	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	1	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T11	1537	2	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	1	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T11	1537	2	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	1	0	0
T15	0	2	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	861968	0	0
T11	1537	92	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	65	0	0
T15	0	470	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	101	0	0
T40	0	3	0	0
T41	0	115	0	0
T42	0	85	0	0
T139	0	54	0	0
T140	0	82	0	0
T142	0	225	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	10661	0	0
T11	1537	287	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	118	0	0
T15	0	618	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	78	0	0
T40	0	30	0	0
T41	0	75	0	0
T42	0	242	0	0
T139	0	387	0	0
T140	0	40	0	0
T142	0	162	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T14,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T14,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T39,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T15
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T14,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T39,T41
0	1	Covered	T42,T71,T99
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T39,T41
0	1	Unreachable
1	0	Covered	T11,T39,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T14,T15
DetectSt	168	Covered	T11,T39,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T39,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T39,T41
DebounceSt->IdleSt	163	Covered	T14,T15,T40
DetectSt->IdleSt	186	Covered	T42,T71,T99
DetectSt->StableSt	191	Covered	T11,T39,T41
IdleSt->DebounceSt	148	Covered	T11,T14,T15
StableSt->IdleSt	206	Covered	T11,T39,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T14,T15
0	1	Covered	T11,T14,T15
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T39,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T14,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T39,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T15,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T14,T15
DetectSt	-	-	-	-	1	-	-	Covered	T42,T71,T99
DetectSt	-	-	-	-	0	1	-	Covered	T11,T39,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T39,T41
StableSt	-	-	-	-	-	-	0	Covered	T11,T39,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	221	0	0
CntIncr_A	9116158	7490	0	0
CntNoWrap_A	9116158	8448337	0	0
DetectStDropOut_A	9116158	26	0	0
DetectedOut_A	9116158	9279	0	0
DetectedPulseOut_A	9116158	54	0	0
DisabledIdleSt_A	9116158	6956500	0	0
DisabledNoDetection_A	9116158	6958914	0	0
EnterDebounceSt_A	9116158	141	0	0
EnterDetectSt_A	9116158	80	0	0
EnterStableSt_A	9116158	54	0	0
PulseIsPulse_A	9116158	54	0	0
StayInStableSt	9116158	9225	0	0
gen_high_event_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_sticky_sva.StableStDropOut_A	9116158	1457206	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	221	0	0
T11	1537	4	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	2	0	0
T15	0	7	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	6	0	0
T71	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	7490	0	0
T11	1537	56	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	114	0	0
T15	0	581	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	28	0	0
T40	0	58	0	0
T41	0	30	0	0
T42	0	42	0	0
T43	0	90	0	0
T44	0	117	0	0
T71	0	215	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448337	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	26	0	0
T16	21770	0	0	0
T17	783	0	0	0
T18	32165	0	0	0
T42	829	1	0	0
T71	0	5	0	0
T99	0	1	0	0
T104	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T127	503	0	0	0
T132	0	3	0	0
T144	0	1	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	9279	0	0
T11	1537	212	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	104	0	0
T41	0	106	0	0
T43	0	64	0	0
T44	0	483	0	0
T45	0	44	0	0
T139	0	362	0	0
T140	0	34	0	0
T141	0	480	0	0
T142	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T11	1537	2	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6956500	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6958914	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	141	0	0
T11	1537	2	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	2	0	0
T15	0	7	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	3	0	0
T71	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	80	0	0
T11	1537	2	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T71	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T11	1537	2	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T11	1537	2	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	9225	0	0
T11	1537	210	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	103	0	0
T41	0	105	0	0
T43	0	63	0	0
T44	0	480	0	0
T45	0	43	0	0
T139	0	361	0	0
T140	0	33	0	0
T141	0	479	0	0
T142	0	104	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1457206	0	0
T11	1537	690	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T33	5966	0	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T39	0	95	0	0
T41	0	204	0	0
T43	0	33	0	0
T44	0	578	0	0
T45	0	124	0	0
T139	0	40	0	0
T140	0	110	0	0
T141	0	387	0	0
T142	0	323	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T20,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T17,T20,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T20,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T20,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T17,T20,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T20,T22
0	1	Covered	T22,T58,T57
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T20,T22
1	-	Covered	T22,T58,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T20,T22
DetectSt	168	Covered	T17,T20,T22
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T17,T20,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T20,T22
DebounceSt->IdleSt	163	Covered	T91,T92
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T17,T20,T22
IdleSt->DebounceSt	148	Covered	T17,T20,T22
StableSt->IdleSt	206	Covered	T20,T22,T58

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T20,T22
0	1	Covered	T17,T20,T22
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T20,T22
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T20,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T20,T22
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T20,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T20,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T58,T57
StableSt	-	-	-	-	-	-	0	Covered	T17,T20,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	68	0	0
CntIncr_A	9116158	1997	0	0
CntNoWrap_A	9116158	8448490	0	0
DetectStDropOut_A	9116158	0	0	0
DetectedOut_A	9116158	2658	0	0
DetectedPulseOut_A	9116158	33	0	0
DisabledIdleSt_A	9116158	8264958	0	0
DisabledNoDetection_A	9116158	8267328	0	0
EnterDebounceSt_A	9116158	35	0	0
EnterDetectSt_A	9116158	33	0	0
EnterStableSt_A	9116158	33	0	0
PulseIsPulse_A	9116158	33	0	0
StayInStableSt	9116158	2606	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	68	0	0
T17	783	2	0	0
T18	32165	0	0	0
T20	0	2	0	0
T22	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	6	0	0
T94	0	2	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1997	0	0
T17	783	38	0	0
T18	32165	0	0	0
T20	0	74	0	0
T22	0	84	0	0
T57	0	22	0	0
T58	0	59	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	282	0	0
T94	0	56	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T154	0	38	0	0
T155	0	24	0	0
T156	0	23	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448490	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2658	0	0
T17	783	104	0	0
T18	32165	0	0	0
T20	0	38	0	0
T22	0	43	0	0
T57	0	58	0	0
T58	0	5	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	150	0	0
T94	0	41	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T154	0	180	0	0
T155	0	37	0	0
T156	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	33	0	0
T17	783	1	0	0
T18	32165	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	3	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8264958	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8267328	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	35	0	0
T17	783	1	0	0
T18	32165	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	3	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	33	0	0
T17	783	1	0	0
T18	32165	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	3	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	33	0	0
T17	783	1	0	0
T18	32165	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	3	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	33	0	0
T17	783	1	0	0
T18	32165	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	3	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2606	0	0
T17	783	102	0	0
T18	32165	0	0	0
T20	0	36	0	0
T22	0	42	0	0
T57	0	57	0	0
T58	0	4	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	147	0	0
T94	0	39	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T154	0	178	0	0
T155	0	35	0	0
T156	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	14	0	0
T22	12721	1	0	0
T43	24485	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T88	0	1	0	0
T93	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	424	0	0	0
T163	996	0	0	0
T164	657	0	0	0
T165	7242	0	0	0
T166	502	0	0	0
T167	679	0	0	0
T168	2263	0	0	0
T169	427	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T12
0	1	Covered	T87,T170,T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T12
0	1	Covered	T10,T12,T20
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T12
1	-	Covered	T10,T12,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T12
DetectSt	168	Covered	T1,T10,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T12
DebounceSt->IdleSt	163	Covered	T154,T93,T91
DetectSt->IdleSt	186	Covered	T87,T170,T171
DetectSt->StableSt	191	Covered	T1,T10,T12
IdleSt->DebounceSt	148	Covered	T1,T10,T12
StableSt->IdleSt	206	Covered	T10,T12,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T12
0	1	Covered	T1,T10,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T154,T93,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T87,T170,T171
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T20
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	126	0	0
CntIncr_A	9116158	125993	0	0
CntNoWrap_A	9116158	8448432	0	0
DetectStDropOut_A	9116158	3	0	0
DetectedOut_A	9116158	195387	0	0
DetectedPulseOut_A	9116158	54	0	0
DisabledIdleSt_A	9116158	8117412	0	0
DisabledNoDetection_A	9116158	8119773	0	0
EnterDebounceSt_A	9116158	69	0	0
EnterDetectSt_A	9116158	57	0	0
EnterStableSt_A	9116158	54	0	0
PulseIsPulse_A	9116158	54	0	0
StayInStableSt	9116158	195308	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9116158	2710	0	0
gen_low_level_sva.LowLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	126	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	2	0	0
T12	0	4	0	0
T20	0	2	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	2	0	0
T55	0	2	0	0
T56	0	4	0	0
T57	0	4	0	0
T58	0	4	0	0
T154	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	125993	0	0
T1	215137	62252	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	79	0	0
T12	0	174	0	0
T20	0	74	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	48	0	0
T55	0	20	0	0
T56	0	176	0	0
T57	0	44	0	0
T58	0	118	0	0
T154	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448432	0	0
T1	215137	214734	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	3	0	0
T87	10791	1	0	0
T104	815	0	0	0
T170	0	1	0	0
T171	0	1	0	0
T173	503	0	0	0
T174	407	0	0	0
T175	673	0	0	0
T176	421	0	0	0
T177	858	0	0	0
T178	36007	0	0	0
T179	98324	0	0	0
T180	13521	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	195387	0	0
T1	215137	152475	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	247	0	0
T12	0	213	0	0
T20	0	51	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	43	0	0
T55	0	102	0	0
T56	0	197	0	0
T57	0	65	0	0
T58	0	85	0	0
T93	0	559	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T20	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T93	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8117412	0	0
T1	215137	3	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8119773	0	0
T1	215137	3	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	69	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T20	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T154	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	57	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T20	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T93	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T20	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T93	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T20	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T93	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	195308	0	0
T1	215137	152473	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	246	0	0
T12	0	210	0	0
T20	0	50	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	41	0	0
T55	0	101	0	0
T56	0	194	0	0
T57	0	62	0	0
T58	0	82	0	0
T93	0	553	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2710	0	0
T1	215137	1	0	0
T2	27744	11	0	0
T3	17023	0	0	0
T4	2290	12	0	0
T5	419	2	0	0
T6	444	8	0	0
T10	0	20	0	0
T25	492	6	0	0
T26	507	5	0	0
T27	405	0	0	0
T28	768	0	0	0
T31	0	6	0	0
T32	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	29	0	0
T10	18817	1	0	0
T12	0	1	0	0
T20	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	2	0	0
T138	417	0	0	0
T181	0	1	0	0
T182	0	1	0	0